git subrepo push emummc

subrepo:
  subdir:   "emummc"
  merged:   "6a814ebb"
upstream:
  origin:   "https://github.com/m4xw/emuMMC"
  branch:   "exo2"
  commit:   "6a814ebb"
git-subrepo:
  version:  "0.4.1"
  origin:   "???"
  commit:   "???"

.gitignore

@@ -31,12 +31,16 @@
 
 # Executables
 *.exe
+*.lz4
 *.out
 *.app
 *.i*86
 *.x86_64
 *.hex
 
+# Deko3d shaders
+*.dksh
+
 # Switch Executables
 *.nso
 *.nro

Makefile

@@ -64,6 +64,7 @@ dist-no-debug: all
 	mkdir -p atmosphere-$(AMSVER)/atmosphere/contents/0100000000000036
 	mkdir -p atmosphere-$(AMSVER)/atmosphere/contents/0100000000000037
 	mkdir -p atmosphere-$(AMSVER)/atmosphere/contents/010000000000003C
+	mkdir -p atmosphere-$(AMSVER)/atmosphere/contents/0100000000000042
 	mkdir -p atmosphere-$(AMSVER)/atmosphere/fatal_errors
 	mkdir -p atmosphere-$(AMSVER)/atmosphere/config_templates
 	mkdir -p atmosphere-$(AMSVER)/atmosphere/config
@@ -80,6 +81,7 @@ dist-no-debug: all
 	cp config_templates/BCT.ini atmosphere-$(AMSVER)/atmosphere/config/BCT.ini
 	cp config_templates/override_config.ini atmosphere-$(AMSVER)/atmosphere/config_templates/override_config.ini
 	cp config_templates/system_settings.ini atmosphere-$(AMSVER)/atmosphere/config_templates/system_settings.ini
+	cp config_templates/exosphere.ini atmosphere-$(AMSVER)/atmosphere/config_templates/exosphere.ini
 	cp -r config_templates/kip_patches atmosphere-$(AMSVER)/atmosphere/kip_patches
 	cp -r config_templates/hbl_html atmosphere-$(AMSVER)/atmosphere/hbl_html
 	cp stratosphere/boot2/boot2.nsp atmosphere-$(AMSVER)/atmosphere/contents/0100000000000008/exefs.nsp
@@ -90,11 +92,13 @@ dist-no-debug: all
 	cp stratosphere/creport/creport.nsp atmosphere-$(AMSVER)/atmosphere/contents/0100000000000036/exefs.nsp
 	cp stratosphere/ro/ro.nsp atmosphere-$(AMSVER)/atmosphere/contents/0100000000000037/exefs.nsp
 	cp stratosphere/jpegdec/jpegdec.nsp atmosphere-$(AMSVER)/atmosphere/contents/010000000000003C/exefs.nsp
+	cp stratosphere/pgl/pgl.nsp atmosphere-$(AMSVER)/atmosphere/contents/0100000000000042/exefs.nsp
 	mkdir -p atmosphere-$(AMSVER)/atmosphere/contents/0100000000000032/flags
 	touch atmosphere-$(AMSVER)/atmosphere/contents/0100000000000032/flags/boot2.flag
 	mkdir -p atmosphere-$(AMSVER)/atmosphere/contents/0100000000000037/flags
 	touch atmosphere-$(AMSVER)/atmosphere/contents/0100000000000037/flags/boot2.flag
 	cp troposphere/reboot_to_payload/reboot_to_payload.nro atmosphere-$(AMSVER)/switch/reboot_to_payload.nro
+	cp troposphere/daybreak/daybreak.nro atmosphere-$(AMSVER)/switch/daybreak.nro
 	cd atmosphere-$(AMSVER); zip -r ../atmosphere-$(AMSVER).zip ./*; cd ../;
 	rm -r atmosphere-$(AMSVER)
 	mkdir out
@@ -120,10 +124,11 @@ dist: dist-no-debug
 	cp sept/sept-primary/sept-primary.elf atmosphere-$(AMSVER)-debug/sept-primary.elf
 	cp sept/sept-secondary/sept-secondary.elf atmosphere-$(AMSVER)-debug/sept-secondary.elf
 	cp sept/sept-secondary/key_derivation/key_derivation.elf atmosphere-$(AMSVER)-debug/sept-secondary-key-derivation.elf
-	cp exosphere/exosphere.elf atmosphere-$(AMSVER)-debug/exosphere.elf
-	cp exosphere/lp0fw/lp0fw.elf atmosphere-$(AMSVER)-debug/lp0fw.elf
-	cp exosphere/sc7fw/sc7fw.elf atmosphere-$(AMSVER)-debug/sc7fw.elf
-	cp exosphere/rebootstub/rebootstub.elf atmosphere-$(AMSVER)-debug/rebootstub.elf
+	cp exosphere/loader_stub/loader_stub.elf atmosphere-$(AMSVER)-debug/exosphere-loader-stub.elf
+	cp exosphere/program/program.elf atmosphere-$(AMSVER)-debug/exosphere-program.elf
+	cp exosphere/warmboot/warmboot.elf atmosphere-$(AMSVER)-debug/exosphere-warmboot.elf
+	cp exosphere/program/sc7fw/sc7fw.elf atmosphere-$(AMSVER)-debug/exosphere-sc7fw.elf
+	cp exosphere/program/rebootstub/rebootstub.elf atmosphere-$(AMSVER)-debug/exosphere-rebootstub.elf
 	cp mesosphere/kernel_ldr/kernel_ldr.elf atmosphere-$(AMSVER)-debug/kernel_ldr.elf
 	cp stratosphere/ams_mitm/ams_mitm.elf atmosphere-$(AMSVER)-debug/ams_mitm.elf
 	cp stratosphere/boot/boot.elf atmosphere-$(AMSVER)-debug/boot.elf
@@ -139,6 +144,8 @@ dist: dist-no-debug
 	cp stratosphere/spl/spl.elf atmosphere-$(AMSVER)-debug/spl.elf
 	cp stratosphere/erpt/erpt.elf atmosphere-$(AMSVER)-debug/erpt.elf
 	cp stratosphere/jpegdec/jpegdec.elf atmosphere-$(AMSVER)-debug/jpegdec.elf
+	cp stratosphere/pgl/pgl.elf atmosphere-$(AMSVER)-debug/pgl.elf
+	cp troposphere/daybreak/daybreak.elf atmosphere-$(AMSVER)-debug/daybreak.elf
 	cd atmosphere-$(AMSVER)-debug; zip -r ../atmosphere-$(AMSVER)-debug.zip ./*; cd ../;
 	rm -r atmosphere-$(AMSVER)-debug
 	mv atmosphere-$(AMSVER)-debug.zip out/atmosphere-$(AMSVER)-debug.zip

config_templates/system_settings.ini

@@ -4,7 +4,7 @@
 ; Control whether RO should ease its validation of NROs.
 ; (note: this is normally not necessary, and ips patches can be used.)
 [ro]
-; ease_nro_restriction = u8!0x0
+; ease_nro_restriction = u8!0x1
 ; Atmosphere custom settings
 [atmosphere]
 ; Reboot from fatal automatically after some number of milliseconds.

docs/changelog.md

@@ -1,4 +1,73 @@
 # Changelog
+## 0.14.3
++ Support was added for 10.2.0.
++ General system stability improvements to enhance the user's experience.
+## 0.14.2
++ A bug was fixed that could cause a deadlock when installing mitm services.
+  + Fixing this required a breaking change to the client behavior when installing a mitm service, and so custom sysmodules which use mitm will need to be re-compiled to function properly.
++ A bug was fixed that caused atmosphere sysmodules to respond incorrectly when receiving invalid messages.
++ A bug was fixed that caused fatal auto-reboot timing to work improperly.
++ Support was added to fusee for loading binaries for `mesosphere`, atmosphère's reimplementation of the Nintendo Switch kernel.
+  + 0.14.2 does not include mesosphere, but those who are especially interested can build and test mesosphere themselves.
+  + In the future, to enable a sufficient testing period Atmosphère releases will distribute two zips for some time.
+    + One zip will use mesosphere, and the other will not.
+    + This will allow users who are interested to opt-in to mesosphere usage before it has been tested to be stable.
+  + When mesosphere is stable and well-tested, it will be enabled by default and Atmosphère's version will transition to 1.0.0.
++ General system stability improvements to enhance the user's experience.
+## 0.14.1
++ An issue was fixed in 0.14.0 that would cause a black screen on boot when the INI1's size was not aligned to 8 bytes.
++ General system stability improvements to enhance the user's experience.
+## 0.14.0
++ An API (`ams:su`) was added to allow homebrew to safely install system upgrades or downgrades.
+  + This is a re-implementation of the logic that `ns` uses to install gamecard system updates.
+  + Nintendo (and now atmosphère) uses an installation process that can recover no matter where a failure occurs, which should significantly improve the safety of custom system update installation.
++ Support was added to `exosphère` for running on Mariko hardware.
+  + **Please note**: Atmosphère still does not support Mariko, and should not be run on Mariko yet.
+    + Certain stratosphere components do not handle mariko-specific logic fully correctly yet, and may initialize or interact with hardware incorrectly.
+    + This will be fixed and support will be added over the remainder of the Summer.
++ A homebrew application (`daybreak`) was added that uses the system updater API (with thanks to @Adubbz for both design and implementation).
+  + `daybreak` is included with atmosphère, and functions as a safer/more accurate equivalent to e.g. ChoiDujourNX.
+  + Upgrades/downgrades can be installed from a folder containing the update NCAs on the SD card.
+  + Because the update logic functions identically to Nintendo's, `daybreak` will be safe to use on Mariko when the rest of atmosphère has support.
+  + **Please note**: Daybreak requires that meta (.cnmt) NCAs have the correct extension `.cnmt.nca`.
+    + This is because gamecard system update logic uses extension to determine whether to mount the content.
+    + [Several](https://gist.github.com/HookedBehemoth/df36b5970e1c5b1b512ec7bdd9043c6e) [scripts](https://gist.github.com/antiKk/279966c27fdfd9c7fe63b4ae410f89c4) have been made by community members to automatically rename folders with incorrect extensions.
++ A bug was fixed that would cause file-based emummc to throw an error (showing a hexdump) on boot.
+  + Major thanks to @hexkyz for tracking down and resolving this.
++ A number of minor issues were resolved, including:
+  + fusee now prints information to the screen when an error occurs, instead of getting stuck trying to initialize the display.
+  + A race condition in Horizon was worked around that could prevent boot under certain circumstances.
+  + A bug was fixed that would cause atmosphère modules to open ten copies of certain filesystems instead of one.
+    + This could cause object exhaustion under certain circumstances.
++ For those interested in atmosphère's future development plans, the project's [roadmap](https://github.com/Atmosphere-NX/Atmosphere/blob/ac9832c5ce7be5832f6d29f6564a9c03e7efd22f/docs/roadmap.md) was updated.
++ General system stability improvements to enhance the user's experience.
+## 0.13.0
++ `exosphère`, atmosphère's secure monitor re-implementation, was completely re-written.
+  + `exosphère` was the first component authored for the project in early 2018. It is written in C, and in a style very different from the rest of atmosphère's code.
+    + This has made the codebase difficult to maintain as time has gone on.
+  + `exosphère` was also written to conform to constraints and assumptions that simply no longer apply when cfw is not launched from the web browser, and when warmboothax is possible.
+  + Even beyond these issues, `exosphère` used all but 1KB of the 64KB of space available to it. This was a problem for a few reasons:
+    + Each new system update added requires additional space to support (to add new keys and reflect various changes); 10.0.0 support used up 3 of the 4KB we had left.
+    + atmosphère will want to have software support for mariko hardware, and this is not possible to fit in 1 KB.
+  + The `exosphère` rewrite (which was codenamed `exosphère2` during development) solves these problems.
+  + The new codebase is C++20 written in atmosphère's style.
+    + This solves the maintainability problem, and should make understanding how the secure monitor works *much* easier for those interested in using the code as a reference implementation.
+  + In addition, the new implementation currently uses ~59.5 of the 64KB available.
+    + Several potential code changes are planned that can save/grant access to an additional ~2-3 KB if needed.
+      + Unlike the first codebase, the new `exosphère` actually already has space allocated for future keys/etc. It is currently expected that the reserved space will never be required.
+    + The previous implementation chose not to implement a number of "unimportant" secure monitor functions due to space concerns. The new code has enough breathing room that it can implement them without worries. :)
+  + Finally, the groundwork for mariko support has been laid -- there are only a few minor changes needed for the new secure monitor implementation to work on both erista and mariko hardware.
+    + **Please note**: `exosphère` is only one of many components, and many more need changes to support running on mariko hardware.
+      + Software-side support for executing on mariko hardware is expected some time during Summer 2020, though it should also be noted that this is not a hard deadline.
+  + **Please note**: The new `exosphère` binary is not abi-compatible with the old one. Users who boot using hekate should wait for it to update before running 0.13.0 (or boot fusee-primary via hekate).
++ atmosphère's api for target firmware was changed. All minor/micro system versions are now recognized, instead of only major versions.
+  + This was required in order to support firmware version 5.1.0, which made breaking changes to certain IPC APIs that caused atmosphère 0.12.0 to abort.
+  + **Please note**: this is (unavoidably) a breaking change. System modules using atmosphere-libs will need to update to understand what firmware version they are running.
++ `emummc` was updated to include the new changes.
+  + `emummc` now uses an updated/improved/faster SDMMC driver.
+  + File-based emummc is now almost as fast as raw partition-based emummc.
++ For those interested in atmosphère's future development plans, the project's [roadmap](https://github.com/Atmosphere-NX/Atmosphere/blob/f68d33b70aed8954cc2c539e5934bcaf37ba51da/docs/roadmap.md) was updated.
++ General system stability improvements to enhance the user's experience.
 
 ## 0.12.0
 + Configuration for exosphere was moved to sd:/exosphere.ini.

docs/roadmap.md

@@ -1,12 +1,12 @@
 # Planned Features
 atmosphère has a number of features that are either works-in-progress or planned. Please note that while time-estimates are given, they are loose, and things may be completed sooner or later than advertised.
 
-The following descriptions were last updated in late April of 2020.
+The following descriptions were last updated on July 7th, 2020.
 
-## system updater api
-* **Description**: A planned extension api for stratosphere (tenatively `ams:su`), this will provide an interface for homebrew to safely install system upgrades or downgrades. This will allow for much more easily transitioning safely between different versions of the operating system.
-* **Development Status**: Under active development by SciresM
-* **Estimated Time**: May 2020
+## ams-on-mariko
+* **Description**: Atmosphere cannot run as-is on Mariko hardware. A large number of changes are needed in many components. Although secure monitor support is complete in exosphere, additional work is needed on the bootloader and stratosphere sides as well. Mariko support will also require further design thought; atmosphere's debugging design heavily relies on reboot-to-payload and (more generally) the ability to perform warmboot bootrom hax at will. This is not possible on Mariko, and will require a new design/software support for whatever solution is chosen.
+* **Development Status**: Planned.
+* **Estimated Time**: Summer 2020
 
 ## settings reimplementation
 * **Description**: A planned reimplementation of the settings system module, and with it a removal of the settings mitm. This will greatly simplify atmosphère's boot process, and will allow much more flexible control over the various system settings.
@@ -15,14 +15,9 @@ The following descriptions were last updated in late April of 2020.
 
 ## mesosphere
 * **Description**: mesosphère is a reimplementation of the Horizon operating system's Kernel. It aims to provide an open-source reference for Nintendo's code.
-* **Development Status**: Under semi-active development by SciresM; temporarily on pause while the System Updater API is completed.
+* **Development Status**: Under active development by SciresM.
 * **Estimated Time**: Mid-to-Late 2020
 
-## exosphere re-write
-* **Description**: exosphère, atmosphère's reimplementation of Horizon's Secure Monitor, was the first component authored for the project in early 2018. It is written in C, and in a style very different from the rest of atmosphère's code. In addition, exosphère was written to conform to constraints that no longer apply in an environment where it is not launched from the web browser, and where using a custom firmware image to orchestrate wake-from-sleep is possible. exosphère currently uses all but 1 KB of the space available to it, putting it at risk of breaking as future firmware updates are supported. A re-write will solve these issues.
-* **Development Status**: Planned.
-* **Estimated Time**: 2020-2021.
-
 ## tma reimplementation
 * **Description** tma ("target manager agent") is a system module that manages communication between the Switch and a client PC. Atmosphere's implementation will allow homebrew on the switch to communicate with a connected PC to do various operations such as exchanging data or interacting with files. It will also serve as the communicator for Atmosphère's planned debugger. This will also include PC-side software for interacting with the Switch.
 * **Development Status**: Planned. Switch-side code is fully implemented but needs heavy refactoring/rebasing, as the code was originally authored in 2018.
@@ -47,3 +42,21 @@ The following descriptions were last updated in late April of 2020.
 * **Description**: General system stability improvements to enhance the user's experience.
 * **Development Status**: Undergoing active development by all members of the atmosphère team.
 * **Estimated Time**: June 15th.
+
+# Completed features
+
+The following features were previously included under the planned features section and are now complete.
+
+Please note that this is not an exhaustive list of features present in atmosphère, and only serves to indicate what from the above has been completed.
+
+## system updater homebrew
+* **Description**: A user homebrew making use of the new system updater api, so that users can actually use the new api in practice.
+* **Completion Time**: July 2020
+
+## system updater api
+* **Description**: A planned extension api for stratosphere (tenatively `ams:su`), this will provide an interface for homebrew to safely install system upgrades or downgrades. This will allow for much more easily transitioning safely between different versions of the operating system.
+* **Completion Time**: June 2020
+
+## exosphere re-write
+* **Description**: exosphère, atmosphère's reimplementation of Horizon's Secure Monitor, was the first component authored for the project in early 2018. It is written in C, and in a style very different from the rest of atmosphère's code. In addition, exosphère was written to conform to constraints that no longer apply in an environment where it is not launched from the web browser, and where using a custom firmware image to orchestrate wake-from-sleep is possible. exosphère currently uses all but 1 KB of the space available to it, putting it at risk of breaking as future firmware updates are supported. A re-write will solve these issues.
+* **Completion Time**: June 2020

emummc/.gitrepo

@@ -5,8 +5,8 @@
 ;
 [subrepo]
 	remote = https://github.com/m4xw/emuMMC
-	branch = develop
-	commit = 292a8ad42c8e9f4c9a474b46a5a3190398581131
-	parent = 491ba8fdcfd39a503bedd21b282991fc19aec7d4
+	branch = exo2
+	commit = 6a814ebbe72cf5245b863b9edea9cd3801437a12
+	parent = f551ca4461a79908c37307db10cd8cacf8b98f17
 	method = rebase
 	cmdver = 0.4.1

emummc/Makefile

@@ -21,9 +21,10 @@ include $(DEVKITPRO)/libnx/switch_rules
 
 ARCH	:=	-march=armv8-a -mtune=cortex-a57 -mtp=soft -fPIE
 
-DEFINES := -DINNER_HEAP_SIZE=0x80000
+# Current max usage is 0x4600. (512 * 34 FatFS file objects + 1 fsync buffer).
+DEFINES := -DINNER_HEAP_SIZE=0x8000
 
-CFLAGS	:=	-Wall -O2 -ffunction-sections -Wno-unused-function \
+CFLAGS	:=	-Wall -O2 -ffunction-sections -fdata-sections -Wno-unused-function \
 			$(ARCH) $(DEFINES)
 
 CFLAGS	+=	$(INCLUDE) -D__SWITCH__

emummc/emummc.json

@@ -128,6 +128,8 @@
                 "svcUnmapDeviceAddressSpace": "0x5c",
                 "svcGetSystemInfo": "0x6f",
                 "svcSetProcessMemoryPermission": "0x73",
+                "svcMapProcessMemory": "0x74",
+                "svcUnmapProcessMemory": "0x75",
                 "svcCallSecureMonitor": "0x7f"
             }
         }

emummc/source/FS/FS_offsets.c

@@ -47,6 +47,8 @@
 #include "offsets/910_exfat.h"
 #include "offsets/1000.h"
 #include "offsets/1000_exfat.h"
+#include "offsets/1020.h"
+#include "offsets/1020_exfat.h"
 #include "../utils/fatal.h"
 
 #define GET_OFFSET_STRUCT_NAME(vers) g_offsets##vers
@@ -104,6 +106,8 @@ DEFINE_OFFSET_STRUCT(_910);
 DEFINE_OFFSET_STRUCT(_910_EXFAT);
 DEFINE_OFFSET_STRUCT(_1000);
 DEFINE_OFFSET_STRUCT(_1000_EXFAT);
+DEFINE_OFFSET_STRUCT(_1020);
+DEFINE_OFFSET_STRUCT(_1020_EXFAT);
 
 const fs_offsets_t *get_fs_offsets(enum FS_VER version) {
     switch (version) {
@@ -169,6 +173,10 @@ const fs_offsets_t *get_fs_offsets(enum FS_VER version) {
             return &(GET_OFFSET_STRUCT_NAME(_1000));
         case FS_VER_10_0_0_EXFAT:
             return &(GET_OFFSET_STRUCT_NAME(_1000_EXFAT));
+        case FS_VER_10_2_0:
+            return &(GET_OFFSET_STRUCT_NAME(_1020));
+        case FS_VER_10_2_0_EXFAT:
+            return &(GET_OFFSET_STRUCT_NAME(_1020_EXFAT));
         default:
             fatal_abort(Fatal_UnknownVersion);
     }

emummc/source/FS/FS_versions.h

@@ -68,6 +68,9 @@ enum FS_VER
     FS_VER_10_0_0,
     FS_VER_10_0_0_EXFAT,
 
+    FS_VER_10_2_0,
+    FS_VER_10_2_0_EXFAT,
+
     FS_VER_MAX,
 };
 

emummc/source/FS/offsets/1020.h

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2019 m4xw <m4x@m4xw.net>
+ * Copyright (c) 2019 Atmosphere-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __FS_1020_H__
+#define __FS_1020_H__
+
+// Accessor vtable getters
+#define FS_OFFSET_1020_SDMMC_ACCESSOR_GC   0x14E0F0
+#define FS_OFFSET_1020_SDMMC_ACCESSOR_SD   0x14C200
+#define FS_OFFSET_1020_SDMMC_ACCESSOR_NAND 0x147080
+
+// Hooks
+#define FS_OFFSET_1020_SDMMC_WRAPPER_READ  0x1427E0
+#define FS_OFFSET_1020_SDMMC_WRAPPER_WRITE 0x1428C0
+#define FS_OFFSET_1020_RTLD                0x634
+#define FS_OFFSET_1020_RTLD_DESTINATION    0x9C
+
+#define FS_OFFSET_1020_CLKRST_SET_MIN_V_CLK_RATE 0x141A00
+
+// Misc funcs
+#define FS_OFFSET_1020_LOCK_MUTEX          0x28910
+#define FS_OFFSET_1020_UNLOCK_MUTEX        0x28960
+
+#define FS_OFFSET_1020_SDMMC_WRAPPER_CONTROLLER_CLOSE 0x142740
+
+// Misc Data
+#define FS_OFFSET_1020_SD_MUTEX            0xE273E8
+#define FS_OFFSET_1020_NAND_MUTEX          0xE22DA0
+#define FS_OFFSET_1020_ACTIVE_PARTITION    0xE22DE0
+#define FS_OFFSET_1020_SDMMC_DAS_HANDLE    0xE0AB90
+
+// NOPs
+#define FS_OFFSET_1020_SD_DAS_INIT         0x15214C
+
+// Nintendo Paths
+#define FS_OFFSET_1020_NINTENDO_PATHS \
+{ \
+	{.opcode_reg = 3, .adrp_offset = 0x0006BBA4, .add_rel_offset = 0x00000004}, \
+	{.opcode_reg = 3, .adrp_offset = 0x00078520, .add_rel_offset = 0x00000004}, \
+	{.opcode_reg = 3, .adrp_offset = 0x0007ED0C, .add_rel_offset = 0x00000004}, \
+	{.opcode_reg = 4, .adrp_offset = 0x0009115C, .add_rel_offset = 0x00000004}, \
+	{.opcode_reg = 0, .adrp_offset = 0, .add_rel_offset = 0}, \
+}
+
+#endif // __FS_1020_H__

emummc/source/FS/offsets/1020_exfat.h

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2019 m4xw <m4x@m4xw.net>
+ * Copyright (c) 2019 Atmosphere-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __FS_1020_EXFAT_H__
+#define __FS_1020_EXFAT_H__
+
+// Accessor vtable getters
+#define FS_OFFSET_1020_EXFAT_SDMMC_ACCESSOR_GC   0x14E0F0
+#define FS_OFFSET_1020_EXFAT_SDMMC_ACCESSOR_SD   0x14C200
+#define FS_OFFSET_1020_EXFAT_SDMMC_ACCESSOR_NAND 0x147080
+
+// Hooks
+#define FS_OFFSET_1020_EXFAT_SDMMC_WRAPPER_READ  0x1427E0
+#define FS_OFFSET_1020_EXFAT_SDMMC_WRAPPER_WRITE 0x1428C0
+#define FS_OFFSET_1020_EXFAT_RTLD                0x634
+#define FS_OFFSET_1020_EXFAT_RTLD_DESTINATION    0x9C
+
+#define FS_OFFSET_1020_EXFAT_CLKRST_SET_MIN_V_CLK_RATE 0x141A00
+
+// Misc funcs
+#define FS_OFFSET_1020_EXFAT_LOCK_MUTEX          0x28910
+#define FS_OFFSET_1020_EXFAT_UNLOCK_MUTEX        0x28960
+
+#define FS_OFFSET_1020_EXFAT_SDMMC_WRAPPER_CONTROLLER_CLOSE 0x142740
+
+// Misc Data
+#define FS_OFFSET_1020_EXFAT_SD_MUTEX            0xE353E8
+#define FS_OFFSET_1020_EXFAT_NAND_MUTEX          0xE30DA0
+#define FS_OFFSET_1020_EXFAT_ACTIVE_PARTITION    0xE30DE0
+#define FS_OFFSET_1020_EXFAT_SDMMC_DAS_HANDLE    0xE18B90
+
+// NOPs
+#define FS_OFFSET_1020_EXFAT_SD_DAS_INIT         0x15214C
+
+// Nintendo Paths
+#define FS_OFFSET_1020_EXFAT_NINTENDO_PATHS \
+{ \
+	{.opcode_reg = 3, .adrp_offset = 0x0006BBA4, .add_rel_offset = 0x00000004}, \
+	{.opcode_reg = 3, .adrp_offset = 0x00078520, .add_rel_offset = 0x00000004}, \
+	{.opcode_reg = 3, .adrp_offset = 0x0007ED0C, .add_rel_offset = 0x00000004}, \
+	{.opcode_reg = 4, .adrp_offset = 0x0009115C, .add_rel_offset = 0x00000004}, \
+	{.opcode_reg = 0, .adrp_offset = 0, .add_rel_offset = 0}, \
+}
+
+#endif // __FS_1020_EXFAT_H__

emummc/source/emmc/mmc.h

@@ -31,7 +31,7 @@
 #define MMC_ALL_SEND_CID          2   /* bcr                     R2  */
 #define MMC_SET_RELATIVE_ADDR     3   /* ac   [31:16] RCA        R1  */
 #define MMC_SET_DSR               4   /* bc   [31:16] RCA            */
-#define MMC_SLEEP_AWAKE		  5   /* ac   [31:16] RCA 15:flg R1b */
+#define MMC_SLEEP_AWAKE           5   /* ac   [31:16] RCA 15:flg R1b */
 #define MMC_SWITCH                6   /* ac   [31:0] See below   R1b */
 #define MMC_SELECT_CARD           7   /* ac   [31:16] RCA        R1  */
 #define MMC_SEND_EXT_CSD          8   /* adtc                    R1  */
@@ -51,7 +51,7 @@
 #define MMC_READ_SINGLE_BLOCK    17   /* adtc [31:0] data addr   R1  */
 #define MMC_READ_MULTIPLE_BLOCK  18   /* adtc [31:0] data addr   R1  */
 #define MMC_SEND_TUNING_BLOCK    19   /* adtc                    R1  */
-#define MMC_SEND_TUNING_BLOCK_HS200	21	/* adtc R1  */
+#define MMC_SEND_TUNING_BLOCK_HS200 21	/* adtc R1  */
 
 /* class 3 */
 #define MMC_WRITE_DAT_UNTIL_STOP 20   /* adtc [31:0] data addr   R1  */

emummc/source/emmc/nx_sd.c

@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2019 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "nx_sd.h"
+#include "sdmmc.h"
+#include "sdmmc_driver.h"
+#include "../soc/gpio.h"
+#include "../libs/fatfs/ff.h"
+
+extern sdmmc_t sd_sdmmc;
+extern sdmmc_storage_t sd_storage;
+
+static u32  sd_mode = SD_UHS_SDR104;
+
+u32 nx_sd_mode_get()
+{
+	return sd_mode;
+}
+
+int nx_sd_init_retry(bool power_cycle)
+{
+	u32 bus_width = SDMMC_BUS_WIDTH_4;
+	u32 type = SDHCI_TIMING_UHS_SDR104;
+
+	// Power cycle SD card.
+	if (power_cycle)
+	{
+		sd_mode--;
+		sdmmc_storage_end(&sd_storage);
+	}
+
+	// Get init parameters.
+	switch (sd_mode)
+	{
+	case SD_INIT_FAIL: // Reset to max.
+		return 0;
+	case SD_1BIT_HS25:
+		bus_width = SDMMC_BUS_WIDTH_1;
+		type = SDHCI_TIMING_SD_HS25;
+		break;
+	case SD_4BIT_HS25:
+		type = SDHCI_TIMING_SD_HS25;
+		break;
+	case SD_UHS_SDR82:
+		type = SDHCI_TIMING_UHS_SDR82;
+		break;
+	case SD_UHS_SDR104:
+		type = SDHCI_TIMING_UHS_SDR104;
+		break;
+	default:
+		sd_mode = SD_UHS_SDR104;
+	}
+
+	return sdmmc_storage_init_sd(&sd_storage, &sd_sdmmc, bus_width, type);
+}
+
+bool nx_sd_initialize(bool power_cycle)
+{
+	if (power_cycle)
+		sdmmc_storage_end(&sd_storage);
+
+	int res = !nx_sd_init_retry(false);
+
+	while (true)
+	{
+		if (!res)
+			return true;
+		else
+		{
+			if (sd_mode == SD_INIT_FAIL)
+				break;
+
+			res = !nx_sd_init_retry(true);
+		}
+	}
+
+	return false;
+}

emummc/source/emmc/nx_sd.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018-2019 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef NX_SD_H
+#define NX_SD_H
+
+#include "../utils/types.h"
+
+enum
+{
+	SD_INIT_FAIL  = 0,
+	SD_1BIT_HS25  = 1,
+	SD_4BIT_HS25  = 2,
+	SD_UHS_SDR82  = 3,
+	SD_UHS_SDR104 = 4
+};
+
+u32  nx_sd_get_mode();
+int  nx_sd_init_retry(bool power_cycle);
+bool nx_sd_initialize(bool power_cycle);
+
+#endif

emummc/source/emmc/sd.h

@@ -1,8 +1,8 @@
 /*
  *  include/linux/mmc/sd.h
  *
- *  Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
- *  Copyright (C) 2018 CTCaer
+ *  Copyright (c) 2005-2007 Pierre Ossman, All Rights Reserved.
+ *  Copyright (c) 2018 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -40,7 +40,9 @@
 #define SD_ROCR_S18A        SD_OCR_S18R  /* 1.8V switching accepted by card */
 #define SD_OCR_XPC          (1 << 28)    /* SDXC power control */
 #define SD_OCR_CCS          (1 << 30)    /* Card Capacity Status */
+#define SD_OCR_VDD_27_34    (0x7F << 15) /* VDD voltage 2.7 ~ 3.4 */
 #define SD_OCR_VDD_32_33    (1 << 20)	 /* VDD voltage 3.2 ~ 3.3 */
+#define SD_OCR_VDD_18       (1 << 7)	 /* VDD voltage 1.8 */
 
 /*
 * SD_SWITCH argument format:
@@ -104,6 +106,11 @@
 #define SD_SET_CURRENT_LIMIT_600	2
 #define SD_SET_CURRENT_LIMIT_800	3
 
+#define SD_MAX_CURRENT_200 (1 << SD_SET_CURRENT_LIMIT_200)
+#define SD_MAX_CURRENT_400 (1 << SD_SET_CURRENT_LIMIT_400)
+#define SD_MAX_CURRENT_600 (1 << SD_SET_CURRENT_LIMIT_600)
+#define SD_MAX_CURRENT_800 (1 << SD_SET_CURRENT_LIMIT_800)
+
 /*
 * SD_SWITCH mode
 */

emummc/source/emmc/sdmmc.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (C) 2018 CTCaer
+ * Copyright (c) 2018-2019 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -20,6 +20,7 @@
 #include <stdio.h>
 #include "sdmmc.h"
 #include "mmc.h"
+#include "nx_sd.h"
 #include "sd.h"
 #include "../utils/types.h"
 #include "../utils/util.h"
@@ -188,6 +189,7 @@ static int _sdmmc_storage_execute_cmd_type1_ex(sdmmc_storage_t *storage, u32 *re
 	if (_sdmmc_storage_check_result(*resp))
 		if (expected_state == 0x10 || R1_CURRENT_STATE(*resp) == expected_state)
 			return 1;
+
 	return 0;
 }
 
@@ -201,6 +203,7 @@ static int _sdmmc_storage_go_idle_state(sdmmc_storage_t *storage)
 {
 	sdmmc_cmd_t cmd;
 	sdmmc_init_cmd(&cmd, MMC_GO_IDLE_STATE, 0, SDMMC_RSP_TYPE_0, 0);
+
 	return sdmmc_execute_cmd(storage->sdmmc, &cmd, 0, 0);
 }
 
@@ -210,7 +213,9 @@ static int _sdmmc_storage_get_cid(sdmmc_storage_t *storage, void *buf)
 	sdmmc_init_cmd(&cmd, MMC_ALL_SEND_CID, 0, SDMMC_RSP_TYPE_2, 0);
 	if (!sdmmc_execute_cmd(storage->sdmmc, &cmd, 0, 0))
 		return 0;
+
 	sdmmc_get_rsp(storage->sdmmc, buf, 0x10, SDMMC_RSP_TYPE_2);
+
 	return 1;
 }
 
@@ -225,7 +230,9 @@ static int _sdmmc_storage_get_csd(sdmmc_storage_t *storage, void *buf)
 	sdmmc_init_cmd(&cmdbuf, MMC_SEND_CSD, storage->rca << 16, SDMMC_RSP_TYPE_2, 0);
 	if (!sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, 0, 0))
 		return 0;
+
 	sdmmc_get_rsp(storage->sdmmc, buf, 0x10, SDMMC_RSP_TYPE_2);
+
 	return 1;
 }
 
@@ -247,9 +254,9 @@ static int _sdmmc_storage_check_status(sdmmc_storage_t *storage)
 
 static int _sdmmc_storage_readwrite_ex(sdmmc_storage_t *storage, u32 *blkcnt_out, u32 sector, u32 num_sectors, void *buf, u32 is_write)
 {
+	u32 tmp = 0;
 	sdmmc_cmd_t cmdbuf;
 	sdmmc_req_t reqbuf;
-	u32 tmp = 0;
 
 	sdmmc_init_cmd(&cmdbuf, is_write ? MMC_WRITE_MULTIPLE_BLOCK : MMC_READ_MULTIPLE_BLOCK, sector, SDMMC_RSP_TYPE_1, 0);
 
@@ -264,6 +271,7 @@ static int _sdmmc_storage_readwrite_ex(sdmmc_storage_t *storage, u32 *blkcnt_out
 	{
 		sdmmc_stop_transmission(storage->sdmmc, &tmp);
 		_sdmmc_storage_get_status(storage, &tmp, 0);
+
 		return 0;
 	}
 
@@ -274,36 +282,58 @@ int sdmmc_storage_end(sdmmc_storage_t *storage)
 {
 	if (!_sdmmc_storage_go_idle_state(storage))
 		return 0;
+
 	sdmmc_end(storage->sdmmc);
+
 	return 1;
 }
 
 static int _sdmmc_storage_readwrite(sdmmc_storage_t *storage, u32 sector, u32 num_sectors, void *buf, u32 is_write)
 {
 	u8 *bbuf = (u8 *)buf;
-
+	bool first_reinit = false;
 	while (num_sectors)
 	{
 		u32 blkcnt = 0;
-		//Retry 9 times on error.
-		u32 retries = 10;
+		// Retry 5 times if failed.
+		u32 retries = 5;
 		do
 		{
+reinit_try:
 			if (_sdmmc_storage_readwrite_ex(storage, &blkcnt, sector, MIN(num_sectors, 0xFFFF), bbuf, is_write))
 				goto out;
 			else
 				retries--;
 
-			msleep(100);
+			msleep(50);
 		} while (retries);
+
+		// Disk IO failure! Reinit SD Card to a lower speed.
+		if (storage->sdmmc->id == SDMMC_1)
+		{
+			int res;
+
+			if (!first_reinit)
+				res = nx_sd_initialize(true);
+			else
+				res = nx_sd_init_retry(true);
+
+			retries = 3;
+			first_reinit = true;
+
+			if (res)
+				goto reinit_try;
+		}
+
 		return 0;
 
-out:;
-		DPRINTF("readwrite: %08X\n", blkcnt);
+out:
+DPRINTF("readwrite: %08X\n", blkcnt);
 		sector += blkcnt;
 		num_sectors -= blkcnt;
 		bbuf += 512 * blkcnt;
 	}
+
 	return 1;
 }
 
@@ -427,10 +457,10 @@ static int _mmc_storage_get_op_cond_inner(sdmmc_storage_t *storage, u32 *pout, u
 	switch (power)
 	{
 	case SDMMC_POWER_1_8:
-		arg = 0x40000080; //Sector access, voltage.
+		arg = SD_OCR_CCS | SD_OCR_VDD_18;
 		break;
 	case SDMMC_POWER_3_3:
-		arg = 0x403F8000; //Sector access, voltage.
+		arg = SD_OCR_CCS | SD_OCR_VDD_27_34;
 		break;
 	default:
 		return 0;
@@ -445,21 +475,24 @@ static int _mmc_storage_get_op_cond_inner(sdmmc_storage_t *storage, u32 *pout, u
 
 static int _mmc_storage_get_op_cond(sdmmc_storage_t *storage, u32 power)
 {
-	u32 timeout = get_tmr_ms() + 1500;
+	u64 timeout = get_tmr_ms() + 1500;
 
 	while (1)
 	{
 		u32 cond = 0;
 		if (!_mmc_storage_get_op_cond_inner(storage, &cond, power))
 			break;
+
 		if (cond & MMC_CARD_BUSY)
 		{
-			if (cond & 0x40000000)
+			if (cond & SD_OCR_CCS)
 				storage->has_sector_access = 1;
+
 			return 1;
 		}
 		if (get_tmr_ms() > timeout)
 			break;
+
 		usleep(1000);
 	}
 
@@ -589,6 +622,7 @@ static int _mmc_storage_switch_buswidth(sdmmc_storage_t *storage, u32 bus_width)
 		if (_sdmmc_storage_check_status(storage))
 		{
 			sdmmc_set_bus_width(storage->sdmmc, bus_width);
+
 			return 1;
 		}
 
@@ -599,14 +633,19 @@ static int _mmc_storage_enable_HS(sdmmc_storage_t *storage, int check)
 {
 	if (!_mmc_storage_switch(storage, SDMMC_SWITCH(MMC_SWITCH_MODE_WRITE_BYTE, EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS)))
 		return 0;
+
 	if (check && !_sdmmc_storage_check_status(storage))
 		return 0;
-	if (!sdmmc_setup_clock(storage->sdmmc, 2))
+
+	if (!sdmmc_setup_clock(storage->sdmmc, SDHCI_TIMING_MMC_HS52))
 		return 0;
-	DPRINTF("[MMC] switched to HS\n");
+
+DPRINTF("[MMC] switched to HS\n");
 	storage->csd.busspeed = 52;
+
 	if (check || _sdmmc_storage_check_status(storage))
 		return 1;
+
 	return 0;
 }
 
@@ -614,12 +653,16 @@ static int _mmc_storage_enable_HS200(sdmmc_storage_t *storage)
 {
 	if (!_mmc_storage_switch(storage, SDMMC_SWITCH(MMC_SWITCH_MODE_WRITE_BYTE, EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS200)))
 		return 0;
-	if (!sdmmc_setup_clock(storage->sdmmc, 3))
+
+	if (!sdmmc_setup_clock(storage->sdmmc, SDHCI_TIMING_MMC_HS200))
 		return 0;
-	if (!sdmmc_config_tuning(storage->sdmmc, 3, MMC_SEND_TUNING_BLOCK_HS200))
+
+	if (!sdmmc_tuning_execute(storage->sdmmc, SDHCI_TIMING_MMC_HS200, MMC_SEND_TUNING_BLOCK_HS200))
 		return 0;
-	DPRINTF("[MMC] switched to HS200\n");
+
+DPRINTF("[MMC] switched to HS200\n");
 	storage->csd.busspeed = 200;
+
 	return _sdmmc_storage_check_status(storage);
 }
 
@@ -627,41 +670,46 @@ static int _mmc_storage_enable_HS400(sdmmc_storage_t *storage)
 {
 	if (!_mmc_storage_enable_HS200(storage))
 		return 0;
-	sdmmc_get_venclkctl(storage->sdmmc);
+
+	sdmmc_set_tap_value(storage->sdmmc);
+
 	if (!_mmc_storage_enable_HS(storage, 0))
 		return 0;
+
 	if (!_mmc_storage_switch(storage, SDMMC_SWITCH(MMC_SWITCH_MODE_WRITE_BYTE, EXT_CSD_BUS_WIDTH, EXT_CSD_DDR_BUS_WIDTH_8)))
 		return 0;
+
 	if (!_mmc_storage_switch(storage, SDMMC_SWITCH(MMC_SWITCH_MODE_WRITE_BYTE, EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS400)))
 		return 0;
-	if (!sdmmc_setup_clock(storage->sdmmc, 4))
+
+	if (!sdmmc_setup_clock(storage->sdmmc, SDHCI_TIMING_MMC_HS400))
 		return 0;
-	DPRINTF("[MMC] switched to HS400\n");
+
+DPRINTF("[MMC] switched to HS400\n");
 	storage->csd.busspeed = 400;
+
 	return _sdmmc_storage_check_status(storage);
 }
 
 static int _mmc_storage_enable_highspeed(sdmmc_storage_t *storage, u32 card_type, u32 type)
 {
-	//TODO: this should be a config item.
-	// --v
-	if (!1 || sdmmc_get_voltage(storage->sdmmc) != SDMMC_POWER_1_8)
+	if (sdmmc_get_io_power(storage->sdmmc) != SDMMC_POWER_1_8)
 		goto out;
 
 	if (sdmmc_get_bus_width(storage->sdmmc) == SDMMC_BUS_WIDTH_8 &&
-		card_type & EXT_CSD_CARD_TYPE_HS400_1_8V &&
-		type == 4)
+		card_type & EXT_CSD_CARD_TYPE_HS400_1_8V && type == SDHCI_TIMING_MMC_HS400)
 		return _mmc_storage_enable_HS400(storage);
 
 	if (sdmmc_get_bus_width(storage->sdmmc) == SDMMC_BUS_WIDTH_8 ||
 		(sdmmc_get_bus_width(storage->sdmmc) == SDMMC_BUS_WIDTH_4
 		&& card_type & EXT_CSD_CARD_TYPE_HS200_1_8V
-		&& (type == 4 || type == 3)))
+		&& (type == SDHCI_TIMING_MMC_HS400 || type == SDHCI_TIMING_MMC_HS200)))
 		return _mmc_storage_enable_HS200(storage);
 
-out:;
+out:
 	if (card_type & EXT_CSD_CARD_TYPE_HS_52)
 		return _mmc_storage_enable_HS(storage, 1);
+
 	return 1;
 }
 
@@ -669,53 +717,54 @@ static int _mmc_storage_enable_bkops(sdmmc_storage_t *storage)
 {
 	if (!_mmc_storage_switch(storage, SDMMC_SWITCH(MMC_SWITCH_MODE_SET_BITS, EXT_CSD_BKOPS_EN, EXT_CSD_BKOPS_LEVEL_2)))
 		return 0;
+
 	return _sdmmc_storage_check_status(storage);
 }
 
-int sdmmc_storage_init_mmc(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 id, u32 bus_width, u32 type)
+int sdmmc_storage_init_mmc(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 bus_width, u32 type)
 {
 	memset(storage, 0, sizeof(sdmmc_storage_t));
 	storage->sdmmc = sdmmc;
 	storage->rca = 2; //TODO: this could be a config item.
 
-	if (!sdmmc_init(sdmmc, id, SDMMC_POWER_1_8, SDMMC_BUS_WIDTH_1, 0, 0))
+	if (!sdmmc_init(sdmmc, SDMMC_4, SDMMC_POWER_1_8, SDMMC_BUS_WIDTH_1, SDHCI_TIMING_MMC_ID, SDMMC_AUTO_CAL_DISABLE))
 		return 0;
-	DPRINTF("[MMC] after init\n");
+DPRINTF("[MMC] after init\n");
 
 	usleep(1000 + (74000 + sdmmc->divisor - 1) / sdmmc->divisor);
 
 	if (!_sdmmc_storage_go_idle_state(storage))
 		return 0;
-	DPRINTF("[MMC] went to idle state\n");
+DPRINTF("[MMC] went to idle state\n");
 
 	if (!_mmc_storage_get_op_cond(storage, SDMMC_POWER_1_8))
 		return 0;
-	DPRINTF("[MMC] got op cond\n");
+DPRINTF("[MMC] got op cond\n");
 
 	if (!_sdmmc_storage_get_cid(storage, storage->raw_cid))
 		return 0;
-	DPRINTF("[MMC] got cid\n");
+DPRINTF("[MMC] got cid\n");
 
 	if (!_mmc_storage_set_relative_addr(storage))
 		return 0;
-	DPRINTF("[MMC] set relative addr\n");
+DPRINTF("[MMC] set relative addr\n");
 
 	if (!_sdmmc_storage_get_csd(storage, storage->raw_csd))
 		return 0;
-	DPRINTF("[MMC] got csd\n");
+DPRINTF("[MMC] got csd\n");
 	_mmc_storage_parse_csd(storage);
 
-	if (!sdmmc_setup_clock(storage->sdmmc, 1))
+	if (!sdmmc_setup_clock(storage->sdmmc, SDHCI_TIMING_MMC_LS26))
 		return 0;
-	DPRINTF("[MMC] after setup clock\n");
+DPRINTF("[MMC] after setup clock\n");
 
 	if (!_sdmmc_storage_select_card(storage))
 		return 0;
-	DPRINTF("[MMC] card selected\n");
+DPRINTF("[MMC] card selected\n");
 
 	if (!_sdmmc_storage_set_blocklen(storage, 512))
 		return 0;
-	DPRINTF("[MMC] set blocklen to 512\n");
+DPRINTF("[MMC] set blocklen to 512\n");
 
 	u32 *csd = (u32 *)storage->raw_csd;
 	//Check system specification version, only version 4.0 and later support below features.
@@ -727,36 +776,29 @@ int sdmmc_storage_init_mmc(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 id, u32
 
 	if (!_mmc_storage_switch_buswidth(storage, bus_width))
 		return 0;
-	DPRINTF("[MMC] switched buswidth\n");
-
-	u8 *ext_csd = (u8 *)malloc(512);
-	if (!_mmc_storage_get_ext_csd(storage, ext_csd))
-	{
-		free(ext_csd);
+DPRINTF("[MMC] switched buswidth\n");
+	u8 buf[512];
+	memset(buf, 0, sizeof(buf));
+	if (!_mmc_storage_get_ext_csd(storage, buf))
 		return 0;
-	}
-	free(ext_csd);
-	DPRINTF("[MMC] got ext_csd\n");
+DPRINTF("[MMC] got ext_csd\n");
+
 	_mmc_storage_parse_cid(storage); //This needs to be after csd and ext_csd
 
 	/* When auto BKOPS is enabled the mmc device should be powered all the time until we disable this and check status.
 	   Disable it for now until BKOPS disable added to power down sequence at sdmmc_storage_end().
 	   Additionally this works only when we put the device in idle mode which we don't after enabling it. */
-	if (storage->ext_csd.bkops & 0x1 && !(storage->ext_csd.bkops_en & EXT_CSD_BKOPS_LEVEL_2) && 0)
+	if (0 && storage->ext_csd.bkops & 0x1 && !(storage->ext_csd.bkops_en & EXT_CSD_BKOPS_LEVEL_2))
 	{
 		_mmc_storage_enable_bkops(storage);
-		DPRINTF("[MMC] BKOPS enabled\n");
-	}
-	else
-	{
-		DPRINTF("[MMC] BKOPS disabled\n");
+DPRINTF("[MMC] BKOPS enabled\n");
 	}
 
 	if (!_mmc_storage_enable_highspeed(storage, storage->ext_csd.card_type, type))
 		return 0;
-	DPRINTF("[MMC] succesfully switched to highspeed mode\n");
+DPRINTF("[MMC] succesfully switched to HS mode\n");
 
-	sdmmc_sd_clock_ctrl(storage->sdmmc, 1);
+	sdmmc_card_clock_ctrl(storage->sdmmc, SDMMC_AUTO_CAL_ENABLE);
 
 	return 1;
 }
@@ -765,8 +807,10 @@ int sdmmc_storage_set_mmc_partition(sdmmc_storage_t *storage, u32 partition)
 {
 	if (!_mmc_storage_switch(storage, SDMMC_SWITCH(MMC_SWITCH_MODE_WRITE_BYTE, EXT_CSD_PART_CONFIG, partition)))
 		return 0;
+
 	if (!_sdmmc_storage_check_status(storage))
 		return 0;
+
 	storage->partition = partition;
 	return 1;
 }
@@ -780,6 +824,7 @@ static int _sd_storage_execute_app_cmd(sdmmc_storage_t *storage, u32 expected_st
 	u32 tmp;
 	if (!_sdmmc_storage_execute_cmd_type1_ex(storage, &tmp, MMC_APP_CMD, storage->rca << 16, 0, expected_state, mask))
 		return 0;
+
 	return sdmmc_execute_cmd(storage->sdmmc, cmd, req, blkcnt_out);
 }
 
@@ -787,6 +832,7 @@ static int _sd_storage_execute_app_cmd_type1(sdmmc_storage_t *storage, u32 *resp
 {
 	if (!_sdmmc_storage_execute_cmd_type1(storage, MMC_APP_CMD, storage->rca << 16, 0, R1_STATE_TRAN))
 		return 0;
+
 	return _sdmmc_storage_execute_cmd_type1_ex(storage, resp, cmd, arg, check_busy, expected_state, 0);
 }
 
@@ -816,32 +862,27 @@ static int _sd_storage_get_op_cond_once(sdmmc_storage_t *storage, u32 *cond, int
 	// This is needed for most cards. Do not set bit7 even if 1.8V is supported.
 	arg |= SD_OCR_VDD_32_33;
 	sdmmc_init_cmd(&cmdbuf, SD_APP_OP_COND, arg, SDMMC_RSP_TYPE_3, 0);
-
-	DPRINTF("[SD] before _sd_storage_execute_app_cmd\n");
 	if (!_sd_storage_execute_app_cmd(storage, 0x10, is_version_1 ? 0x400000 : 0, &cmdbuf, 0, 0))
 		return 0;
-	DPRINTF("[SD] before sdmmc_get_rsp\n");
+
 	return sdmmc_get_rsp(storage->sdmmc, cond, 4, SDMMC_RSP_TYPE_3);
 }
 
 static int _sd_storage_get_op_cond(sdmmc_storage_t *storage, int is_version_1, int supports_low_voltage)
 {
-	u32 timeout = get_tmr_ms() + 1500;
+	u64 timeout = get_tmr_ms() + 1500;
 
 	while (1)
 	{
 		u32 cond = 0;
 		if (!_sd_storage_get_op_cond_once(storage, &cond, is_version_1, supports_low_voltage))
-		{
-			DPRINTF("[SD] _sd_storage_get_op_cond_once failed\r\n");
 			break;
-		}
-
 		if (cond & MMC_CARD_BUSY)
 		{
 			if (cond & SD_OCR_CCS)
 				storage->has_sector_access = 1;
 
+			// Check if card supports 1.8V signaling.
 			if (cond & SD_ROCR_S18A && supports_low_voltage)
 			{
 				//The low voltage regulator configuration is valid for SDMMC1 only.
@@ -852,7 +893,7 @@ static int _sd_storage_get_op_cond(sdmmc_storage_t *storage, int is_version_1, i
 						return 0;
 					storage->is_low_voltage = 1;
 
-					DPRINTF("-> switched to low voltage\n");
+DPRINTF("-> switched to low voltage\n");
 				}
 			}
 
@@ -863,8 +904,6 @@ static int _sd_storage_get_op_cond(sdmmc_storage_t *storage, int is_version_1, i
 		msleep(10); // Needs to be at least 10ms for some SD Cards
 	}
 
-	DPRINTF("[SD] _sd_storage_get_op_cond Timeout\r\n");
-
 	return 0;
 }
 
@@ -873,7 +912,7 @@ static int _sd_storage_get_rca(sdmmc_storage_t *storage)
 	sdmmc_cmd_t cmdbuf;
 	sdmmc_init_cmd(&cmdbuf, SD_SEND_RELATIVE_ADDR, 0, SDMMC_RSP_TYPE_4, 0);
 
-	u32 timeout = get_tmr_ms() + 1500;
+	u64 timeout = get_tmr_ms() + 1500;
 
 	while (1)
 	{
@@ -991,34 +1030,37 @@ int _sd_storage_switch(sdmmc_storage_t *storage, void *buf, int mode, int group,
 	return _sdmmc_storage_check_result(tmp);
 }
 
-void _sd_storage_set_current_limit(sdmmc_storage_t *storage, u8 *buf)
+void _sd_storage_set_current_limit(sdmmc_storage_t *storage, u16 current_limit, u8 *buf)
 {
-	u32 pwr = SD_SET_CURRENT_LIMIT_800;
+	u32 pwr = SD_SET_CURRENT_LIMIT_200;
+
+	if (current_limit & SD_MAX_CURRENT_800)
+		pwr = SD_SET_CURRENT_LIMIT_800;
+	else if (current_limit & SD_MAX_CURRENT_600)
+		pwr = SD_SET_CURRENT_LIMIT_600;
+	else if (current_limit & SD_MAX_CURRENT_400)
+		pwr = SD_SET_CURRENT_LIMIT_400;
+
 	_sd_storage_switch(storage, buf, SD_SWITCH_SET, 3, pwr);
 
-	while (pwr > 0)
+	if (((buf[15] >> 4) & 0x0F) == pwr)
 	{
-		pwr--;
-		_sd_storage_switch(storage, buf, SD_SWITCH_SET, 3, pwr);
-		if (((buf[15] >> 4) & 0x0F) == pwr)
+		switch (pwr)
+		{
+		case SD_SET_CURRENT_LIMIT_800:
+DPRINTF("[SD] power limit raised to 800mA\n");
 			break;
-	}
-
-	switch (pwr)
-	{
-	case SD_SET_CURRENT_LIMIT_800:
-		DPRINTF("[SD] Power limit raised to 800mA\n");
-		break;
-	case SD_SET_CURRENT_LIMIT_600:
-		DPRINTF("[SD] Power limit raised to 600mA\n");
-		break;
-	case SD_SET_CURRENT_LIMIT_400:
-		DPRINTF("[SD] Power limit raised to 800mA\n");
-		break;
-	default:
-	case SD_SET_CURRENT_LIMIT_200:
-		DPRINTF("[SD] Power limit defaulted to 200mA\n");
-		break;
+		case SD_SET_CURRENT_LIMIT_600:
+DPRINTF("[SD] power limit raised to 600mA\n");
+			break;
+		case SD_SET_CURRENT_LIMIT_400:
+DPRINTF("[SD] power limit raised to 400mA\n");
+			break;
+		default:
+		case SD_SET_CURRENT_LIMIT_200:
+DPRINTF("[SD] power limit defaulted to 200mA\n");
+			break;
+		}
 	}
 }
 
@@ -1026,62 +1068,91 @@ int _sd_storage_enable_highspeed(sdmmc_storage_t *storage, u32 hs_type, u8 *buf)
 {
 	if (!_sd_storage_switch(storage, buf, SD_SWITCH_CHECK, 0, hs_type))
 		return 0;
+DPRINTF("[SD] supports switch to (U)HS mode\n");
 
 	u32 type_out = buf[16] & 0xF;
 	if (type_out != hs_type)
 		return 0;
+DPRINTF("[SD] supports selected (U)HS mode\n");
 
-	if ((((u16)buf[0] << 8) | buf[1]) < 0x320)
+	u16 total_pwr_consumption = ((u16)buf[0] << 8) | buf[1];
+DPRINTF("[SD] total max current: %d\n", total_pwr_consumption);
+
+	if (total_pwr_consumption <= 800)
 	{
 		if (!_sd_storage_switch(storage, buf, SD_SWITCH_SET, 0, hs_type))
 			return 0;
 
 		if (type_out != (buf[16] & 0xF))
 			return 0;
-	}
 
-	return 1;
+		return 1;
+	}
+DPRINTF("[SD] card max current over limit\n");
+
+	return 0;
 }
 
-int _sd_storage_enable_highspeed_low_volt(sdmmc_storage_t *storage, u32 type, u8 *buf)
+int _sd_storage_enable_uhs_low_volt(sdmmc_storage_t *storage, u32 type, u8 *buf)
 {
-	// Try to raise the current limit to let the card perform better.
-	_sd_storage_set_current_limit(storage, buf);
-
 	if (sdmmc_get_bus_width(storage->sdmmc) != SDMMC_BUS_WIDTH_4)
 		return 0;
 
 	if (!_sd_storage_switch_get(storage, buf))
 		return 0;
+	//gfx_hexdump(0, (u8 *)buf, 64);
+
+	u8  access_mode = buf[13];
+	u16 current_limit = buf[7] | buf[6] << 8;
+
+	// Try to raise the current limit to let the card perform better.
+	_sd_storage_set_current_limit(storage, current_limit, buf);
 
 	u32 hs_type = 0;
 	switch (type)
 	{
-	case 11:
+	case SDHCI_TIMING_UHS_SDR104:
+	case SDHCI_TIMING_UHS_SDR82:
 		// Fall through if not supported.
-		if (buf[13] & SD_MODE_UHS_SDR104)
+		if (access_mode & SD_MODE_UHS_SDR104)
 		{
-			type = 11;
 			hs_type = UHS_SDR104_BUS_SPEED;
-			DPRINTF("[SD] Bus speed set to SDR104\n");
-			storage->csd.busspeed = 104;
+DPRINTF("[SD] bus speed set to SDR104\n");
+			switch (type)
+			{
+			case SDHCI_TIMING_UHS_SDR104:
+				storage->csd.busspeed = 104;
+				break;
+			case SDHCI_TIMING_UHS_SDR82:
+				storage->csd.busspeed = 82;
+				break;
+			}
 			break;
 		}
-	case 10:
-		if (buf[13] & SD_MODE_UHS_SDR50)
+	case SDHCI_TIMING_UHS_SDR50:
+		if (access_mode & SD_MODE_UHS_SDR50)
 		{
-			type = 10;
+			type = SDHCI_TIMING_UHS_SDR50;
 			hs_type = UHS_SDR50_BUS_SPEED;
-			DPRINTF("[SD] Bus speed set to SDR50\n");
+DPRINTF("[SD] bus speed set to SDR50\n");
 			storage->csd.busspeed = 50;
 			break;
 		}
-	case 8:
-		if (!(buf[13] & SD_MODE_UHS_SDR12))
+	case SDHCI_TIMING_UHS_SDR25:
+		if (access_mode & SD_MODE_UHS_SDR25)
+		{
+			type = SDHCI_TIMING_UHS_SDR25;
+			hs_type = UHS_SDR50_BUS_SPEED;
+DPRINTF("[SD] bus speed set to SDR25\n");
+			storage->csd.busspeed = 25;
+			break;
+		}
+	case SDHCI_TIMING_UHS_SDR12:
+		if (!(access_mode & SD_MODE_UHS_SDR12))
 			return 0;
-		type = 8;
+		type = SDHCI_TIMING_UHS_SDR12;
 		hs_type = UHS_SDR12_BUS_SPEED;
-		DPRINTF("[SD] Bus speed set to SDR12\n");
+DPRINTF("[SD] bus speed set to SDR12\n");
 		storage->csd.busspeed = 12;
 		break;
 	default:
@@ -1091,106 +1162,38 @@ int _sd_storage_enable_highspeed_low_volt(sdmmc_storage_t *storage, u32 type, u8
 
 	if (!_sd_storage_enable_highspeed(storage, hs_type, buf))
 		return 0;
+DPRINTF("[SD] card accepted UHS\n");
 	if (!sdmmc_setup_clock(storage->sdmmc, type))
 		return 0;
-	if (!sdmmc_config_tuning(storage->sdmmc, type, MMC_SEND_TUNING_BLOCK))
+DPRINTF("[SD] setup clock\n");
+	if (!sdmmc_tuning_execute(storage->sdmmc, type, MMC_SEND_TUNING_BLOCK))
 		return 0;
+DPRINTF("[SD] config tuning\n");
 	return _sdmmc_storage_check_status(storage);
 }
 
-int _sd_storage_enable_highspeed_high_volt(sdmmc_storage_t *storage, u8 *buf)
+int _sd_storage_enable_hs_high_volt(sdmmc_storage_t *storage, u8 *buf)
 {
 	if (!_sd_storage_switch_get(storage, buf))
 		return 0;
-	if (!(buf[13] & SD_MODE_HIGH_SPEED))
+	//gfx_hexdump(0, (u8 *)buf, 64);
+
+	u8  access_mode = buf[13];
+	u16 current_limit = buf[7] | buf[6] << 8;
+
+	// Try to raise the current limit to let the card perform better.
+	_sd_storage_set_current_limit(storage, current_limit, buf);
+
+	if (!(access_mode & SD_MODE_HIGH_SPEED))
 		return 1;
 
-	if (!_sd_storage_enable_highspeed(storage, 1, buf))
+	if (!_sd_storage_enable_highspeed(storage, HIGH_SPEED_BUS_SPEED, buf))
 		return 0;
+
 	if (!_sdmmc_storage_check_status(storage))
 		return 0;
-	return sdmmc_setup_clock(storage->sdmmc, 7);
-}
 
-static void _sd_storage_parse_ssr(sdmmc_storage_t *storage)
-{
-	// unstuff_bits supports only 4 u32 so break into 2 x 16byte groups
-	u32 raw_ssr1[4];
-	u32 raw_ssr2[4];
-
-	raw_ssr1[3] = *(u32 *)&storage->raw_ssr[12];
-	raw_ssr1[2] = *(u32 *)&storage->raw_ssr[8];
-	raw_ssr1[1] = *(u32 *)&storage->raw_ssr[4];
-	raw_ssr1[0] = *(u32 *)&storage->raw_ssr[0];
-
-	raw_ssr2[3] = *(u32 *)&storage->raw_ssr[28];
-	raw_ssr2[2] = *(u32 *)&storage->raw_ssr[24];
-	raw_ssr2[1] = *(u32 *)&storage->raw_ssr[20];
-	raw_ssr2[0] = *(u32 *)&storage->raw_ssr[16];
-
-	storage->ssr.bus_width = (unstuff_bits(raw_ssr1, 510 - 384, 2) & SD_BUS_WIDTH_4) ? 4 : 1;
-	switch(unstuff_bits(raw_ssr1, 440 - 384, 8))
-	{
-	case 0:
-		storage->ssr.speed_class = 0;
-		break;
-	case 1:
-		storage->ssr.speed_class = 2;
-		break;
-	case 2:
-		storage->ssr.speed_class = 4;
-		break;
-	case 3:
-		storage->ssr.speed_class = 6;
-		break;
-	case 4:
-		storage->ssr.speed_class = 10;
-		break;
-	default:
-		storage->ssr.speed_class = unstuff_bits(raw_ssr1, 440 - 384, 8);
-		break;
-	}
-	storage->ssr.uhs_grade = unstuff_bits(raw_ssr1, 396 - 384, 4);
-	storage->ssr.video_class = unstuff_bits(raw_ssr1, 384 - 384, 8);
-
-	storage->ssr.app_class = unstuff_bits(raw_ssr2, 336 - 256, 4);
-}
-
-static int _sd_storage_get_ssr(sdmmc_storage_t *storage, u8 *buf)
-{
-	sdmmc_cmd_t cmdbuf;
-	sdmmc_init_cmd(&cmdbuf, SD_APP_SD_STATUS, 0, SDMMC_RSP_TYPE_1, 0);
-
-	sdmmc_req_t reqbuf;
-	reqbuf.buf = buf;
-	reqbuf.blksize = 64;
-	reqbuf.num_sectors = 1;
-	reqbuf.is_write = 0;
-	reqbuf.is_multi_block = 0;
-	reqbuf.is_auto_cmd12 = 0;
-
-	if (!(storage->csd.cmdclass & CCC_APP_SPEC))
-	{
-		DPRINTF("[SD] ssr: Card lacks mandatory SD Status function\n");
-		return 0;
-	}
-
-	if (!_sd_storage_execute_app_cmd(storage, R1_STATE_TRAN, 0, &cmdbuf, &reqbuf, 0))
-		return 0;
-
-	u32 tmp = 0;
-	sdmmc_get_rsp(storage->sdmmc, &tmp, 4, SDMMC_RSP_TYPE_1);
-    //Prepare buffer for unstuff_bits
-	for (int i = 0; i < 64; i+=4)
-	{
-		storage->raw_ssr[i + 3] = buf[i];
-		storage->raw_ssr[i + 2] = buf[i + 1];
-		storage->raw_ssr[i + 1] = buf[i + 2];
-		storage->raw_ssr[i]     = buf[i + 3];
-	}
-	_sd_storage_parse_ssr(storage);
-
-	return _sdmmc_storage_check_result(tmp);
+	return sdmmc_setup_clock(storage->sdmmc, SDHCI_TIMING_SD_HS25);
 }
 
 static void _sd_storage_parse_cid(sdmmc_storage_t *storage)
@@ -1232,45 +1235,65 @@ static void _sd_storage_parse_csd(sdmmc_storage_t *storage)
 	}
 }
 
-int sdmmc_storage_init_sd(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 id, u32 bus_width, u32 type)
+static bool _sdmmc_storage_supports_low_voltage(u32 bus_width, u32 type)
 {
+	switch (type)
+	{
+	case SDHCI_TIMING_UHS_SDR12:
+	case SDHCI_TIMING_UHS_SDR25:
+	case SDHCI_TIMING_UHS_SDR50:
+	case SDHCI_TIMING_UHS_SDR104:
+	case SDHCI_TIMING_UHS_SDR82:
+	case SDHCI_TIMING_UHS_DDR50:
+		if (bus_width == SDMMC_BUS_WIDTH_4)
+			return true;
+	default:
+		return false;
+	}
+}
+
+int sdmmc_storage_init_sd(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 bus_width, u32 type)
+{
+	u8 buf[512];
 	int is_version_1 = 0;
 
+	memset(buf, 0, sizeof(buf));
 	memset(storage, 0, sizeof(sdmmc_storage_t));
 	storage->sdmmc = sdmmc;
 
-	DPRINTF("[SD] before init\n");
-	if (!sdmmc_init(sdmmc, id, SDMMC_POWER_3_3, SDMMC_BUS_WIDTH_1, 5, 0))
+	if (!sdmmc_init(sdmmc, SDMMC_1, SDMMC_POWER_3_3, SDMMC_BUS_WIDTH_1, SDHCI_TIMING_SD_ID, SDMMC_AUTO_CAL_DISABLE))
 		return 0;
-	DPRINTF("[SD] after init\n");
+DPRINTF("[SD] after init\n");
 
 	usleep(1000 + (74000 + sdmmc->divisor - 1) / sdmmc->divisor);
 
 	if (!_sdmmc_storage_go_idle_state(storage))
 		return 0;
-	DPRINTF("[SD] went to idle state\n");
+DPRINTF("[SD] went to idle state\n");
 
 	is_version_1 = _sd_storage_send_if_cond(storage);
 	if (is_version_1 == 2)
 		return 0;
-	DPRINTF("[SD] after send if cond\n");
+DPRINTF("[SD] after send if cond\n");
 
-	if (!_sd_storage_get_op_cond(storage, is_version_1, bus_width == SDMMC_BUS_WIDTH_4 && type == 11))
+	bool supports_low_voltage = _sdmmc_storage_supports_low_voltage(bus_width, type);
+
+	if (!_sd_storage_get_op_cond(storage, is_version_1, supports_low_voltage))
 		return 0;
-	DPRINTF("[SD] got op cond\n");
+DPRINTF("[SD] got op cond\n");
 
 	if (!_sdmmc_storage_get_cid(storage, storage->raw_cid))
 		return 0;
-	DPRINTF("[SD] got cid\n");
+DPRINTF("[SD] got cid\n");
 	_sd_storage_parse_cid(storage);
 
 	if (!_sd_storage_get_rca(storage))
 		return 0;
-	DPRINTF("[SD] got rca (= %04X)\n", storage->rca);
+DPRINTF("[SD] got rca (= %04X)\n", storage->rca);
 
 	if (!_sdmmc_storage_get_csd(storage, storage->raw_csd))
 		return 0;
-	DPRINTF("[SD] got csd\n");
+DPRINTF("[SD] got csd\n");
 
 	//Parse CSD.
 	_sd_storage_parse_csd(storage);
@@ -1283,84 +1306,75 @@ int sdmmc_storage_init_sd(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 id, u32
 		storage->sec_cnt = storage->csd.c_size << 10;
 		break;
 	default:
-		DPRINTF("[SD] Unknown CSD structure %d\n", storage->csd.structure);
+DPRINTF("[SD] unknown CSD structure %d\n", storage->csd.structure);
 		break;
 	}
 
 	if (!storage->is_low_voltage)
 	{
-		if (!sdmmc_setup_clock(storage->sdmmc, 6))
+		if (!sdmmc_setup_clock(storage->sdmmc, SDHCI_TIMING_SD_DS12))
 			return 0;
-		DPRINTF("[SD] after setup clock\n");
+DPRINTF("[SD] after setup clock\n");
 	}
 
 	if (!_sdmmc_storage_select_card(storage))
 		return 0;
-	DPRINTF("[SD] card selected\n");
+DPRINTF("[SD] card selected\n");
 
 	if (!_sdmmc_storage_set_blocklen(storage, 512))
 		return 0;
-	DPRINTF("[SD] set blocklen to 512\n");
+DPRINTF("[SD] set blocklen to 512\n");
 
 	u32 tmp = 0;
 	if (!_sd_storage_execute_app_cmd_type1(storage, &tmp, SD_APP_SET_CLR_CARD_DETECT, 0, 0, R1_STATE_TRAN))
 		return 0;
-	DPRINTF("[SD] cleared card detect\n");
+DPRINTF("[SD] cleared card detect\n");
 
-	u8 *buf = (u8 *)malloc(512);
 	if (!_sd_storage_get_scr(storage, buf))
-	{
-		free(buf);
 		return 0;
-	}
 
-	DPRINTF("[SD] got scr\n");
+	//gfx_hexdump(0, storage->raw_scr, 8);
+DPRINTF("[SD] got scr\n");
 
 	// Check if card supports a wider bus and if it's not SD Version 1.X
 	if (bus_width == SDMMC_BUS_WIDTH_4 && (storage->scr.bus_widths & 4) && (storage->scr.sda_vsn & 0xF))
 	{
 		if (!_sd_storage_execute_app_cmd_type1(storage, &tmp, SD_APP_SET_BUS_WIDTH, SD_BUS_WIDTH_4, 0, R1_STATE_TRAN))
-		{
-			free(buf);
 			return 0;
-		}
+
 		sdmmc_set_bus_width(storage->sdmmc, SDMMC_BUS_WIDTH_4);
-		DPRINTF("[SD] switched to wide bus width\n");
+DPRINTF("[SD] switched to wide bus width\n");
 	}
 	else
 	{
-		DPRINTF("[SD] SD does not support wide bus width\n");
+DPRINTF("[SD] SD does not support wide bus width\n");
 	}
 
 	if (storage->is_low_voltage)
 	{
-		if (!_sd_storage_enable_highspeed_low_volt(storage, type, buf))
-		{
-			free(buf);
+		if (!_sd_storage_enable_uhs_low_volt(storage, type, buf))
 			return 0;
-		}
-		DPRINTF("[SD] enabled highspeed (low voltage)\n");
+DPRINTF("[SD] enabled UHS\n");
+
+		sdmmc_card_clock_ctrl(sdmmc, SDMMC_AUTO_CAL_ENABLE);
 	}
-	else if (type != 6 && (storage->scr.sda_vsn & 0xF) != 0)
+	else if (type != SDHCI_TIMING_SD_DS12 && (storage->scr.sda_vsn & 0xF) != 0)
 	{
-		if (!_sd_storage_enable_highspeed_high_volt(storage, buf))
-		{
-			free(buf);
+		if (!_sd_storage_enable_hs_high_volt(storage, buf))
 			return 0;
+
+DPRINTF("[SD] enabled HS\n");
+		switch (bus_width)
+		{
+		case SDMMC_BUS_WIDTH_4:
+			storage->csd.busspeed = 25;
+			break;
+		case SDMMC_BUS_WIDTH_1:
+			storage->csd.busspeed = 6;
+			break;
 		}
-		DPRINTF("[SD] enabled highspeed (high voltage)\n");
-		storage->csd.busspeed = 25;
 	}
 
-	sdmmc_sd_clock_ctrl(sdmmc, 1);
-
-	// Parse additional card info from sd status.
-	if (_sd_storage_get_ssr(storage, buf))
-	{
-		DPRINTF("[SD] got sd status\n");
-	}
-
-	free(buf);
 	return 1;
 }
 
@@ -1400,17 +1414,17 @@ int sdmmc_storage_init_gc(sdmmc_storage_t *storage, sdmmc_t *sdmmc)
 	memset(storage, 0, sizeof(sdmmc_storage_t));
 	storage->sdmmc = sdmmc;
 
-	if (!sdmmc_init(sdmmc, SDMMC_2, SDMMC_POWER_1_8, SDMMC_BUS_WIDTH_8, 14, 0))
+	if (!sdmmc_init(sdmmc, SDMMC_2, SDMMC_POWER_1_8, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_DDR52, SDMMC_AUTO_CAL_DISABLE))
 		return 0;
-	DPRINTF("[gc] after init\n");
+DPRINTF("[gc] after init\n");
 
 	usleep(1000 + (10000 + sdmmc->divisor - 1) / sdmmc->divisor);
 
-	if (!sdmmc_config_tuning(storage->sdmmc, 14, MMC_SEND_TUNING_BLOCK_HS200))
+	if (!sdmmc_tuning_execute(storage->sdmmc, SDHCI_TIMING_MMC_DDR52, MMC_SEND_TUNING_BLOCK_HS200))
 		return 0;
-	DPRINTF("[gc] after tuning\n");
+DPRINTF("[gc] after tuning\n");
 
-	sdmmc_sd_clock_ctrl(sdmmc, 1);
+	sdmmc_card_clock_ctrl(sdmmc, SDMMC_AUTO_CAL_ENABLE);
 
 	return 1;
 }

emummc/source/emmc/sdmmc.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
- * Copyright (C) 2018 CTCaer
+ * Copyright (c) 2018 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -95,12 +95,10 @@ typedef struct _sdmmc_storage_t
 	u8  raw_cid[0x10];
 	u8  raw_csd[0x10];
 	u8  raw_scr[8];
-	u8  raw_ssr[0x40];
 	mmc_cid_t     cid;
 	mmc_csd_t     csd;
 	mmc_ext_csd_t ext_csd;
 	sd_scr_t      scr;
-	sd_ssr_t      ssr;
 } sdmmc_storage_t;
 
 extern sdmmc_accessor_t *_current_accessor;
@@ -109,9 +107,9 @@ extern bool sdmmc_memcpy_buf;
 int sdmmc_storage_end(sdmmc_storage_t *storage);
 int sdmmc_storage_read(sdmmc_storage_t *storage, u32 sector, u32 num_sectors, void *buf);
 int sdmmc_storage_write(sdmmc_storage_t *storage, u32 sector, u32 num_sectors, void *buf);
-int sdmmc_storage_init_mmc(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 id, u32 bus_width, u32 type);
+int sdmmc_storage_init_mmc(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 bus_width, u32 type);
 int sdmmc_storage_set_mmc_partition(sdmmc_storage_t *storage, u32 partition);
-int sdmmc_storage_init_sd(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 id, u32 bus_width, u32 type);
+int sdmmc_storage_init_sd(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 bus_width, u32 type);
 int sdmmc_storage_init_gc(sdmmc_storage_t *storage, sdmmc_t *sdmmc);
 intptr_t sdmmc_calculate_dma_addr(sdmmc_accessor_t *_this, void *buf, unsigned int num_sectors);
 int sdmmc_calculate_dma_index(sdmmc_accessor_t *_this, void *buf, unsigned int num_sectors);

emummc/source/emmc/sdmmc_driver.h

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018-2019 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -49,24 +50,158 @@
 #define SDMMC_MASKINT_NOERROR -1
 #define SDMMC_MASKINT_ERROR   -2
 
-/*! SDMMC host control 2 */
-#define SDHCI_CTRL_UHS_MASK			0xFFF8
-#define SDHCI_CTRL_VDD_330			0xFFF7
-#define SDHCI_CTRL_VDD_180			8
-#define SDHCI_CTRL_EXEC_TUNING		0x40
-#define SDHCI_CTRL_TUNED_CLK		0x80
-#define SDHCI_HOST_VERSION_4_EN		0x1000
-#define SDHCI_ADDRESSING_64BIT_EN	0x2000
-#define SDHCI_CTRL_PRESET_VAL_EN	0x8000
+/*! SDMMC present state. */
+#define SDHCI_CMD_INHIBIT      0x1
+#define SDHCI_DATA_INHIBIT     0x2
+#define SDHCI_DOING_WRITE      0x100
+#define SDHCI_DOING_READ       0x200
+#define SDHCI_SPACE_AVAILABLE  0x400
+#define SDHCI_DATA_AVAILABLE   0x800
+#define SDHCI_CARD_PRESENT     0x10000
+#define SDHCI_CD_STABLE        0x20000
+#define SDHCI_CD_LVL           0x40000
+#define SDHCI_WRITE_PROTECT    0x80000
+#define SDHCI_DATA_LVL_MASK    0xF00000
+#define  SDHCI_DATA_0_LVL_MASK 0x100000
+#define SDHCI_CMD_LVL          0x1000000
+
+/*! SDMMC transfer mode. */
+#define SDHCI_TRNS_DMA        0x01
+#define SDHCI_TRNS_BLK_CNT_EN 0x02
+#define SDHCI_TRNS_AUTO_CMD12 0x04
+#define SDHCI_TRNS_AUTO_CMD23 0x08
+#define SDHCI_TRNS_AUTO_SEL   0x0C
+#define SDHCI_TRNS_WRITE      0x00
+#define SDHCI_TRNS_READ       0x10
+#define SDHCI_TRNS_MULTI      0x20
+
+/*! SDMMC command. */
+#define SDHCI_CMD_RESP_MASK       0x3
+#define SDHCI_CMD_RESP_NO_RESP    0x0
+#define SDHCI_CMD_RESP_LEN136     0x1
+#define SDHCI_CMD_RESP_LEN48      0x2
+#define SDHCI_CMD_RESP_LEN48_BUSY 0x3
+#define SDHCI_CMD_CRC       0x08
+#define SDHCI_CMD_INDEX     0x10
+#define SDHCI_CMD_DATA      0x20
+#define SDHCI_CMD_ABORTCMD  0xC0
+
+/*! SDMMC host control. */
+#define SDHCI_CTRL_LED        0x01
+#define SDHCI_CTRL_4BITBUS    0x02
+#define SDHCI_CTRL_HISPD      0x04
+#define SDHCI_CTRL_DMA_MASK   0x18
+#define  SDHCI_CTRL_SDMA      0x00
+#define  SDHCI_CTRL_ADMA1     0x08
+#define  SDHCI_CTRL_ADMA32    0x10
+#define  SDHCI_CTRL_ADMA64    0x18
+#define  SDHCI_CTRL_8BITBUS   0x20
+#define SDHCI_CTRL_CDTEST_INS 0x40
+#define SDHCI_CTRL_CDTEST_EN  0x80
+
+/*! SDMMC host control 2. */
+#define SDHCI_CTRL_UHS_MASK       0xFFF8
+#define SDHCI_CTRL_VDD_180        8
+#define SDHCI_CTRL_DRV_TYPE_B     0x00
+#define SDHCI_CTRL_DRV_TYPE_A     0x10
+#define SDHCI_CTRL_DRV_TYPE_C     0x20
+#define SDHCI_CTRL_DRV_TYPE_D     0x30
+#define SDHCI_CTRL_EXEC_TUNING    0x40
+#define SDHCI_CTRL_TUNED_CLK      0x80
+#define SDHCI_HOST_VERSION_4_EN   0x1000
+#define SDHCI_ADDRESSING_64BIT_EN 0x2000
+#define SDHCI_CTRL_PRESET_VAL_EN  0x8000
+
+/*! SDMMC power control. */
+#define SDHCI_POWER_ON   0x01
+#define SDHCI_POWER_180  0x0A
+#define SDHCI_POWER_300  0x0C
+#define SDHCI_POWER_330  0x0E
+#define SDHCI_POWER_MASK 0xF1
+
+// /*! SDMMC max current. */
+// #define SDHCI_MAX_CURRENT_330_MASK   0xFF
+// #define SDHCI_MAX_CURRENT_180_MASK   0xFF0000
+// #define SDHCI_MAX_CURRENT_MULTIPLIER 4
+
+/*! SDMMC clock control. */
+#define SDHCI_DIVIDER_SHIFT    8
+#define SDHCI_DIVIDER_HI_SHIFT 6
+#define SDHCI_DIV_MASK         0xFF00
+#define SDHCI_DIV_HI_MASK      0xC0
+#define SDHCI_PROG_CLOCK_MODE  0x20
+#define SDHCI_CLOCK_CARD_EN    0x4
+#define SDHCI_CLOCK_INT_STABLE 0x2
+#define SDHCI_CLOCK_INT_EN     0x1
+
+/*! SDMMC software reset. */
+#define SDHCI_RESET_ALL  0x01
+#define SDHCI_RESET_CMD  0x02
+#define SDHCI_RESET_DATA 0x04
+
+/*! SDMMC interrupt status and control. */
+#define SDHCI_INT_RESPONSE     0x1
+#define SDHCI_INT_DATA_END     0x2
+#define SDHCI_INT_BLK_GAP      0x4
+#define SDHCI_INT_DMA_END      0x8
+#define SDHCI_INT_SPACE_AVAIL  0x10
+#define SDHCI_INT_DATA_AVAIL   0x20
+#define SDHCI_INT_CARD_INSERT  0x40
+#define SDHCI_INT_CARD_REMOVE  0x80
+#define SDHCI_INT_CARD_INT     0x100
+#define SDHCI_INT_RETUNE       0x1000
+#define SDHCI_INT_CQE          0x4000
+#define SDHCI_INT_ERROR        0x8000
+
+/*! SDMMC error interrupt status and control. */
+#define SDHCI_ERR_INT_TIMEOUT      0x1
+#define SDHCI_ERR_INT_CRC          0x2
+#define SDHCI_ERR_INT_END_BIT      0x4
+#define SDHCI_ERR_INT_INDEX        0x8
+#define SDHCI_ERR_INT_DATA_TIMEOUT 0x10
+#define SDHCI_ERR_INT_DATA_CRC     0x20
+#define SDHCI_ERR_INT_DATA_END_BIT 0x40
+#define SDHCI_ERR_INT_BUS_POWER    0x80
+#define SDHCI_ERR_INT_AUTO_CMD_ERR 0x100
+#define SDHCI_ERR_INT_ADMA_ERROR   0x200
+
+#define SDHCI_ERR_INT_ALL_EXCEPT_ADMA_BUSPWR \
+	(SDHCI_ERR_INT_AUTO_CMD_ERR | SDHCI_ERR_INT_DATA_END_BIT | \
+	 SDHCI_ERR_INT_DATA_CRC | SDHCI_ERR_INT_DATA_TIMEOUT | \
+	 SDHCI_ERR_INT_INDEX | SDHCI_ERR_INT_END_BIT | \
+	 SDHCI_ERR_INT_CRC | SDHCI_ERR_INT_TIMEOUT)
 
 /*! SD bus speeds. */
-#define UHS_SDR12_BUS_SPEED		0
-#define HIGH_SPEED_BUS_SPEED	1
-#define UHS_SDR25_BUS_SPEED		1
-#define UHS_SDR50_BUS_SPEED		2
-#define UHS_SDR104_BUS_SPEED	3
-#define UHS_DDR50_BUS_SPEED		4
-#define HS400_BUS_SPEED 		5
+#define UHS_SDR12_BUS_SPEED  0
+#define HIGH_SPEED_BUS_SPEED 1
+#define UHS_SDR25_BUS_SPEED  1
+#define UHS_SDR50_BUS_SPEED  2
+#define UHS_SDR104_BUS_SPEED 3
+#define UHS_DDR50_BUS_SPEED  4
+#define HS400_BUS_SPEED      5
+
+/*! SDMMC timmings. */
+#define SDHCI_TIMING_MMC_ID     0
+#define SDHCI_TIMING_MMC_LS26   1
+#define SDHCI_TIMING_MMC_HS52   2
+#define SDHCI_TIMING_MMC_HS200  3
+#define SDHCI_TIMING_MMC_HS400  4
+#define SDHCI_TIMING_SD_ID      5
+#define SDHCI_TIMING_SD_DS12    6
+#define SDHCI_TIMING_SD_HS25    7
+#define SDHCI_TIMING_UHS_SDR12  8
+#define SDHCI_TIMING_UHS_SDR25  9
+#define SDHCI_TIMING_UHS_SDR50  10
+#define SDHCI_TIMING_UHS_SDR104 11
+#define SDHCI_TIMING_UHS_SDR82  12 // SDR104 with a 163.2MHz -> 81.6MHz clock.
+#define SDHCI_TIMING_UHS_DDR50  13
+#define SDHCI_TIMING_MMC_DDR52  14
+
+#define SDHCI_CAN_64BIT 0x10000000
+
+/*! SDMMC Low power features. */
+#define SDMMC_AUTO_CAL_DISABLE 0
+#define SDMMC_AUTO_CAL_ENABLE  1
 
 /*! Helper for SWITCH command argument. */
 #define SDMMC_SWITCH(mode, index, value) (((mode) << 24) | ((index) << 16) | ((value) << 8))
@@ -78,8 +213,8 @@ typedef struct _sdmmc_t
 	u32 id;
 	u32 divisor;
 	u32 clock_stopped;
-	int no_sd;
-	int sd_clock_enabled;
+	int auto_cal_enabled;
+	int card_clock_enabled;
 	int venclkctl_set;
 	u32 venclkctl_tap;
 	u32 expected_rsp_type;
@@ -109,19 +244,21 @@ typedef struct _sdmmc_req_t
 	int is_auto_cmd12;
 } sdmmc_req_t;
 
-int sdmmc_get_voltage(sdmmc_t *sdmmc);
-u32 sdmmc_get_bus_width(sdmmc_t *sdmmc);
+int  sdmmc_get_io_power(sdmmc_t *sdmmc);
+u32  sdmmc_get_bus_width(sdmmc_t *sdmmc);
 void sdmmc_set_bus_width(sdmmc_t *sdmmc, u32 bus_width);
-void sdmmc_get_venclkctl(sdmmc_t *sdmmc);
-int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type);
-void sdmmc_sd_clock_ctrl(sdmmc_t *sdmmc, int no_sd);
-int sdmmc_get_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 size, u32 type);
-int sdmmc_config_tuning(sdmmc_t *sdmmc, u32 type, u32 cmd);
-int sdmmc_stop_transmission(sdmmc_t *sdmmc, u32 *rsp);
-int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int no_sd);
+void sdmmc_set_tap_value(sdmmc_t *sdmmc);
+int  sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type);
+void sdmmc_card_clock_ctrl(sdmmc_t *sdmmc, int auto_cal_enable);
+int  sdmmc_get_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 size, u32 type);
+int  sdmmc_tuning_execute(sdmmc_t *sdmmc, u32 type, u32 cmd);
+int  sdmmc_stop_transmission(sdmmc_t *sdmmc, u32 *rsp);
+int  sdmmc_get_sd_power_enabled();
+bool sdmmc_get_sd_inserted();
+int  sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int auto_cal_enable);
 void sdmmc_end(sdmmc_t *sdmmc);
 void sdmmc_init_cmd(sdmmc_cmd_t *cmdbuf, u16 cmd, u32 arg, u32 rsp_type, u32 check_busy);
-int sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *blkcnt_out);
-int sdmmc_enable_low_voltage(sdmmc_t *sdmmc);
+int  sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *blkcnt_out);
+int  sdmmc_enable_low_voltage(sdmmc_t *sdmmc);
 
 #endif

emummc/source/emmc/sdmmc_t210.h

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018-2019 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -19,49 +20,14 @@
 
 #include "../utils/types.h"
 
-#define TEGRA_MMC_PWRCTL_SD_BUS_POWER 0x1
-#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8 0xA
-#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0 0xC
-#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3 0xE
-#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_MASK 0xF1
-
-#define TEGRA_MMC_HOSTCTL_1BIT 0x00
-#define TEGRA_MMC_HOSTCTL_4BIT 0x02
-#define TEGRA_MMC_HOSTCTL_8BIT 0x20
-
-#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE 0x1
-#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE 0x2
-#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE 0x4
-#define TEGRA_MMC_CLKCON_CLKGEN_SELECT 0x20
-
-#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL 0x1
-#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE 0x2
-#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE 0x4
-
-#define TEGRA_MMC_TRNMOD_DMA_ENABLE 0x1
-#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE 0x2
-#define TEGRA_MMC_TRNMOD_AUTO_CMD12 0x4
-#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE 0x0
-#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ 0x10
-#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT 0x20
-
-#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK 0x8
-#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK 0x10
-#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER 0x20
-
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK 0x3
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE 0x0
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 0x1
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 0x2
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY 0x3
-
-#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE 0x1
-#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE 0x2
-#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT 0x8
-#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT 0x8000
-#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT 0x10000
-
-#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY 0x20
+#define TEGRA_MMC_VNDR_TUN_CTRL0_TAP_VAL_UPDATED_BY_HW 0x20000
+#define TEGRA_MMC_DLLCAL_CFG_EN_CALIBRATE 0x80000000
+#define TEGRA_MMC_DLLCAL_CFG_STATUS_DLL_ACTIVE 0x80000000
+#define TEGRA_MMC_SDMEMCOMPPADCTRL_PAD_E_INPUT_PWRD 0x80000000
+#define TEGRA_MMC_SDMEMCOMPPADCTRL_COMP_VREF_SEL_MASK 0xFFFFFFF0
+#define TEGRA_MMC_AUTOCALCFG_AUTO_CAL_ENABLE 0x20000000
+#define TEGRA_MMC_AUTOCALCFG_AUTO_CAL_START 0x80000000
+#define TEGRA_MMC_AUTOCALSTS_AUTO_CAL_ACTIVE 0x80000000
 
 typedef struct _t210_sdmmc_t
 {
@@ -77,56 +43,66 @@ typedef struct _t210_sdmmc_t
 	vu32 rspreg3;
 	vu32 bdata;
 	vu32 prnsts;
-	vu8 hostctl;
-	vu8 pwrcon;
-	vu8 blkgap;
-	vu8 wakcon;
+	vu8  hostctl;
+	vu8  pwrcon;
+	vu8  blkgap;
+	vu8  wakcon;
 	vu16 clkcon;
-	vu8 timeoutcon;
-	vu8 swrst;
+	vu8  timeoutcon;
+	vu8  swrst;
 	vu16 norintsts;
 	vu16 errintsts;
-	vu16 norintstsen;
-	vu16 errintstsen;
-	vu16 norintsigen;
-	vu16 errintsigen;
+	vu16 norintstsen; // Enable irq status.
+	vu16 errintstsen; // Enable irq status.
+	vu16 norintsigen; // Enable irq signal to LIC/GIC.
+	vu16 errintsigen; // Enable irq signal to LIC/GIC.
 	vu16 acmd12errsts;
 	vu16 hostctl2;
 	vu32 capareg;
 	vu32 capareg_1;
 	vu32 maxcurr;
-	vu8 res3[4];
+	vu8  rsvd0[4]; // 4C-4F reserved for more max current.
 	vu16 setacmd12err;
 	vu16 setinterr;
-	vu8 admaerr;
-	vu8 res4[3];
+	vu8  admaerr;
+	vu8  rsvd1[3]; // 55-57 reserved.
 	vu32 admaaddr;
 	vu32 admaaddr_hi;
-	vu8 res5[156];
-	vu16 slotintstatus;
+	vu8  rsvd2[156]; // 60-FB reserved.
+	vu16 slotintsts;
 	vu16 hcver;
 	vu32 venclkctl;
-	vu32 venspictl;
-	vu32 venspiintsts;
-	vu32 venceatactl;
+	vu32 vensysswctl;
+	vu32 venerrintsts;
+	vu32 vencapover;
 	vu32 venbootctl;
 	vu32 venbootacktout;
 	vu32 venbootdattout;
 	vu32 vendebouncecnt;
 	vu32 venmiscctl;
-	vu32 res6[34];
+	vu32 maxcurrover;
+	vu32 maxcurrover_hi;
+	vu32 unk0[32]; // 0x12C
 	vu32 veniotrimctl;
-	vu32 vendllcal;
-	vu8 res7[8];
-	vu32 dllcfgstatus;
+	vu32 vendllcalcfg;
+	vu32 vendllctl0;
+	vu32 vendllctl1;
+	vu32 vendllcalcfgsts;
 	vu32 ventunctl0;
-	vu32 field_1C4;
-	vu8 field_1C8[24];
+	vu32 ventunctl1;
+	vu32 ventunsts0;
+	vu32 ventunsts1;
+	vu32 venclkgatehystcnt;
+	vu32 venpresetval0;
+	vu32 venpresetval1;
+	vu32 venpresetval2;
 	vu32 sdmemcmppadctl;
 	vu32 autocalcfg;
 	vu32 autocalintval;
 	vu32 autocalsts;
 	vu32 iospare;
+	vu32 mcciffifoctl;
+	vu32 timeoutwcoal;
 } t210_sdmmc_t;
 
 #endif

emummc/source/emuMMC/emummc.c

@@ -18,14 +18,12 @@
 
 #include <stdlib.h>
 
-#include "../soc/gpio.h"
-#include "../utils/fatal.h"
-#include "../libs/fatfs/diskio.h"
 #include "emummc.h"
 #include "emummc_ctx.h"
+#include "../utils/fatal.h"
+#include "../libs/fatfs/diskio.h"
 
 static bool sdmmc_first_init = false;
-static bool storageMMCinitialized = false;
 static bool storageSDinitialized = false;
 
 // hekate sdmmmc vars
@@ -35,6 +33,7 @@ sdmmc_t sd_sdmmc;
 sdmmc_storage_t sd_storage;
 
 // init vars
+bool init_done = false;
 bool custom_driver = true;
 
 // FS funcs
@@ -51,8 +50,8 @@ volatile int *active_partition;
 volatile Handle *sdmmc_das_handle;
 
 // FatFS
+file_based_ctxt f_emu;
 static bool fat_mounted = false;
-static file_based_ctxt f_emu;
 
 static void _sdmmc_ensure_device_attached(void)
 {
@@ -68,8 +67,6 @@ static void _sdmmc_ensure_device_attached(void)
 
 static void _sdmmc_ensure_initialized(void)
 {
-    static bool init_done = false;
-
     // First Initial init
     if (!sdmmc_first_init)
     {
@@ -78,10 +75,11 @@ static void _sdmmc_ensure_initialized(void)
     }
     else
     {
-        // The boot sysmodule will eventually kill power to SD. Detect this, and reinitialize when it happens.
+        // The boot sysmodule will eventually kill power to SD.
+        // Detect this, and reinitialize when it happens.
         if (!init_done)
         {
-            if (gpio_read(GPIO_PORT_E, GPIO_PIN_4) == 0)
+            if (sdmmc_get_sd_power_enabled() == 0)
             {
                 sdmmc_finalize();
                 sdmmc_initialize();
@@ -118,8 +116,6 @@ static void _file_based_emmc_finalize(void)
 
 void sdmmc_finalize(void)
 {
-    _file_based_emmc_finalize();
-
     if (!sdmmc_storage_end(&sd_storage))
     {
         fatal_abort(Fatal_InitSD);
@@ -132,7 +128,6 @@ static void _file_based_emmc_initialize(void)
 {
     char path[sizeof(emuMMC_ctx.storagePath) + 0x20];
     memset(&path, 0, sizeof(path));
-    memset(&f_emu, 0, sizeof(file_based_ctxt));
 
     memcpy(path, (void *)emuMMC_ctx.storagePath, sizeof(emuMMC_ctx.storagePath));
     strcat(path, "/eMMC/");
@@ -141,18 +136,24 @@ static void _file_based_emmc_initialize(void)
     // Open BOOT0 physical partition.
     memcpy(path + path_len, "BOOT0", 6);
     if (f_open(&f_emu.fp_boot0, path, FA_READ | FA_WRITE) != FR_OK)
-        fatal_abort(Fatal_InitSD);
+        fatal_abort(Fatal_FatfsFileOpen);
+    if (!f_expand_cltbl(&f_emu.fp_boot0, 0x400, f_emu.clmt_boot0, f_size(&f_emu.fp_boot0)))
+        fatal_abort(Fatal_FatfsMemExhaustion);
 
     // Open BOOT1 physical partition.
     memcpy(path + path_len, "BOOT1", 6);
     if (f_open(&f_emu.fp_boot1, path, FA_READ | FA_WRITE) != FR_OK)
-        fatal_abort(Fatal_InitSD);
+        fatal_abort(Fatal_FatfsFileOpen);
+    if (!f_expand_cltbl(&f_emu.fp_boot1, 0x400, f_emu.clmt_boot1, f_size(&f_emu.fp_boot1)))
+        fatal_abort(Fatal_FatfsMemExhaustion);
 
     // Open handles for GPP physical partition files.
     _file_based_update_filename(path, path_len, 00);
 
     if (f_open(&f_emu.fp_gpp[0], path, FA_READ | FA_WRITE) != FR_OK)
-        fatal_abort(Fatal_InitSD);
+        fatal_abort(Fatal_FatfsFileOpen);
+    if (!f_expand_cltbl(&f_emu.fp_gpp[0], 0x400, &f_emu.clmt_gpp[0], f_size(&f_emu.fp_gpp[0])))
+        fatal_abort(Fatal_FatfsMemExhaustion);
 
     f_emu.part_size = f_size(&f_emu.fp_gpp[0]) >> 9;
 
@@ -171,38 +172,27 @@ static void _file_based_emmc_initialize(void)
 
             return;
         }
+
+        if (!f_expand_cltbl(&f_emu.fp_gpp[f_emu.parts], 0x400, &f_emu.clmt_gpp[f_emu.parts * 0x400], f_size(&f_emu.fp_gpp[f_emu.parts])))
+            fatal_abort(Fatal_FatfsMemExhaustion);
     }
 }
 
 bool sdmmc_initialize(void)
 {
-    if (!storageMMCinitialized)
-    {
-        if (sdmmc_storage_init_mmc(&storage, &sdmmc, SDMMC_4, SDMMC_BUS_WIDTH_8, 4))
-        {
-            if (sdmmc_storage_set_mmc_partition(&storage, FS_EMMC_PARTITION_GPP))
-                storageMMCinitialized = true;
-        }
-        else
-        {
-            fatal_abort(Fatal_InitMMC);
-        }
-    }
-
     if (!storageSDinitialized)
     {
-        int retries = 5;
+        int retries = 3;
         while (retries)
         {
-            if (sdmmc_storage_init_sd(&sd_storage, &sd_sdmmc, SDMMC_1, SDMMC_BUS_WIDTH_4, 11))
+            if (nx_sd_initialize(false))
             {
                 storageSDinitialized = true;
 
                 // File based emummc.
                 if ((emuMMC_ctx.EMMC_Type == emuMMC_SD_File) && !fat_mounted)
                 {
-                    f_emu.sd_fs = (FATFS *)malloc(sizeof(FATFS));
-                    if (f_mount(f_emu.sd_fs, "", 1) != FR_OK)
+                    if (f_mount(&f_emu.sd_fs, "", 1) != FR_OK)
                         fatal_abort(Fatal_InitSD);
                     else
                         fat_mounted = true;
@@ -214,7 +204,6 @@ bool sdmmc_initialize(void)
             }
 
             retries--;
-            msleep(100);
         }
 
         if (!storageSDinitialized)
@@ -223,7 +212,7 @@ bool sdmmc_initialize(void)
         }
     }
 
-    return storageMMCinitialized && storageSDinitialized;
+    return storageSDinitialized;
 }
 
 sdmmc_accessor_t *sdmmc_accessor_get(int mmc_id)
@@ -295,38 +284,36 @@ static uint64_t emummc_read_write_inner(void *buf, unsigned int sector, unsigned
     }
 
     // File based emummc.
-    FIL *fp_tmp = NULL;
+    FIL *fp = NULL;
     switch (*active_partition)
     {
     case FS_EMMC_PARTITION_GPP:
         if (f_emu.parts)
         {
-            fp_tmp = &f_emu.fp_gpp[sector / f_emu.part_size];
+            fp = &f_emu.fp_gpp[sector / f_emu.part_size];
             sector = sector % f_emu.part_size;
         }
         else
         {
-            fp_tmp = &f_emu.fp_gpp[0];
+            fp = &f_emu.fp_gpp[0];
         }
         break;
     case FS_EMMC_PARTITION_BOOT1:
-        fp_tmp = &f_emu.fp_boot1;
+        fp = &f_emu.fp_boot1;
         break;
     case FS_EMMC_PARTITION_BOOT0:
-        fp_tmp = &f_emu.fp_boot0;
+        fp = &f_emu.fp_boot0;
         break;
     }
 
-    if (f_lseek(fp_tmp, sector << 9) != FR_OK)
-    {
-        ; //TODO. Out of range. close stuff and fatal?
-    }
+    if (f_lseek(fp, sector << 9) != FR_OK)
+        return 0; // Out of bounds.
 
     uint64_t res = 0;
     if (!is_write)
-        res = !(f_read(fp_tmp, buf, num_sectors << 9, NULL));
+        res = !f_read_fast(fp, buf, num_sectors << 9);
     else
-        res = !(f_write(fp_tmp, buf, num_sectors << 9, NULL));
+        res = !f_write_fast(fp, buf, num_sectors << 9);
 
     return res;
 }
@@ -402,12 +389,15 @@ uint64_t sdmmc_wrapper_read(void *buf, uint64_t bufSize, int mmc_id, unsigned in
             if (first_sd_read)
             {
                 first_sd_read = false;
-                // Because some SD cards have issues with emuMMC's driver
-                // we currently swap to FS's driver after first SD read
-                // TODO: Fix remaining driver issues
-                custom_driver = false;
-                // FS will handle sd mutex w/o custom driver from here on
-                unlock_mutex(sd_mutex);
+                if (emuMMC_ctx.EMMC_Type == emuMMC_SD)
+                {
+                    // Because some SD cards have issues with emuMMC's driver
+                    // we currently swap to FS's driver after first SD read
+                    // for raw based emuMMC
+                    custom_driver = false;
+                    // FS will handle sd mutex w/o custom driver from here on
+                    unlock_mutex(sd_mutex);
+                }
             }
 
             // Call hekates driver.

emummc/source/emuMMC/emummc.h

@@ -28,6 +28,7 @@ extern "C" {
 #include <stdio.h>
 #include <string.h>
 
+#include "../emmc/nx_sd.h"
 #include "../emmc/sdmmc.h"
 #include "../soc/i2c.h"
 #include "../soc/gpio.h"
@@ -55,15 +56,17 @@ uint64_t sdmmc_wrapper_controller_close(int mmc_id);
 uint64_t sdmmc_wrapper_read(void *buf, uint64_t bufSize, int mmc_id, unsigned int sector, unsigned int num_sectors);
 uint64_t sdmmc_wrapper_write(int mmc_id, unsigned int sector, unsigned int num_sectors, void *buf, uint64_t bufSize);
 
-// TODO: check if FatFS internal buffers are good (perf wise) to have a x16 alignment.
 typedef struct _file_based_ctxt
 {
+	FATFS sd_fs;
 	uint64_t parts;
 	uint64_t part_size;
-	FATFS *sd_fs;
 	FIL fp_boot0;
+	DWORD clmt_boot0[0x400];
 	FIL fp_boot1;
+	DWORD clmt_boot1[0x400];
 	FIL fp_gpp[32];
+	DWORD clmt_gpp[0x8000];
 } file_based_ctxt;
 
 #ifdef __cplusplus

emummc/source/libs/fatfs/ff.c

@@ -1,10 +1,25 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018-2019 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
 /*----------------------------------------------------------------------------/
-/  FatFs - Generic FAT Filesystem Module  R0.13c (p3)                         /
+/  FatFs - Generic FAT Filesystem Module  R0.13c (p4)                         /
 /-----------------------------------------------------------------------------/
 /
 / Copyright (C) 2018, ChaN, all right reserved.
-/ Copyright (c) 2018 naehrwert
-/ Copyright (C) 2018-2019 CTCaer
 /
 / FatFs module is an open source software. Redistribution and use of FatFs in
 / source and binary forms, with or without modification, are permitted provided
@@ -515,7 +530,7 @@ static WCHAR LfnBuf[FF_MAX_LFN + 1];		/* LFN working buffer */
 #define FREE_NAMBUF()	ff_memfree(lfn)
 #endif
 #define LEAVE_MKFS(res)	{ if (!work) ff_memfree(buf); return res; }
-#define MAX_MALLOC	0x8000	/* Must be >=FF_MAX_SS */
+#define MAX_MALLOC	0x4000	/* Must be >=FF_MAX_SS */
 
 #else
 #error Wrong setting of FF_USE_LFN
@@ -3879,6 +3894,109 @@ FRESULT f_read (
 
 
 
+#ifdef FF_FASTFS
+/*-----------------------------------------------------------------------*/
+/* Fast Read Aligned Sized File Without a Cache                         */
+/*-----------------------------------------------------------------------*/
+#if FF_USE_FASTSEEK
+FRESULT f_read_fast (
+	FIL* fp,			/* Pointer to the file object */
+	const void* buff,	/* Pointer to the data to be written */
+	UINT btr			/* Number of bytes to read */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	UINT csize_bytes;
+	DWORD clst;
+	DWORD wbytes;
+	UINT count;
+	FSIZE_t work_sector = 0;
+	FSIZE_t sector_base = 0;
+	BYTE *wbuff = (BYTE*)buff;
+
+	res = validate(&fp->obj, &fs);			/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) {
+		EFSPRINTF("FOV");
+		LEAVE_FF(fs, res);	/* Check validity */
+	}
+
+	if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */
+	FSIZE_t remain = fp->obj.objsize - fp->fptr;
+	if (btr > remain) btr = (UINT)remain;		/* Truncate btr by remaining bytes */
+
+	csize_bytes = fs->csize * SS(fs);
+	DWORD csect = (UINT)((fp->fptr / SS(fs)) & (fs->csize - 1));	/* Sector offset in the cluster */
+
+	/* If inside a cluster, read the sectors and align to cluster. */
+	if (csect) {
+		wbytes = MIN(btr, (fs->csize - csect) * SS(fs));
+		f_read(fp, wbuff, wbytes, (void *)0);
+		wbuff += wbytes;
+		btr -= wbytes;
+		if (!btr)
+			goto out;
+	}
+
+	if (!fp->fptr) {	/* On the top of the file? */
+		clst = fp->obj.sclust;	/* Follow from the origin */
+	} else {
+		if (fp->cltbl) clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+		else { EFSPRINTF("CLTBL"); ABORT(fs, FR_CLTBL_NO_INIT); }
+	}
+
+	if (clst < 2) { EFSPRINTF("CCHK"); ABORT(fs, FR_INT_ERR); }
+	else if (clst == 0xFFFFFFFF) { EFSPRINTF("DSKC"); ABORT(fs, FR_DISK_ERR); }
+
+	fp->clust = clst;	/* Set working cluster */
+
+	wbytes = MIN(btr, csize_bytes);
+	sector_base = clst2sect(fs, fp->clust);
+	count = wbytes / SS(fs);
+	fp->fptr += wbytes;
+	btr -= wbytes;
+
+	if (!btr) {	/* Final cluster/sectors read. */
+		if (disk_read(fs->pdrv, wbuff, sector_base, count) != RES_OK) ABORT(fs, FR_DISK_ERR);
+		goto out;
+	}
+
+	while (btr) {
+		clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+
+		if (clst < 2) { EFSPRINTF("CCHK2"); ABORT(fs, FR_INT_ERR); }
+		else if (clst == 0xFFFFFFFF) { EFSPRINTF("DSKC"); ABORT(fs, FR_DISK_ERR); }
+
+		fp->clust = clst;
+
+		work_sector = clst2sect(fs, fp->clust);
+		wbytes = MIN(btr, csize_bytes);
+		if ((work_sector - sector_base) == count) count += wbytes / SS(fs);
+		else {
+			if (disk_read(fs->pdrv, wbuff, sector_base, count) != RES_OK) ABORT(fs, FR_DISK_ERR);
+			wbuff += count * SS(fs);
+
+			sector_base = work_sector;
+			count = wbytes / SS(fs);
+		}
+
+		fp->fptr += wbytes;
+		btr -= wbytes;
+
+		if (!btr) {	/* Final cluster/sectors read. */
+			if (disk_read(fs->pdrv, wbuff, sector_base, count) != RES_OK) ABORT(fs, FR_DISK_ERR);
+		}
+	}
+
+out:
+	LEAVE_FF(fs, FR_OK);
+}
+#endif
+#endif
+
+
+
+
 #if !FF_FS_READONLY
 /*-----------------------------------------------------------------------*/
 /* Write File                                                            */
@@ -4018,6 +4136,117 @@ FRESULT f_write (
 
 
 
+#ifdef FF_FASTFS
+/*-----------------------------------------------------------------------*/
+/* Fast Write Aligned Sized File Without a Cache                         */
+/*-----------------------------------------------------------------------*/
+#if FF_USE_FASTSEEK
+FRESULT f_write_fast (
+	FIL* fp,			/* Pointer to the file object */
+	const void* buff,	/* Pointer to the data to be written */
+	UINT btw			/* Number of bytes to write */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	UINT csize_bytes;
+	DWORD clst;
+	DWORD wbytes;
+	UINT count;
+	FSIZE_t work_sector = 0;
+	FSIZE_t sector_base = 0;
+	BYTE *wbuff = (BYTE*)buff;
+
+	res = validate(&fp->obj, &fs);			/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) {
+		EFSPRINTF("FOV");
+		LEAVE_FF(fs, res);	/* Check validity */
+	}
+
+	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+	/* Check fptr wrap-around (file size cannot reach 4 GiB at FAT volume) */
+	if ((!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) && (DWORD)(fp->fptr + btw) < (DWORD)fp->fptr) {
+		btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr);
+	}
+
+	csize_bytes = fs->csize * SS(fs);
+	DWORD csect = (UINT)((fp->fptr / SS(fs)) & (fs->csize - 1));	/* Sector offset in the cluster */
+
+	/* If inside a cluster, write the sectors and align to cluster. */
+	if (csect) {
+		wbytes = MIN(btw, (fs->csize - csect) * SS(fs));
+		f_write(fp, wbuff, wbytes, (void *)0);
+		/* Ensure flushing of it. FatFS is not notified for next write if raw. */
+		f_sync(fp);
+		wbuff += wbytes;
+		btw -= wbytes;
+		if (!btw)
+			goto out;
+	}
+
+	if (!fp->fptr) {	/* On the top of the file? */
+		clst = fp->obj.sclust;	/* Follow from the origin */
+	} else {
+		if (fp->cltbl) clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+		else { EFSPRINTF("CLTBL"); ABORT(fs, FR_CLTBL_NO_INIT); }
+	}
+
+	if (clst < 2) { EFSPRINTF("CCHK"); ABORT(fs, FR_INT_ERR); }
+	else if (clst == 0xFFFFFFFF) { EFSPRINTF("DSKC"); ABORT(fs, FR_DISK_ERR); }
+
+	fp->clust = clst;	/* Set working cluster */
+
+	wbytes = MIN(btw, csize_bytes);
+	sector_base = clst2sect(fs, fp->clust);
+	count = wbytes / SS(fs);
+	fp->fptr += wbytes;
+	btw -= wbytes;
+
+	if (!btw) {	/* Final cluster/sectors write. */
+		if (disk_write(fs->pdrv, wbuff, sector_base, count) != RES_OK) ABORT(fs, FR_DISK_ERR);
+		fp->flag &= (BYTE)~FA_DIRTY;
+		goto out;
+	}
+
+	while (btw) {
+		clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+
+		if (clst < 2) { EFSPRINTF("CCHK2"); ABORT(fs, FR_INT_ERR); }
+		else if (clst == 0xFFFFFFFF) { EFSPRINTF("DSKC"); ABORT(fs, FR_DISK_ERR); }
+
+		fp->clust = clst;
+
+		work_sector = clst2sect(fs, fp->clust);
+		wbytes = MIN(btw, csize_bytes);
+		if ((work_sector - sector_base) == count) count += wbytes / SS(fs);
+		else {
+			if (disk_write(fs->pdrv, wbuff, sector_base, count) != RES_OK) ABORT(fs, FR_DISK_ERR);
+			wbuff += count * SS(fs);
+
+			sector_base = work_sector;
+			count = wbytes / SS(fs);
+		}
+
+		fp->fptr += wbytes;
+		btw -= wbytes;
+
+		if (!btw) {	/* Final cluster/sectors write. */
+			if (disk_write(fs->pdrv, wbuff, sector_base, count) != RES_OK) ABORT(fs, FR_DISK_ERR);
+			fp->flag &= (BYTE)~FA_DIRTY;
+		}
+	}
+
+out:
+	fp->flag |= FA_MODIFIED;	/* Set file change flag */
+
+	LEAVE_FF(fs, FR_OK);
+}
+#endif
+#endif
+
+
+
+
 /*-----------------------------------------------------------------------*/
 /* Synchronize the File                                                  */
 /*-----------------------------------------------------------------------*/
@@ -4231,9 +4460,9 @@ FRESULT f_getcwd (
 	TCHAR *tp = buff;
 #if FF_VOLUMES >= 2
 	UINT vl;
-#endif
 #if FF_STR_VOLUME_ID
 	const char *vp;
+#endif
 #endif
 	FILINFO fno;
 	DEF_NAMBUF
@@ -4474,6 +4703,37 @@ FRESULT f_lseek (
 
 
 
+#ifdef FF_FASTFS
+#if FF_USE_FASTSEEK
+/*-----------------------------------------------------------------------*/
+/* Seek File Read/Write Pointer                                          */
+/*-----------------------------------------------------------------------*/
+
+DWORD *f_expand_cltbl (
+	FIL* fp,		/* Pointer to the file object */
+	UINT tblsz,		/* Size of table */
+	DWORD *tbl,		/* Table pointer */
+	FSIZE_t ofs		/* File pointer from top of file */
+)
+{
+	if (fp->flag & FA_WRITE) f_lseek(fp, ofs);	/* Expand file if write is enabled */
+	fp->cltbl = (DWORD *)tbl;
+	fp->cltbl[0] = tblsz;
+	if (f_lseek(fp, CREATE_LINKMAP)) {	/* Create cluster link table */
+		fp->cltbl = (void *)0;
+		EFSPRINTF("CLTBLSZ");
+		return (void *)0;
+	}
+	f_lseek(fp, 0);
+
+	return fp->cltbl;
+}
+#endif
+#endif
+
+
+
+
 #if FF_FS_MINIMIZE <= 1
 /*-----------------------------------------------------------------------*/
 /* Create a Directory Object                                             */
@@ -4714,7 +4974,7 @@ FRESULT f_getfree (
 	/* Get logical drive */
 	res = find_volume(&path, &fs, 0);
 	if (res == FR_OK) {
-		*fatfs = fs;				/* Return ptr to the fs object */
+		if (fatfs) *fatfs = fs;	/* Return ptr to the fs object */
 		/* If free_clst is valid, return it without full FAT scan */
 		if (fs->free_clst <= fs->n_fatent - 2) {
 			*nclst = fs->free_clst;

emummc/source/libs/fatfs/ff.h

@@ -246,7 +246,12 @@ typedef enum {
 	FR_LOCKED,				/* (16) The operation is rejected according to the file sharing policy */
 	FR_NOT_ENOUGH_CORE,		/* (17) LFN working buffer could not be allocated */
 	FR_TOO_MANY_OPEN_FILES,	/* (18) Number of open files > FF_FS_LOCK */
+#ifdef FF_FASTFS
+	FR_INVALID_PARAMETER,	/* (19) Given parameter is invalid */
+	FR_CLTBL_NO_INIT	    /* (20) The cluster table for fast seek/read/write was not created */
+#else
 	FR_INVALID_PARAMETER	/* (19) Given parameter is invalid */
+#endif
 } FRESULT;
 
 
@@ -258,6 +263,10 @@ FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode);				/* Open or create a f
 FRESULT f_close (FIL* fp);											/* Close an open file object */
 FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br);			/* Read data from the file */
 FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw);	/* Write data to the file */
+#ifdef FF_FASTFS
+FRESULT f_read_fast (FIL* fp, const void* buff, UINT btr);			/* Fast read data from the file */
+FRESULT f_write_fast (FIL* fp, const void* buff, UINT btw);         /* Fast write data to the file */
+#endif
 FRESULT f_lseek (FIL* fp, FSIZE_t ofs);								/* Move file pointer of the file object */
 FRESULT f_truncate (FIL* fp);										/* Truncate the file */
 FRESULT f_sync (FIL* fp);											/* Flush cached data of the writing file */
@@ -279,7 +288,10 @@ FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs);	/* Get numbe
 FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn);	/* Get volume label */
 FRESULT f_setlabel (const TCHAR* label);							/* Set volume label */
 FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf);	/* Forward data to the stream */
-FRESULT f_expand (FIL* fp, FSIZE_t szf, BYTE opt);					/* Allocate a contiguous block to the file */
+#ifdef FF_FASTFS
+DWORD  *f_expand_cltbl (FIL* fp, UINT tblsz, DWORD *tbl, FSIZE_t ofs);	/* Expand file and populate cluster table */
+#endif
+FRESULT f_expand (FIL* fp, FSIZE_t fsz, BYTE opt);					/* Allocate a contiguous block to the file */
 FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt);			/* Mount/Unmount a logical drive */
 FRESULT f_mkfs (const TCHAR* path, BYTE opt, DWORD au, void* work, UINT len);	/* Create a FAT volume */
 FRESULT f_fdisk (BYTE pdrv, const DWORD* szt, void* work);			/* Divide a physical drive into some partitions */

emummc/source/libs/fatfs/ffconf.h

@@ -15,7 +15,7 @@
 /  and optional writing functions as well. */
 
 
-#define FF_FS_MINIMIZE	0
+#define FF_FS_MINIMIZE	2
 /* This option defines minimization level to remove some basic API functions.
 /
 /   0: Basic functions are fully enabled.
@@ -41,8 +41,13 @@
 #define FF_USE_MKFS		0
 /* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
 
+#define FF_FASTFS 1
 
+#ifdef FF_FASTFS
+#define FF_USE_FASTSEEK	1
+#else
 #define FF_USE_FASTSEEK	0
+#endif
 /* This option switches fast seek function. (0:Disable or 1:Enable) */
 
 
@@ -50,7 +55,7 @@
 /* This option switches f_expand function. (0:Disable or 1:Enable) */
 
 
-#define FF_USE_CHMOD	1
+#define FF_USE_CHMOD	0
 /* This option switches attribute manipulation functions, f_chmod() and f_utime().
 /  (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */
 
@@ -239,7 +244,7 @@
 #define FF_FS_NORTC		1
 #define FF_NORTC_MON	1
 #define FF_NORTC_MDAY	1
-#define FF_NORTC_YEAR	2019
+#define FF_NORTC_YEAR	2020
 /* The option FF_FS_NORTC switches timestamp function. If the system does not have
 /  any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable
 /  the timestamp function. Every object modified by FatFs will have a fixed timestamp

emummc/source/libs/fatfs/ffunicode.c

@@ -34,7 +34,6 @@
 #define MERGE2(a, b) a ## b
 #define CVTBL(tbl, cp) MERGE2(tbl, cp)
 
-
 /*------------------------------------------------------------------------*/
 /* Code Conversion Tables                                                 */
 /*------------------------------------------------------------------------*/
@@ -623,5 +622,4 @@ DWORD ff_wtoupper (	/* Returns up-converted code point */
 	return uni;
 }
 
-
 #endif /* #if FF_USE_LFN */

emummc/source/main.c

@@ -33,19 +33,22 @@
 void __init();
 void __initheap(void);
 void setup_hooks(void);
-void setup_nintendo_paths(void);
 void __libc_init_array(void);
+void setup_nintendo_paths(void);
 void hook_function(uintptr_t source, uintptr_t target);
 
 void *__stack_top;
 uintptr_t text_base;
+size_t fs_code_size;
+u8 *fs_rw_mapping = NULL;
+Handle self_proc_handle = 0;
 char inner_heap[INNER_HEAP_SIZE];
 size_t inner_heap_size = INNER_HEAP_SIZE;
+
 extern char _start;
 extern char __argdata__;
 
 // Nintendo Path
-// TODO
 static char nintendo_path[0x80] = "Nintendo";
 
 // 1.0.0 requires special path handling because it has separate album and contents paths.
@@ -60,6 +63,7 @@ static const fs_offsets_t *fs_offsets;
 // Defined by linkerscript
 #define INJECTED_SIZE ((uintptr_t)&__argdata__ - (uintptr_t)&_start)
 #define INJECT_OFFSET(type, offset) (type)(text_base + INJECTED_SIZE + offset)
+#define FS_CODE_BASE INJECT_OFFSET(uintptr_t, 0)
 
 #define GENERATE_ADD(register, register_target, value) (0x91000000 | value << 10 | register << 5 | register_target)
 #define GENERATE_ADRP(register, page_addr) (0x90000000 | ((((page_addr) >> 12) & 0x3) << 29) | ((((page_addr) >> 12) & 0x1FFFFC) << 3) | ((register) & 0x1F))
@@ -148,15 +152,117 @@ void __initheap(void)
     fake_heap_end = (char *)addr + size;
 }
 
+static void _receive_process_handle_thread(void *_session_handle) {
+    Result rc;
+
+    // Convert the argument to a handle we can use.
+    Handle session_handle = (Handle)(uintptr_t)_session_handle;
+
+    // Receive the request from the client thread.
+    memset(armGetTls(), 0, 0x10);
+    s32 idx = 0;
+    rc = svcReplyAndReceive(&idx, &session_handle, 1, INVALID_HANDLE, UINT64_MAX);
+    if (rc != 0)
+    {
+        fatal_abort(Fatal_BadResult);
+    }
+
+    // Set the process handle.
+    self_proc_handle = ((u32 *)armGetTls())[3];
+
+    // Close the session.
+    svcCloseHandle(session_handle);
+
+    // Terminate ourselves.
+    svcExitThread();
+
+    // This code will never execute.
+    while (true);
+}
+
+static void _init_process_handle(void) {
+    Result rc;
+    u8 temp_thread_stack[0x1000];
+
+    // Create a new session to transfer our process handle to ourself
+    Handle server_handle, client_handle;
+    rc = svcCreateSession(&server_handle, &client_handle, 0, 0);
+    if (rc != 0)
+    {
+        fatal_abort(Fatal_BadResult);
+    }
+
+    // Create a new thread to receive our handle.
+    Handle thread_handle;
+    rc = svcCreateThread(&thread_handle, _receive_process_handle_thread, (void *)(uintptr_t)server_handle, temp_thread_stack + sizeof(temp_thread_stack), 0x20, 3);
+    if (rc != 0)
+    {
+        fatal_abort(Fatal_BadResult);
+    }
+
+    // Start the new thread.
+    rc = svcStartThread(thread_handle);
+    if (rc != 0)
+    {
+        fatal_abort(Fatal_BadResult);
+    }
+
+    // Send the message.
+    static const u32 SendProcessHandleMessage[4] = { 0x00000000, 0x80000000, 0x00000002, CUR_PROCESS_HANDLE };
+    memcpy(armGetTls(), SendProcessHandleMessage, sizeof(SendProcessHandleMessage));
+    svcSendSyncRequest(client_handle);
+
+    // Close the session handle.
+    svcCloseHandle(client_handle);
+
+    // Wait for the thread to be done.
+    rc = svcWaitSynchronizationSingle(thread_handle, UINT64_MAX);
+    if (rc != 0)
+    {
+        fatal_abort(Fatal_BadResult);
+    }
+
+    // Close the thread handle.
+    svcCloseHandle(thread_handle);
+}
+
+static void _map_fs_rw(void) {
+    Result rc;
+
+    do {
+        fs_rw_mapping = (u8 *)(smcGenerateRandomU64() & 0xFFFFFF000ull);
+        rc = svcMapProcessMemory(fs_rw_mapping, self_proc_handle, FS_CODE_BASE, fs_code_size);
+    } while (rc == 0xDC01 || rc == 0xD401);
+
+    if (rc != 0)
+    {
+        fatal_abort(Fatal_BadResult);
+    }
+}
+
+static void _unmap_fs_rw(void) {
+    Result rc = svcUnmapProcessMemory(fs_rw_mapping, self_proc_handle, FS_CODE_BASE, fs_code_size);
+    if (rc != 0)
+    {
+        fatal_abort(Fatal_BadResult);
+    }
+
+    fs_rw_mapping = NULL;
+}
+
+static void _write32(uintptr_t source, u32 value) {
+    *((u32 *)(fs_rw_mapping + (source - FS_CODE_BASE))) = value;
+}
+
 void hook_function(uintptr_t source, uintptr_t target)
 {
     u32 branch_opcode = GENERATE_BRANCH(source, target);
-    smcWriteAddress32((void *)source, branch_opcode);
+    _write32(source, branch_opcode);
 }
 
 void write_nop(uintptr_t source)
 {
-    smcWriteAddress32((void *)source, GENERATE_NOP());
+    _write32(source, GENERATE_NOP());
 }
 
 void write_adrp_add(int reg, uintptr_t pc, uintptr_t add_rel_offset, intptr_t destination)
@@ -167,8 +273,8 @@ void write_adrp_add(int reg, uintptr_t pc, uintptr_t add_rel_offset, intptr_t de
     uint32_t opcode_adrp = GENERATE_ADRP(reg, offset);
     uint32_t opcode_add = GENERATE_ADD(reg, reg, (destination & 0x00000FFF));
 
-    smcWriteAddress32((void *)pc, opcode_adrp);
-    smcWriteAddress32((void *)add_opcode_location, opcode_add);
+    _write32(pc, opcode_adrp);
+    _write32(add_opcode_location, opcode_add);
 }
 
 void setup_hooks(void)
@@ -306,14 +412,21 @@ void __init()
 
     text_base = meminfo.addr;
 
+    // Get code size
+    svcQueryMemory(&meminfo, &pageinfo, FS_CODE_BASE);
+    fs_code_size = meminfo.size;
+
     load_emummc_ctx();
 
     fs_offsets = get_fs_offsets(emuMMC_ctx.fs_ver);
 
+    _init_process_handle();
+    _map_fs_rw();
     setup_hooks();
     populate_function_pointers();
     write_nops();
     setup_nintendo_paths();
+    _unmap_fs_rw();
 
     clock_enable_i2c5();
     i2c_init();

emummc/source/nx/smc.c

@@ -6,6 +6,7 @@
 #include <stddef.h>
 #include <string.h>
 #include "smc.h"
+#include "../utils/fatal.h"
 
 void smcRebootToRcm(void)
 {
@@ -117,45 +118,6 @@ Result smcReadWriteRegister(u32 phys_addr, u32 value, u32 mask)
     return rc;
 }
 
-static Result _smcWriteAddress(void *dst_addr, u64 val, u32 size)
-{
-    SecmonArgs args;
-    args.X[0] = 0xF0000003;     /* smcAmsWriteAddress */
-    args.X[1] = (u64)dst_addr;  /* DRAM address */
-    args.X[2] = val;            /* value */
-    args.X[3] = size;           /* Amount to write */
-    Result rc = svcCallSecureMonitor(&args);
-    if (rc == 0)
-    {
-        if (args.X[0] != 0)
-        {
-            /* SPL result n = SMC result n */
-            rc = (26u | ((u32)args.X[0] << 9u));
-        }
-    }
-    return rc;
-}
-
-Result smcWriteAddress8(void *dst_addr, u8 val)
-{
-    return _smcWriteAddress(dst_addr, val, 1);
-}
-
-Result smcWriteAddress16(void *dst_addr, u16 val)
-{
-    return _smcWriteAddress(dst_addr, val, 2);
-}
-
-Result smcWriteAddress32(void *dst_addr, u32 val)
-{
-    return _smcWriteAddress(dst_addr, val, 4);
-}
-
-Result smcWriteAddress64(void *dst_addr, u64 val)
-{
-    return _smcWriteAddress(dst_addr, val, 8);
-}
-
 Result smcGetEmummcConfig(exo_emummc_mmc_t mmc_id, exo_emummc_config_t *out_cfg, void *out_paths)
 {
     SecmonArgs args;
@@ -178,3 +140,37 @@ Result smcGetEmummcConfig(exo_emummc_mmc_t mmc_id, exo_emummc_config_t *out_cfg,
     return rc;
 
 }
+
+Result smcGenerateRandomBytes(void *dst, u32 size)
+{
+    SecmonArgs args;
+    args.X[0] = 0xC3000006;     /* smcGenerateRandomBytes */
+    args.X[1] = size;
+    Result rc = svcCallSecureMonitor(&args);
+    if (rc == 0)
+    {
+        if (args.X[0] != 0)
+        {
+            /* SPL result n = SMC result n */
+            rc = (26u | ((u32)args.X[0] << 9u));
+        }
+        if (rc == 0)
+        {
+            memcpy(dst, &args.X[1], size);
+        }
+    }
+    return rc;
+}
+
+u64 smcGenerateRandomU64(void)
+{
+    u64 random;
+
+    Result rc = smcGenerateRandomBytes(&random, sizeof(random));
+    if (rc != 0)
+    {
+        fatal_abort(Fatal_BadResult);
+    }
+
+    return random;
+}

emummc/source/nx/smc.h

@@ -78,13 +78,11 @@ Result smcCopyFromIram(void *dst_addr, uintptr_t iram_addr, u32 size);
 
 Result smcReadWriteRegister(u32 phys_addr, u32 value, u32 mask);
 
-Result smcWriteAddress8(void *dst_addr, u8 val);
-Result smcWriteAddress16(void *dst_addr, u16 val);
-Result smcWriteAddress32(void *dst_addr, u32 val);
-Result smcWriteAddress64(void *dst_addr, u64 val);
-
 Result smcGetEmummcConfig(exo_emummc_mmc_t mmc_id, exo_emummc_config_t *out_cfg, void *out_paths);
 
+Result smcGenerateRandomBytes(void *dst, u32 size);
+u64 smcGenerateRandomU64(void);
+
 #ifdef __cplusplus
 }
 #endif

emummc/source/nx/svc.h

@@ -106,6 +106,104 @@ Result svcSetProcessMemoryPermission(Handle proc, u64 addr, u64 size, u32 perm);
  */
 Result svcSetMemoryPermission(void* addr, u64 size, u32 perm);
 
+/**
+ * @brief Creates a thread.
+ * @return Result code.
+ * @note Syscall number 0x08.
+ */
+Result svcCreateThread(Handle* out, void* entry, void* arg, void* stack_top, int prio, int cpuid);
+
+/**
+ * @brief Starts a freshly created thread.
+ * @return Result code.
+ * @note Syscall number 0x09.
+ */
+Result svcStartThread(Handle handle);
+
+/**
+ * @brief Exits the current thread.
+ * @note Syscall number 0x0A.
+ */
+void __attribute__((noreturn)) svcExitThread(void);
+
+/**
+ * @brief Closes a handle, decrementing the reference count of the corresponding kernel object.
+ * This might result in the kernel freeing the object.
+ * @param handle Handle to close.
+ * @return Result code.
+ * @note Syscall number 0x16.
+ */
+Result svcCloseHandle(Handle handle);
+
+/**
+ * @brief Waits on one or more synchronization objects, optionally with a timeout.
+ * @return Result code.
+ * @note Syscall number 0x18.
+ * @note \p handleCount must not be greater than \ref MAX_WAIT_OBJECTS. This is a Horizon kernel limitation.
+ * @note This is the raw syscall, which can be cancelled by \ref svcCancelSynchronization or other means. \ref waitHandles or \ref waitMultiHandle should normally be used instead.
+ */
+Result svcWaitSynchronization(s32* index, const Handle* handles, s32 handleCount, u64 timeout);
+
+/**
+ * @brief Waits on a single synchronization object, optionally with a timeout.
+ * @return Result code.
+ * @note Wrapper for \ref svcWaitSynchronization.
+ * @note This is the raw syscall, which can be cancelled by \ref svcCancelSynchronization or other means. \ref waitSingleHandle should normally be used instead.
+ */
+static inline Result svcWaitSynchronizationSingle(Handle handle, u64 timeout) {
+    s32 tmp;
+    return svcWaitSynchronization(&tmp, &handle, 1, timeout);
+}
+
+/**
+ * @brief Creates an IPC session.
+ * @return Result code.
+ * @note Syscall number 0x40.
+ * @warning This is a privileged syscall. Use \ref envIsSyscallHinted to check if it is available.
+ */
+Result svcCreateSession(Handle *server_handle, Handle *client_handle, u32 unk0, u64 unk1);//unk* are normally 0?
+
+/**
+ * @brief Sends an IPC synchronization request to a session.
+ * @return Result code.
+ * @note Syscall number 0x21.
+ */
+Result svcSendSyncRequest(Handle session);
+
+/**
+ * @brief Performs IPC input/output.
+ * @return Result code.
+ * @note Syscall number 0x43.
+ * @warning This is a privileged syscall. Use \ref envIsSyscallHinted to check if it is available.
+ */
+Result svcReplyAndReceive(s32* index, const Handle* handles, s32 handleCount, Handle replyTarget, u64 timeout);
+
+/**
+ * @brief Maps the src address from the supplied process handle into the current process.
+ * @param[in] dst Address to which map the memory in the current process.
+ * @param[in] proc Process handle.
+ * @param[in] src Source mapping address.
+ * @param[in] size Size of the memory.
+ * @return Result code.
+ * @remark This allows mapping code and rodata with RW- permission.
+ * @note Syscall number 0x74.
+ * @warning This is a privileged syscall. Use \ref envIsSyscallHinted to check if it is available.
+ */
+Result svcMapProcessMemory(void* dst, Handle proc, u64 src, u64 size);
+
+/**
+ * @brief Undoes the effects of \ref svcMapProcessMemory.
+ * @param[in] dst Destination mapping address
+ * @param[in] proc Process handle.
+ * @param[in] src Address of the memory in the process.
+ * @param[in] size Size of the memory.
+ * @return Result code.
+ * @remark This allows mapping code and rodata with RW- permission.
+ * @note Syscall number 0x75.
+ * @warning This is a privileged syscall. Use \ref envIsSyscallHinted to check if it is available.
+ */
+Result svcUnmapProcessMemory(void* dst, Handle proc, u64 src, u64 size);
+
 /**
  * @brief Calls a secure monitor function (TrustZone, EL3).
  * @param regs Arguments to pass to the secure monitor.

emummc/source/nx/svc.s

@@ -56,6 +56,69 @@ SVC_BEGIN svcSetProcessMemoryPermission
 	RET
 SVC_END
 
+SVC_BEGIN svcCreateThread
+	STR X0, [SP, #-16]!
+	SVC 0x8
+	LDR X2, [SP], #16
+	STR W1, [X2]
+	RET
+SVC_END
+
+SVC_BEGIN svcStartThread
+	SVC 0x9
+	RET
+SVC_END
+
+SVC_BEGIN svcExitThread
+	SVC 0xA
+	RET
+SVC_END
+
+SVC_BEGIN svcCloseHandle
+	SVC 0x16
+	RET
+SVC_END
+
+SVC_BEGIN svcWaitSynchronization
+	STR X0, [SP, #-16]!
+	SVC 0x18
+	LDR X2, [SP], #16
+	STR W1, [X2]
+	RET
+SVC_END
+
+SVC_BEGIN svcCreateSession
+	STP X0, X1, [SP, #-16]!
+	SVC 0x40
+	LDP X3, X4, [SP], #16
+	STR W1, [X3]
+	STR W2, [X4]
+	RET
+SVC_END
+
+SVC_BEGIN svcSendSyncRequest
+	SVC 0x21
+	RET
+SVC_END
+
+SVC_BEGIN svcReplyAndReceive
+	STR X0, [SP, #-16]!
+	SVC 0x43
+	LDR X2, [SP], #16
+	STR W1, [X2]
+	RET
+SVC_END
+
+SVC_BEGIN svcMapProcessMemory
+	SVC 0x74
+	RET
+SVC_END
+
+SVC_BEGIN svcUnmapProcessMemory
+	SVC 0x75
+	RET
+SVC_END
+
 SVC_BEGIN svcCallSecureMonitor
 	STR X0, [SP, #-16]!
 	MOV X8, X0

emummc/source/power/max77620.h

@@ -1,7 +1,7 @@
 /*
  * Defining registers address and its bit definitions of MAX77620 and MAX20024
  *
- * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2016 NVIDIA CORPORATION. All rights reserved.
  * Copyright (c) 2019 CTCaer
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -19,9 +19,19 @@
 #define  MAX77620_CNFGGLBL1_LBDAC_EN          (1 << 7)
 #define  MAX77620_CNFGGLBL1_MPPLD             (1 << 6)
 #define  MAX77620_CNFGGLBL1_LBHYST            ((1 << 5) | (1 << 4))
-#define  MAX77620_CNFGGLBL1_LBHYST_N          (1 << 4)
-#define  MAX77620_CNFGGLBL1_LBDAC             0x0E
-#define  MAX77620_CNFGGLBL1_LBDAC_N           (1 << 1)
+#define  MAX77620_CNFGGLBL1_LBHYST_100        (0 << 4)
+#define  MAX77620_CNFGGLBL1_LBHYST_200        (1 << 4)
+#define  MAX77620_CNFGGLBL1_LBHYST_300        (2 << 4)
+#define  MAX77620_CNFGGLBL1_LBHYST_400        (3 << 4)
+#define  MAX77620_CNFGGLBL1_LBDAC_MASK        0x0E
+#define  MAX77620_CNFGGLBL1_LBDAC_2700        (0 << 1)
+#define  MAX77620_CNFGGLBL1_LBDAC_2800        (1 << 1)
+#define  MAX77620_CNFGGLBL1_LBDAC_2900        (2 << 1)
+#define  MAX77620_CNFGGLBL1_LBDAC_3000        (3 << 1)
+#define  MAX77620_CNFGGLBL1_LBDAC_3100        (4 << 1)
+#define  MAX77620_CNFGGLBL1_LBDAC_3200        (5 << 1)
+#define  MAX77620_CNFGGLBL1_LBDAC_3300        (6 << 1)
+#define  MAX77620_CNFGGLBL1_LBDAC_3400        (7 << 1)
 #define  MAX77620_CNFGGLBL1_LBRSTEN           (1 << 0)
 
 #define MAX77620_REG_CNFGGLBL2      0x01
@@ -130,7 +140,7 @@
 #define  MAX77620_POWER_MODE_DISABLE          0
 #define  MAX20024_LDO_CFG2_MPOK_MASK          (1 << 2)
 #define  MAX77620_LDO_CFG2_ADE_MASK           (1 << 1)
-#define  MAX77620_LDO_CFG2_ADE_DISABLE        0
+#define  MAX77620_LDO_CFG2_ADE_DISABLE        (0 << 1)
 #define  MAX77620_LDO_CFG2_ADE_ENABLE         (1 << 1)
 #define  MAX77620_LDO_CFG2_SS_MASK            (1 << 0)
 #define  MAX77620_LDO_CFG2_SS_FAST            (1 << 0)
@@ -153,6 +163,24 @@
 #define MAX77620_REG_PUE_GPIO       0x3E
 #define MAX77620_REG_PDE_GPIO       0x3F
 #define MAX77620_REG_AME_GPIO       0x40
+#define  MAX77620_CNFG_GPIO_DRV_MASK          (1 << 0)
+#define  MAX77620_CNFG_GPIO_DRV_PUSHPULL      (1 << 0)
+#define  MAX77620_CNFG_GPIO_DRV_OPENDRAIN     (0 << 0)
+#define  MAX77620_CNFG_GPIO_DIR_MASK          (1 << 1)
+#define  MAX77620_CNFG_GPIO_DIR_INPUT         (1 << 1)
+#define  MAX77620_CNFG_GPIO_DIR_OUTPUT        (0 << 1)
+#define  MAX77620_CNFG_GPIO_INPUT_VAL_MASK    (1 << 2)
+#define  MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK   (1 << 3)
+#define  MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH   (1 << 3)
+#define  MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW    (0 << 3)
+#define  MAX77620_CNFG_GPIO_INT_MASK          (0x3 << 4)
+#define  MAX77620_CNFG_GPIO_INT_FALLING       (1 << 4)
+#define  MAX77620_CNFG_GPIO_INT_RISING        (1 << 5)
+#define  MAX77620_CNFG_GPIO_DBNC_MASK         (0x3 << 6)
+#define  MAX77620_CNFG_GPIO_DBNC_None         (0x0 << 6)
+#define  MAX77620_CNFG_GPIO_DBNC_8ms          (0x1 << 6)
+#define  MAX77620_CNFG_GPIO_DBNC_16ms         (0x2 << 6)
+#define  MAX77620_CNFG_GPIO_DBNC_32ms         (0x3 << 6)
 
 #define MAX77620_REG_ONOFFCNFG1     0x41
 #define  MAX77620_ONOFFCNFG1_SFT_RST          (1 << 7)
@@ -259,25 +287,6 @@
 #define MAX77620_SD_CFG1_FSRADE_SD_DISABLE    0
 #define MAX77620_SD_CFG1_FSRADE_SD_ENABLE     (1 << 0)
 
-#define MAX77620_CNFG_GPIO_DRV_MASK           (1 << 0)
-#define MAX77620_CNFG_GPIO_DRV_PUSHPULL       (1 << 0)
-#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN      0
-#define MAX77620_CNFG_GPIO_DIR_MASK           (1 << 1)
-#define MAX77620_CNFG_GPIO_DIR_INPUT          (1 << 1)
-#define MAX77620_CNFG_GPIO_DIR_OUTPUT         0
-#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK     (1 << 2)
-#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK    (1 << 3)
-#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH    (1 << 3)
-#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW     0
-#define MAX77620_CNFG_GPIO_INT_MASK           (0x3 << 4)
-#define MAX77620_CNFG_GPIO_INT_FALLING        (1 << 4)
-#define MAX77620_CNFG_GPIO_INT_RISING         (1 << 5)
-#define MAX77620_CNFG_GPIO_DBNC_MASK          (0x3 << 6)
-#define MAX77620_CNFG_GPIO_DBNC_None          (0x0 << 6)
-#define MAX77620_CNFG_GPIO_DBNC_8ms           (0x1 << 6)
-#define MAX77620_CNFG_GPIO_DBNC_16ms          (0x2 << 6)
-#define MAX77620_CNFG_GPIO_DBNC_32ms          (0x3 << 6)
-
 #define MAX77620_IRQ_LVL2_GPIO_EDGE0          (1 << 0)
 #define MAX77620_IRQ_LVL2_GPIO_EDGE1          (1 << 1)
 #define MAX77620_IRQ_LVL2_GPIO_EDGE2          (1 << 2)

emummc/source/power/max7762x.c

@@ -157,9 +157,3 @@ void max77620_config_default()
 	}
 	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD_CFG2, 4);
 }
-
-void max77620_low_battery_monitor_config()
-{
-	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CNFGGLBL1,
-		MAX77620_CNFGGLBL1_LBDAC_EN | MAX77620_CNFGGLBL1_LBHYST_N | MAX77620_CNFGGLBL1_LBDAC_N);
-}

emummc/source/power/max7762x.h

@@ -24,16 +24,16 @@
 * Switch Power domains (max77620):
 * Name  | Usage         | uV step | uV min | uV default | uV max  | Init
 *-------+---------------+---------+--------+------------+---------+------------------
-*  sd0  | core          | 12500   | 600000 |  625000    | 1400000 | 1.125V (pkg1.1)
+*  sd0  | SoC           | 12500   | 600000 |  625000    | 1400000 | 1.125V (pkg1.1)
 *  sd1  | SDRAM         | 12500   | 600000 | 1125000    | 1125000 | 1.1V   (pkg1.1)
 *  sd2  | ldo{0-1, 7-8} | 12500   | 600000 | 1325000    | 1350000 | 1.325V (pcv)
 *  sd3  | 1.8V general  | 12500   | 600000 | 1800000    | 1800000 |
 *  ldo0 | Display Panel | 25000   | 800000 | 1200000    | 1200000 | 1.2V   (pkg1.1)
 *  ldo1 | XUSB, PCIE    | 25000   | 800000 | 1050000    | 1050000 | 1.05V  (pcv)
 *  ldo2 | SDMMC1        | 50000   | 800000 | 1800000    | 3300000 |
-*  ldo3 | GC ASIC       | 50000   | 800000 | 3100000    | 3100000 | 3.1V  (pcv)
+*  ldo3 | GC ASIC       | 50000   | 800000 | 3100000    | 3100000 | 3.1V   (pcv)
 *  ldo4 | RTC           | 12500   | 800000 |  850000    |  850000 |
-*  ldo5 | GC ASIC       | 50000   | 800000 | 1800000    | 1800000 | 1.8V  (pcv)
+*  ldo5 | GC ASIC       | 50000   | 800000 | 1800000    | 1800000 | 1.8V   (pcv)
 *  ldo6 | Touch, ALS    | 50000   | 800000 | 2900000    | 2900000 | 2.9V
 *  ldo7 | XUSB          | 50000   | 800000 | 1050000    | 1050000 |
 *  ldo8 | XUSB, DC      | 50000   | 800000 | 1050000    | 1050000 |
@@ -71,6 +71,8 @@
 /* MAX77621_VOUT */
 #define MAX77621_VOUT_ENABLE  (1 << 7)
 #define MAX77621_VOUT_MASK    0x7F
+#define  MAX77621_VOUT_0_95V  0x37
+#define  MAX77621_VOUT_1_09V  0x4F
 
 /* MAX77621_VOUT_DVC_DVS */
 #define MAX77621_DVS_VOUT_MASK 0x7F
@@ -111,6 +113,5 @@ int max77620_regulator_set_voltage(u32 id, u32 mv);
 int max77620_regulator_enable(u32 id, int enable);
 int max77620_regulator_set_volt_and_flags(u32 id, u32 mv, u8 flags);
 void max77620_config_default();
-void max77620_low_battery_monitor_config();
 
 #endif

emummc/source/soc/clock.c

@@ -23,6 +23,10 @@ static const sclock_t _clock_i2c5 = {
 	CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 0xF, 0, 4 //81.6MHz -> 400KHz
 };
 
+static sclock_t _clock_sdmmc_legacy_tm = {
+	CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM, 1, 4, 66
+};
+
 void clock_enable(const sclock_t *clk)
 {
 	// Put clock into reset.
@@ -34,6 +38,8 @@ void clock_enable(const sclock_t *clk)
 		CLOCK(clk->source) = clk->clk_div | (clk->clk_src << 29);
 	// Enable.
 	CLOCK(clk->enable) = (CLOCK(clk->enable) & ~(1 << clk->index)) | (1 << clk->index);
+	usleep(2);
+
 	// Take clock off reset.
 	CLOCK(clk->reset) &= ~(1 << clk->index);
 }
@@ -56,6 +62,33 @@ void clock_disable_i2c5()
 	clock_disable(&_clock_i2c5);
 }
 
+static void _clock_enable_pllc4()
+{
+	if ((CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) & (PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | 0xFFFFFF))
+		== (PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | (104 << 8) | 4))
+		return;
+
+	// Enable Phase and Frequency lock detection.
+	//CLOCK(CLK_RST_CONTROLLER_PLLC4_MISC) = PLLC4_MISC_EN_LCKDET;
+
+	// Disable PLL and IDDQ in case they are on.
+	CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) &= ~PLLCX_BASE_ENABLE;
+	CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) &= ~PLLC4_BASE_IDDQ;
+	(void)CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE);
+	usleep(10);
+
+	// Set PLLC4 dividers.
+	CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) = (104 << 8) | 4; // DIVM: 4, DIVP: 1.
+
+	// Enable PLLC4 and wait for Phase and Frequency lock.
+	CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) |= PLLCX_BASE_ENABLE;
+	(void)CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE);
+	while (!(CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) & PLLCX_BASE_LOCK))
+		;
+
+	msleep(1); // Wait a bit for PLL to stabilize.
+}
+
 #define L_SWR_SDMMC1_RST (1 << 14)
 #define L_SWR_SDMMC2_RST (1 << 9)
 #define L_SWR_SDMMC4_RST (1 << 15)
@@ -194,57 +227,103 @@ static void _clock_sdmmc_clear_enable(u32 id)
 	}
 }
 
-static u32 _clock_sdmmc_table[8] = { 0 };
+static void _clock_sdmmc_config_legacy_tm()
+{
+	sclock_t *clk = &_clock_sdmmc_legacy_tm;
+	if (!(CLOCK(clk->enable) & (1 << clk->index)))
+		clock_enable(clk);
+}
 
-#define PLLP_OUT0      0x0
+typedef struct _clock_sdmmc_t
+{
+	u32 clock;
+	u32 real_clock;
+} clock_sdmmc_t;
 
-static int _clock_sdmmc_config_clock_source_inner(u32 *pout, u32 id, u32 val)
+static clock_sdmmc_t _clock_sdmmc_table[4] = { 0 };
+
+#define SDMMC_CLOCK_SRC_PLLP_OUT0      0x0
+#define SDMMC_CLOCK_SRC_PLLC4_OUT2     0x3
+#define SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ 0x1
+
+static int _clock_sdmmc_config_clock_host(u32 *pclock, u32 id, u32 val)
 {
 	u32 divisor = 0;
-	u32 source = PLLP_OUT0;
+	u32 source = SDMMC_CLOCK_SRC_PLLP_OUT0;
 
+	if (id > SDMMC_4)
+		return 0;
+
+	// Get IO clock divisor.
 	switch (val)
 	{
 	case 25000:
-		*pout = 24728;
-		divisor = 31;
+		*pclock = 24728;
+		divisor = 31; // 16.5 div.
 		break;
 	case 26000:
-		*pout = 25500;
-		divisor = 30;
+		*pclock = 25500;
+		divisor = 30; // 16 div.
 		break;
 	case 40800:
-		*pout = 40800;
-		divisor = 18;
+		*pclock = 40800;
+		divisor = 18; // 10 div.
 		break;
 	case 50000:
-		*pout = 48000;
-		divisor = 15;
+		*pclock = 48000;
+		divisor = 15; // 8.5 div.
 		break;
 	case 52000:
-		*pout = 51000;
-		divisor = 14;
+		*pclock = 51000;
+		divisor = 14; // 8 div.
 		break;
 	case 100000:
-		*pout = 90667;
-		divisor = 7;
+		source = SDMMC_CLOCK_SRC_PLLC4_OUT2;
+		*pclock = 99840;
+		divisor = 2;  // 2 div.
+		break;
+	case 164000:
+		*pclock = 163200;
+		divisor = 3;  // 2.5 div.
 		break;
 	case 200000:
-		*pout = 163200;
-		divisor = 3;
-		break;
-	case 208000:
-		*pout = 204000;
-		divisor = 2;
+		switch (id)
+		{
+		case SDMMC_1:
+			source = SDMMC_CLOCK_SRC_PLLC4_OUT2;
+			break;
+		case SDMMC_2:
+			source = SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ;
+			break;
+		case SDMMC_3:
+			source = SDMMC_CLOCK_SRC_PLLC4_OUT2;
+			break;
+		case SDMMC_4:
+			source = SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ;
+			break;
+		}
+		*pclock = 199680;
+		divisor = 0;  // 1 div.
 		break;
 	default:
-		*pout = 24728;
-		divisor = 31;
+		*pclock = 24728;
+		divisor = 31; // 16.5 div.
 	}
 
-	_clock_sdmmc_table[2 * id] = val;
-	_clock_sdmmc_table[2 * id + 1] = *pout;
+	_clock_sdmmc_table[id].clock = val;
+	_clock_sdmmc_table[id].real_clock = *pclock;
 
+	// PLLC4 and LEGACY_TM clocks are already initialized,
+	// because we init at the first eMMC read.
+	// // Enable PLLC4 if in use by any SDMMC.
+	// if (source)
+	// 	_clock_enable_pllc4();
+
+	// // Set SDMMC legacy timeout clock.
+	// _clock_sdmmc_config_legacy_tm();
+
+
+	// Set SDMMC clock.
 	switch (id)
 	{
 	case SDMMC_1:
@@ -264,69 +343,75 @@ static int _clock_sdmmc_config_clock_source_inner(u32 *pout, u32 id, u32 val)
 	return 1;
 }
 
-void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val)
+void clock_sdmmc_config_clock_source(u32 *pclock, u32 id, u32 val)
 {
-	if (_clock_sdmmc_table[2 * id] == val)
+	if (_clock_sdmmc_table[id].clock == val)
 	{
-		*pout = _clock_sdmmc_table[2 * id + 1];
+		*pclock = _clock_sdmmc_table[id].real_clock;
 	}
 	else
 	{
 		int is_enabled = _clock_sdmmc_is_enabled(id);
 		if (is_enabled)
 			_clock_sdmmc_clear_enable(id);
-		_clock_sdmmc_config_clock_source_inner(pout, id, val);
+		_clock_sdmmc_config_clock_host(pclock, id, val);
 		if (is_enabled)
 			_clock_sdmmc_set_enable(id);
 		_clock_sdmmc_is_reset(id);
 	}
 }
 
-void clock_sdmmc_get_params(u32 *pout, u16 *pdivisor, u32 type)
+void clock_sdmmc_get_card_clock_div(u32 *pclock, u16 *pdivisor, u32 type)
 {
+	// Get Card clock divisor.
 	switch (type)
 	{
-	case 0:
-		*pout = 26000;
+	case SDHCI_TIMING_MMC_ID: // Actual IO Freq: 380.59 KHz.
+		*pclock = 26000;
 		*pdivisor = 66;
 		break;
-	case 1:
-		*pout = 26000;
+	case SDHCI_TIMING_MMC_LS26:
+		*pclock = 26000;
 		*pdivisor = 1;
 		break;
-	case 2:
-		*pout = 52000;
+	case SDHCI_TIMING_MMC_HS52:
+		*pclock = 52000;
 		*pdivisor = 1;
 		break;
-	case 3:
-	case 4:
-	case 11:
-		*pout = 200000;
+	case SDHCI_TIMING_MMC_HS200:
+	case SDHCI_TIMING_MMC_HS400:
+	case SDHCI_TIMING_UHS_SDR104:
+		*pclock = 200000;
 		*pdivisor = 1;
 		break;
-	case 5:
-		*pout = 25000;
+	case SDHCI_TIMING_SD_ID: // Actual IO Freq: 380.43 KHz.
+		*pclock = 25000;
 		*pdivisor = 64;
 		break;
-	case 6:
-	case 8:
-		*pout = 25000;
+	case SDHCI_TIMING_SD_DS12:
+	case SDHCI_TIMING_UHS_SDR12:
+		*pclock = 25000;
 		*pdivisor = 1;
 		break;
-	case 7:
-		*pout = 50000;
+	case SDHCI_TIMING_SD_HS25:
+	case SDHCI_TIMING_UHS_SDR25:
+		*pclock = 50000;
 		*pdivisor = 1;
 		break;
-	case 10:
-		*pout = 100000;
+	case SDHCI_TIMING_UHS_SDR50:
+		*pclock = 100000;
 		*pdivisor = 1;
 		break;
-	case 13:
-		*pout = 40800;
+	case SDHCI_TIMING_UHS_SDR82:
+		*pclock = 164000;
 		*pdivisor = 1;
 		break;
-	case 14:
-		*pout = 200000;
+	case SDHCI_TIMING_UHS_DDR50:
+		*pclock = 40800;
+		*pdivisor = 1;
+		break;
+	case SDHCI_TIMING_MMC_DDR52: // Actual IO Freq: 49.92 MHz.
+		*pclock = 200000;
 		*pdivisor = 2;
 		break;
 	}
@@ -339,15 +424,15 @@ int clock_sdmmc_is_not_reset_and_enabled(u32 id)
 
 void clock_sdmmc_enable(u32 id, u32 val)
 {
-	u32 div = 0;
+	u32 clock = 0;
 
 	if (_clock_sdmmc_is_enabled(id))
 		_clock_sdmmc_clear_enable(id);
 	_clock_sdmmc_set_reset(id);
-	_clock_sdmmc_config_clock_source_inner(&div, id, val);
+	_clock_sdmmc_config_clock_host(&clock, id, val);
 	_clock_sdmmc_set_enable(id);
 	_clock_sdmmc_is_reset(id);
-	usleep((100000 + div - 1) / div);
+	usleep((100000 + clock - 1) / clock);
 	_clock_sdmmc_clear_reset(id);
 	_clock_sdmmc_is_reset(id);
 }

emummc/source/soc/clock.h

@@ -35,12 +35,16 @@
 #define CLK_RST_CONTROLLER_MISC_CLK_ENB 0x48
 #define CLK_RST_CONTROLLER_OSC_CTRL 0x50
 #define CLK_RST_CONTROLLER_PLLC_BASE 0x80
+#define CLK_RST_CONTROLLER_PLLC_OUT 0x84
 #define CLK_RST_CONTROLLER_PLLC_MISC 0x88
+#define CLK_RST_CONTROLLER_PLLC_MISC_1 0x8C
 #define CLK_RST_CONTROLLER_PLLM_BASE 0x90
 #define CLK_RST_CONTROLLER_PLLM_MISC1 0x98
 #define CLK_RST_CONTROLLER_PLLM_MISC2 0x9C
 #define CLK_RST_CONTROLLER_PLLP_BASE 0xA0
 #define CLK_RST_CONTROLLER_PLLD_BASE 0xD0
+#define CLK_RST_CONTROLLER_PLLD_MISC1 0xD8
+#define CLK_RST_CONTROLLER_PLLD_MISC 0xDC
 #define CLK_RST_CONTROLLER_PLLX_BASE 0xE0
 #define CLK_RST_CONTROLLER_PLLX_MISC 0xE4
 #define CLK_RST_CONTROLLER_PLLE_BASE 0xE8
@@ -50,6 +54,7 @@
 #define CLK_RST_CONTROLLER_CLK_SOURCE_PWM 0x110
 #define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 0x124
 #define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 0x128
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 0x138
 #define CLK_RST_CONTROLLER_CLK_SOURCE_VI 0x148
 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 0x150
 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 0x154
@@ -57,11 +62,13 @@
 #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA 0x178
 #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB 0x17C
 #define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X 0x180
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 0x198
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C
 #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC 0x1A0
 #define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 0x1B8
 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 0x1BC
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD 0x1C0
 #define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE 0x1D4
-#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C
 #define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC 0x1F4
 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_X 0x280
 #define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x284
@@ -95,9 +102,13 @@
 #define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC 0x3A0
 #define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD 0x3A4
 #define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT 0x3B4
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 0x3C4
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SYS 0x400
 #define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410
 #define CLK_RST_CONTROLLER_CLK_SOURCE_SE 0x42C
+#define CLK_RST_CONTROLLER_RST_DEV_V_CLR 0x434
 #define CLK_RST_CONTROLLER_CLK_ENB_V_SET 0x440
+#define CLK_RST_CONTROLLER_CLK_ENB_V_CLR 0x444
 #define CLK_RST_CONTROLLER_CLK_ENB_W_SET 0x448
 #define CLK_RST_CONTROLLER_CLK_ENB_W_CLR 0x44C
 #define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET 0x450
@@ -108,16 +119,32 @@
 #define CLK_RST_CONTROLLER_PLLX_MISC_3 0x518
 #define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE 0x554
 #define CLK_RST_CONTROLLER_SPARE_REG0 0x55C
+#define CLK_RST_CONTROLLER_PLLC4_BASE 0x5A4
+#define CLK_RST_CONTROLLER_PLLC4_MISC 0x5A8
+#define CLK_RST_CONTROLLER_PLLC_MISC_2 0x5D0
+#define CLK_RST_CONTROLLER_PLLC4_OUT 0x5E4
 #define CLK_RST_CONTROLLER_PLLMB_BASE 0x5E8
 #define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP 0x620
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 0x65C
 #define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL 0x664
-#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIP_CAL 0x66C
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL 0x66C
 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM 0x694
 #define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC 0x6A0
 #define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER 0x704
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE 0x710
 
 #define CLK_NO_SOURCE 0x0
 
+/*! PLL control and status bits */
+#define PLLCX_BASE_ENABLE    (1 << 30)
+#define PLLCX_BASE_REF_DIS   (1 << 29)
+#define PLLCX_BASE_LOCK      (1 << 27)
+
+#define PLLC4_MISC_EN_LCKDET (1 << 30)
+#define PLLC4_BASE_IDDQ      (1 << 18)
+#define PLLC4_OUT3_CLKEN     (1 << 1)
+#define PLLC4_OUT3_RSTN_CLR  (1 << 0)
+
 /*! Generic clock descriptor. */
 typedef struct _sclock_t
 {
@@ -136,8 +163,8 @@ void clock_disable(const sclock_t *clk);
 /*! Clock control for specific hardware portions. */
 void clock_enable_i2c5();
 void clock_disable_i2c5();
-void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val);
-void clock_sdmmc_get_params(u32 *pout, u16 *pdivisor, u32 type);
+void clock_sdmmc_config_clock_source(u32 *pclock, u32 id, u32 val);
+void clock_sdmmc_get_card_clock_div(u32 *pclock, u16 *pdivisor, u32 type);
 int  clock_sdmmc_is_not_reset_and_enabled(u32 id);
 void clock_sdmmc_enable(u32 id, u32 val);
 void clock_sdmmc_disable(u32 id);

emummc/source/soc/i2c.c

@@ -49,12 +49,17 @@ static int _i2c_send_pkt(u32 idx, u32 x, u8 *buf, u32 size)
 	vu32 *base = (vu32 *)QueryIoMapping(i2c_addrs[I2C_5], 0x1000);
 	base[I2C_CMD_ADDR0] = x << 1; //Set x (send mode).
 	base[I2C_CMD_DATA1] = tmp;    //Set value.
-	base[I2C_CNFG] = (2 * size - 2) | 0x2800; //Set size and send mode.
-	_i2c_wait(base);  //Kick transaction.
+	base[I2C_CNFG] = ((size - 1) << 1) | 0x2800; //Set size and send mode.
+	_i2c_wait(base);                             //Kick transaction.
 
 	base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFFDFF) | 0x200;
+
+	u32 timeout = get_tmr_ms() + 1500;
 	while (base[I2C_STATUS] & 0x100)
-		;
+	{
+		if (get_tmr_ms() > timeout)
+			return 0;
+	}
 
 	if (base[I2C_STATUS] << 28)
 		return 0;
@@ -68,14 +73,18 @@ static int _i2c_recv_pkt(u32 idx, u8 *buf, u32 size, u32 x)
 		return 0;
 
 	vu32 *base = (vu32 *)QueryIoMapping(i2c_addrs[I2C_5], 0x1000);
-
-	base[I2C_CMD_ADDR0] = (x << 1) | 1; // Set x (recv mode).
-	base[I2C_CNFG] = (size - 1) << 1 | 0x2840; // Set size and recv mode.
-	_i2c_wait(base);        // Kick transaction.
+	base[I2C_CMD_ADDR0] = (x << 1) | 1;          // Set x (recv mode).
+	base[I2C_CNFG] = ((size - 1) << 1) | 0x2840; // Set size and recv mode.
+	_i2c_wait(base);                             // Kick transaction.
 
 	base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFFDFF) | 0x200;
+
+	u32 timeout = get_tmr_ms() + 1500;
 	while (base[I2C_STATUS] & 0x100)
-		;
+	{
+		if (get_tmr_ms() > timeout)
+			return 0;
+	}
 
 	if (base[I2C_STATUS] << 28)
 		return 0;

emummc/source/soc/pmc.h

@@ -25,6 +25,7 @@
 #define APBDEV_PMC_PWRGATE_TOGGLE 0x30
 #define APBDEV_PMC_PWRGATE_STATUS 0x38
 #define APBDEV_PMC_NO_IOPOWER 0x44
+#define  PMC_NO_IOPOWER_SDMMC1_IO_EN (1 << 12)
 #define APBDEV_PMC_SCRATCH0 0x50
 #define APBDEV_PMC_SCRATCH1 0x54
 #define APBDEV_PMC_SCRATCH20 0xA0
@@ -37,6 +38,7 @@
 #define APBDEV_PMC_SCRATCH33 0x120
 #define APBDEV_PMC_SCRATCH40 0x13C
 #define APBDEV_PMC_OSC_EDPD_OVER 0x1A4
+#define  PMC_OSC_EDPD_OVER_OSC_CTRL_OVER 0x400000
 #define APBDEV_PMC_RST_STATUS 0x1B4
 #define APBDEV_PMC_IO_DPD_REQ 0x1B8
 #define APBDEV_PMC_IO_DPD2_REQ 0x1C0
@@ -51,9 +53,11 @@
 #define APBDEV_PMC_REG_SHORT 0x2CC
 #define APBDEV_PMC_SEC_DISABLE3 0x2D8
 #define APBDEV_PMC_SECURE_SCRATCH21 0x334
+#define  PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT 0x10
 #define APBDEV_PMC_SECURE_SCRATCH32 0x360
 #define APBDEV_PMC_SECURE_SCRATCH49 0x3A4
 #define APBDEV_PMC_CNTRL2 0x440
+#define  PMC_CNTRL2_HOLD_CKE_LOW_EN 0x1000
 #define APBDEV_PMC_IO_DPD3_REQ 0x45C
 #define APBDEV_PMC_IO_DPD4_REQ 0x464
 #define APBDEV_PMC_UTMIP_PAD_CFG1 0x4C4

emummc/source/soc/t210.h

@@ -88,7 +88,9 @@ intptr_t QueryIoMapping(u64 addr, u64 size);
 #define APB_MISC_PP_PINMUX_GLOBAL 0x40
 #define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34
 #define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL 0xA98
+#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL 0xA9C
 #define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL 0xAB4
+#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL 0xABC
 #define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64
 #define APB_MISC_GP_WIFI_RST_CFGPADCTRL 0xB68
 

emummc/source/utils/fatal.h

@@ -29,8 +29,12 @@ enum FatalReason
     Fatal_UnknownVersion,
     Fatal_BadResult,
     Fatal_GetConfig,
+    Fatal_OpenAccessor,
     Fatal_CloseAccessor,
     Fatal_IoMapping,
+    Fatal_FatfsMount,
+    Fatal_FatfsFileOpen,
+    Fatal_FatfsMemExhaustion,
     Fatal_Max
 };
 

emummc/source/utils/types.h

@@ -31,30 +31,33 @@
 #define BIT(n) (1U<<(n))
 #endif
 
-typedef signed char s8;
-typedef short s16;
-typedef short SHORT;
-typedef int s32;
-typedef int INT;
-typedef long LONG;
-typedef long long int s64;
-typedef unsigned char u8;
-typedef unsigned char BYTE;
-typedef unsigned short u16;
-typedef unsigned short WORD;
-typedef unsigned short WCHAR;
-typedef unsigned int u32;
-typedef unsigned int UINT;
-typedef unsigned long DWORD;
-typedef unsigned long long QWORD;
-typedef unsigned long long int u64;
-typedef volatile unsigned char vu8;
-typedef volatile unsigned short vu16;
-typedef volatile unsigned int vu32;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int16_t SHORT;
+typedef int32_t s32;
+typedef int32_t INT;
+typedef int64_t LONG;
+typedef int64_t s64;
+typedef uint8_t u8;
+typedef uint8_t BYTE;
+typedef uint16_t u16;
+typedef uint16_t WORD;
+typedef uint16_t WCHAR;
+typedef uint32_t u32;
+typedef uint32_t UINT;
+typedef uint32_t DWORD;
+typedef uint64_t QWORD;
+typedef uint64_t u64;
+typedef volatile uint8_t vu8;
+typedef volatile uint16_t vu16;
+typedef volatile uint32_t vu32;
 
 typedef u32 Handle; ///< Kernel object handle.
 typedef u32 Result; ///< Function error code result type.
 
+#define INVALID_HANDLE ((Handle) 0)
+#define CUR_PROCESS_HANDLE ((Handle) 0xFFFF8001)
+
 #ifndef __cplusplus
 typedef int bool;
 #define true  1

emummc/source/utils/util.c

@@ -96,7 +96,7 @@ u64 get_tmr_us()
 void msleep(u64 milliseconds)
 {
 	u64 now = get_tmr_ms();
-	while (get_tmr_ms() - now < milliseconds)
+	while (((u64)get_tmr_ms() - now) < milliseconds)
 		;
 	//svcSleepThread(1000000 * milliseconds);
 }
@@ -105,7 +105,7 @@ void msleep(u64 milliseconds)
 void usleep(u64 microseconds)
 {
 	u64 now = get_tmr_us();
-	while (get_tmr_us() - now < microseconds)
+	while (((u64)get_tmr_us() - now) < microseconds)
 		;
 	//svcSleepThread(1000 * microseconds);
 }

emummc/source/utils/util.h

@@ -22,8 +22,8 @@
 #include "../emuMMC/emummc_ctx.h"
 
 intptr_t QueryIoMapping(u64 addr, u64 size);
-#define byte_swap_32(num) ((num >> 24) & 0xff) | ((num << 8) & 0xff0000) | \
-						((num >> 8 )& 0xff00) | ((num << 24) & 0xff000000)
+#define byte_swap_32(num) (((num >> 24) & 0xff) | ((num << 8) & 0xff0000) | \
+						((num >> 8 )& 0xff00) | ((num << 24) & 0xff000000))
 
 typedef struct _cfg_op_t
 {
@@ -38,6 +38,12 @@ void usleep(u64 ticks);
 void msleep(u64 milliseconds);
 void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops);
 
+static inline void *armGetTls(void) {
+    void *ret;
+    __asm__ __volatile__("MRS %x[data], TPIDRRO_EL0" : [data]"=r"(ret));
+    return ret;
+}
+
 extern volatile emuMMC_ctx_t emuMMC_ctx;
 
 #endif

exosphere/Makefile

@@ -1,178 +1,47 @@
-#---------------------------------------------------------------------------------
-.SUFFIXES:
-#---------------------------------------------------------------------------------
+TARGETS := exosphere.bin warmboot.bin program.lz4
+CLEAN_TARGETS := exosphere-clean program-clean boot_code-clean warmboot-clean
 
-ifeq ($(strip $(DEVKITPRO)),)
-$(error "Please set DEVKITPRO in your environment. export DEVKITPRO=<path to>/devkitpro")
-endif
+SUBFOLDERS := $(MODULES)
 
-TOPDIR ?= $(CURDIR)
-include $(DEVKITPRO)/devkitA64/base_rules
+all: exosphere.bin warmboot.bin
 
-AMSBRANCH := $(shell git symbolic-ref --short HEAD)
-AMSHASH = $(shell git rev-parse --short=16 HEAD)
-AMSREV := $(AMSBRANCH)-$(shell git rev-parse --short HEAD)
+clean: $(CLEAN_TARGETS)
+	@rm -f exosphere.bin
 
-ifneq (, $(strip $(shell git status --porcelain 2>/dev/null)))
-    AMSREV := $(AMSREV)-dirty
-endif
+exosphere.bin: program.lz4 boot_code.lz4
+	$(MAKE) -C loader_stub
+	@cp loader_stub/loader_stub.bin exosphere.bin
+	@printf LENY >> exosphere.bin
+	@echo "Built exosphere.bin..."
 
-#---------------------------------------------------------------------------------
-# TARGET is the name of the output
-# BUILD is the directory where object files & intermediate files will be placed
-# SOURCES is a list of directories containing source code
-# DATA is a list of directories containing data files
-# INCLUDES is a list of directories containing header files
-#---------------------------------------------------------------------------------
-TARGET		:=	$(notdir $(CURDIR))
-BUILD		:=	build
-SOURCES		:=	src src/dbg
-DATA		:=	data
-INCLUDES	:=	include ../libraries/libvapours/include
+program.lz4: build_program
+	@cp program/program.lz4 program.lz4
+	@cp program/boot_code.lz4 boot_code.lz4
 
-#---------------------------------------------------------------------------------
-# options for code generation
-#---------------------------------------------------------------------------------
-ARCH	:=	-march=armv8-a -mtune=cortex-a57 -mgeneral-regs-only #<- important
-DEFINES	:=	-D__CCPLEX__ -DATMOSPHERE_GIT_BRANCH=\"$(AMSBRANCH)\" -DATMOSPHERE_GIT_REV=\"$(AMSREV)\" -DATMOSPHERE_RELEASE_VERSION_HASH="0x$(AMSHASH)"
-CFLAGS	:= \
-	-g \
-	-Os \
-	-ffunction-sections \
-	-fdata-sections \
-	-fomit-frame-pointer \
-    -fno-asynchronous-unwind-tables \
-    -fno-unwind-tables \
-	-std=gnu11 \
-	-Werror \
-	-Wall \
-	$(ARCH) $(DEFINES)
+build_program:
+	$(MAKE) -C program
 
-CFLAGS	+=	$(INCLUDE)
+warmboot.bin: build_warmboot
+	@cp warmboot/warmboot.bin warmboot.bin
 
-CXXFLAGS	:= $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11
+build_warmboot:
+	$(MAKE) -C warmboot
 
-ASFLAGS	:=	-g $(ARCH)
-LDFLAGS	=	-specs=$(TOPDIR)/linker.specs -nostartfiles -nostdlib -g $(ARCH) -Wl,-Map,$(notdir $*.map)
+boot_code.lz4: program.lz4
 
-LIBS	:=
+exosphere-clean:
+	$(MAKE) -C loader_stub clean
+	@rm -f exosphere.bin
 
-#---------------------------------------------------------------------------------
-# list of directories containing libraries, this must be the top level containing
-# include and lib
-#---------------------------------------------------------------------------------
-LIBDIRS	:=
+program-clean:
+	$(MAKE) -C program clean
+	@rm -f program.lz4
 
+warmboot-clean:
+	$(MAKE) -C warmboot clean
+	@rm -f warmboot.bin
 
-#---------------------------------------------------------------------------------
-# no real need to edit anything past this point unless you need to add additional
-# rules for different file extensions
-#---------------------------------------------------------------------------------
-ifneq ($(BUILD),$(notdir $(CURDIR)))
-#---------------------------------------------------------------------------------
+boot_code-clean:
+	@rm -f boot_code.lz4
 
-export OUTPUT	:=	$(CURDIR)/$(TARGET)
-export TOPDIR	:=	$(CURDIR)
-
-export VPATH	:=	$(foreach dir,$(SOURCES),$(CURDIR)/$(dir)) \
-			$(foreach dir,$(DATA),$(CURDIR)/$(dir)) \
-			$(TOPDIR)/lp0fw \
-			$(TOPDIR)/sc7fw \
-			$(TOPDIR)/rebootstub
-
-export DEPSDIR	:=	$(CURDIR)/$(BUILD)
-
-CFILES		:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.c)))
-CPPFILES	:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.cpp)))
-SFILES		:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.s)))
-BINFILES	:=	$(foreach dir,$(DATA),$(notdir $(wildcard $(dir)/*.*))) sc7fw.bin lp0fw.bin rebootstub.bin
-
-#---------------------------------------------------------------------------------
-# use CXX for linking C++ projects, CC for standard C
-#---------------------------------------------------------------------------------
-ifeq ($(strip $(CPPFILES)),)
-#---------------------------------------------------------------------------------
-	export LD	:=	$(CC)
-#---------------------------------------------------------------------------------
-else
-#---------------------------------------------------------------------------------
-	export LD	:=	$(CXX)
-#---------------------------------------------------------------------------------
-endif
-#---------------------------------------------------------------------------------
-
-export OFILES_BIN	:=	$(addsuffix .o,$(BINFILES))
-export OFILES_SRC	:=	$(CPPFILES:.cpp=.o) $(CFILES:.c=.o) $(SFILES:.s=.o)
-export OFILES 		:=	$(OFILES_BIN) $(OFILES_SRC)
-export HFILES_BIN	:=	$(addsuffix .h,$(subst .,_,$(BINFILES)))
-
-export INCLUDE	:=	$(foreach dir,$(INCLUDES),-I$(CURDIR)/$(dir)) \
-			$(foreach dir,$(LIBDIRS),-I$(dir)/include) \
-			-I$(CURDIR)/$(BUILD)
-
-export LIBPATHS	:=	$(foreach dir,$(LIBDIRS),-L$(dir)/lib)
-
-.PHONY: $(BUILD) build_sc7fw build_lp0fw build_rebootstub clean all
-
-#---------------------------------------------------------------------------------
-all: $(BUILD)
-
-check_sc7fw:
-	@$(MAKE) -C sc7fw all
-
-check_lp0fw:
-	@$(MAKE) -C lp0fw all
-
-check_rebootstub:
-	@$(MAKE) -C rebootstub all
-
-$(BUILD): check_sc7fw check_lp0fw check_rebootstub
-	@[ -d $@ ] || mkdir -p $@
-	@$(MAKE) --no-print-directory -C $(BUILD) -f $(CURDIR)/Makefile
-
-#---------------------------------------------------------------------------------
-clean:
-	@echo clean ...
-	@$(MAKE) -C $(TOPDIR)/sc7fw clean
-	@$(MAKE) -C $(TOPDIR)/lp0fw clean
-	@$(MAKE) -C $(TOPDIR)/rebootstub clean
-	@rm -fr $(BUILD) $(TARGET).bin $(TARGET).elf
-
-
-#---------------------------------------------------------------------------------
-else
-.PHONY:	all
-
-DEPENDS	:=	$(OFILES:.o=.d)
-
-#---------------------------------------------------------------------------------
-# main targets
-#---------------------------------------------------------------------------------
-all	:	$(OUTPUT).bin
-
-$(OUTPUT).bin	:	$(OUTPUT).elf
-	$(OBJCOPY) -S -O binary $< $@
-	@echo built ... $(notdir $@)
-
-$(OUTPUT).elf	:	$(OFILES)
-
-%.elf:
-	@echo linking $(notdir $@)
-	$(LD) $(LDFLAGS) $(OFILES) $(LIBPATHS) $(LIBS) -o $@
-	@$(NM) -CSn $@ > $(notdir $*.lst)
-
-$(OFILES_SRC)	: $(HFILES_BIN)
-
-#---------------------------------------------------------------------------------
-# you need a rule like this for each extension you use as binary data
-#---------------------------------------------------------------------------------
-%.bin.o	%_bin.h:	%.bin
-#---------------------------------------------------------------------------------
-	@echo $(notdir $<)
-	@$(bin2o)
-
--include $(DEPENDS)
-
-#---------------------------------------------------------------------------------------
-endif
-#---------------------------------------------------------------------------------------
+.PHONY: all clean build_program $(CLEAN_TARGETS)

exosphere/README.md

@@ -1,6 +0,0 @@
-Exosphère
-=====
-
-![License](https://img.shields.io/badge/License-GPLv2-blue.svg)
-
-Exosphère is a Secure Monitor implementation for the Nintendo Switch.

exosphere/linker.ld

@@ -1,269 +0,0 @@
-OUTPUT_ARCH(aarch64)
-ENTRY(__start_cold)
-
-MEMORY
-{
-    NULL  : ORIGIN = 0,           LENGTH = 4K
-    ccrt0 : ORIGIN = 0x040006000, LENGTH = 4K
-    glob  : ORIGIN = 0x040020000, LENGTH = 128K
-    tzram : ORIGIN = 0x07C010000, LENGTH = 64K
-    /*
-        The warmboot crt0 is preceeded by the exception vector page and the L2 and L3 translation tables.
-        Normally the main code immediately follows the warmboot crt0, aligned to 256 bytes.
-        We can't ensure or replicate that behavior properly so we'll just give 2K to the warmboot crt0.
-    */
-    warmboot_crt0 : ORIGIN = ORIGIN(tzram) + 12K, LENGTH = 2K
-
-    /* 8K are the MMU L2 and L3 tables & 2K from the evt page */
-    main    : ORIGIN = 0x1F01E0000                          + LENGTH(warmboot_crt0),    LENGTH = LENGTH(tzram) - LENGTH(pk2ldr) - LENGTH(evt) - LENGTH(warmboot_crt0) - 10K
-    pk2ldr  : ORIGIN = ORIGIN(main) - LENGTH(warmboot_crt0) + LENGTH(tzram),            LENGTH = 8K
-    /* The first half of the page are exception entry stacks, the other half are the vectors themselves */
-    evt     : ORIGIN = ORIGIN(pk2ldr)                       + 40K + 2K,                 LENGTH = 2K
-}
-
-SECTIONS
-{
-    PROVIDE(__start__ = 0x040006000);
-    . = __start__;
-
-    .cold_crt0 :
-    {
-        . = ALIGN(64);
-        __cold_crt0_start__ = ABSOLUTE(.);
-        __glob_origin__ = ORIGIN(glob);
-        KEEP (*(.cold_crt0.text.start)) /* MUST be first */
-        KEEP (*(.cold_crt0.text*))
-        KEEP (coldboot_init.o(.text*))
-        *(.cold_crt0.rodata*)
-        coldboot_init.o(.rodata*)
-        *(.cold_crt0.data*)
-        coldboot_init.o(.data*)
-        . = ALIGN(8);
-        *(.cold_crt0.bss*)
-        coldboot_init.o(.bss* COMMON)
-        . = ALIGN(64);
-        __cold_crt0_end__ = ABSOLUTE(.);
-    } >ccrt0 AT>glob
-
-    .pk2ldr :
-    {
-        . = ALIGN(4096);
-        __pk2ldr_lma__   = LOADADDR(.pk2ldr);
-        __pk2ldr_start__ = ABSOLUTE(.);
-        KEEP (package2.o(.text*))
-        package2.o(.rodata*)
-        package2.o(.data*)
-        . = ALIGN(8);
-    } >pk2ldr AT>glob
-
-    .pk2ldr.bss :
-    {
-        . = ALIGN(8);
-        __pk2ldr_bss_start__ = ABSOLUTE(.);
-        package2.o(.bss* COMMON)
-        . = ALIGN(8);
-        __pk2ldr_end__ = ABSOLUTE(.);
-    } >pk2ldr AT>glob
-
-    .vectors :
-    {
-        . = ALIGN(2048);
-        __vectors_lma__   = LOADADDR(.vectors);
-        __vectors_start__ = ABSOLUTE(.);
-        KEEP (*(.vectors*))
-        . = ALIGN(8);
-        __vectors_end__ = ABSOLUTE(.);
-    } >evt AT>glob
-
-    .warm_crt0 :
-    {
-        . = ALIGN(64);
-        __warmboot_crt0_lma__   = LOADADDR(.warm_crt0);
-        __warmboot_crt0_start__ = ABSOLUTE(.);
-        KEEP (*(.warm_crt0.text.start)) /* Should be first */
-        KEEP (*(.warm_crt0.text*))
-        KEEP (warmboot_init.o(.text*))
-        *(.warm_crt0.rodata*)
-        warmboot_init.o(.rodata*)
-        *(.warm_crt0.data*)
-        warmboot_init.o(.data*)
-        . = ALIGN(8);
-        *(.warm_crt0.bss*)
-        warmboot_init.o(.bss*)
-        . = ALIGN(64);
-        __warmboot_crt0_end__ = ABSOLUTE(.);
-    } >warmboot_crt0 AT>glob
-
-    .text :
-    {
-        . = ALIGN(256);
-        __main_lma__    = LOADADDR(.text);
-        __main_start__  = ABSOLUTE(.);
-        *(.text.unlikely .text.*_unlikely .text.unlikely.*)
-        *(.text.exit .text.exit.*)
-        *(.text.startup .text.startup.*)
-        *(.text.hot .text.hot.*)
-        *(.text .stub .text.* .gnu.linkonce.t.*)
-        . = ALIGN(8);
-    } >main AT>glob
-
-    .init :
-    {
-        KEEP( *(.init) )
-        . = ALIGN(8);
-    } >main AT>glob
-
-    .plt :
-    {
-        *(.plt)
-        *(.iplt)
-        . = ALIGN(8);
-    } >main AT>glob
-
-
-    .fini :
-    {
-        KEEP( *(.fini) )
-        . = ALIGN(8);
-    } >main AT>glob
-
-    .rodata :
-    {
-        *(.rodata .rodata.* .gnu.linkonce.r.*)
-        SORT(CONSTRUCTORS)
-        . = ALIGN(8);
-    } >main AT>glob
-
-    .got            : { __got_start__ = ABSOLUTE(.); *(.got) *(.igot) } >main AT>glob
-    .got.plt        : { *(.got.plt)  *(.igot.plt)  __got_end__ = ABSOLUTE(.);} >main AT>glob
-
-    .preinit_array :
-    {
-        . = ALIGN(8);
-        PROVIDE (__preinit_array_start = .);
-        KEEP (*(.preinit_array))
-        PROVIDE (__preinit_array_end = .);
-        . = ALIGN(8);
-    } >main AT>glob
-
-    .init_array :
-    {
-        PROVIDE (__init_array_start = .);
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        PROVIDE (__init_array_end = .);
-    } >main AT>glob
-
-    .fini_array :
-    {
-        . = ALIGN(8);
-        PROVIDE (__fini_array_start = .);
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        PROVIDE (__fini_array_end = .);
-        . = ALIGN(8);
-    } >main AT>glob
-
-    .ctors :
-    {
-        . = ALIGN(8);
-        KEEP (*crtbegin.o(.ctors)) /* MUST be first -- GCC requires it */
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*(.ctors))
-        . = ALIGN(8);
-    } >main AT>glob
-
-    .dtors ALIGN(8) :
-    {
-        . = ALIGN(8);
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*(.dtors))
-        . = ALIGN(8);
-    } >main AT>glob
-
-    .data ALIGN(8) :
-    {
-        *(.data .data.* .gnu.linkonce.d.*)
-        CONSTRUCTORS
-        . = ALIGN(8);
-    } >main AT>glob
-
-
-    .eh_frame_hdr     : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } >main AT>glob
-    .eh_frame         : { KEEP (*(.eh_frame)) *(.eh_frame.*) } >main AT>glob
-    .gcc_except_table : { *(.gcc_except_table .gcc_except_table.*) } >main AT>glob
-    .gnu_extab        : { *(.gnu_extab*) } >main AT>glob
-    .exception_ranges : { *(.exception_ranges .exception_ranges*) } >main AT>glob
-
-    .dynamic           : { *(.dynamic) } >main AT>glob
-    .interp            : { *(.interp) } >main AT>glob
-    .note.gnu.build-id : { *(.note.gnu.build-id) } >main AT>glob
-    .hash              : { *(.hash) } >main AT>glob
-    .gnu.hash          : { *(.gnu.hash) } >main AT>glob
-    .gnu.version       : { *(.gnu.version) } >main AT>glob
-    .gnu.version_d     : { *(.gnu.version_d) } >main AT>glob
-    .gnu.version_r     : { *(.gnu.version_r) } >main AT>glob
-    .dynsym            : { *(.dynsym) } >main AT>glob
-    .dynstr            : { *(.dynstr) } >main AT>glob
-    .rela.dyn          : { *(.rela.*); __main_end__ = ABSOLUTE(.);} >main AT>glob
-
-    .bss :
-    {
-        . = ALIGN(8);
-        __main_bss_start__  = ABSOLUTE(.);
-        __loaded_end_lma__  = LOADADDR(.bss);
-        *(.dynbss)
-        *(.bss .bss.* .gnu.linkonce.b.*)
-        *(COMMON)
-        . = ALIGN(8);
-        __main_end__ = ABSOLUTE(.);
-    } >main AT>glob
-
-    __end__ = ABSOLUTE(.) ;
-
-    . = ALIGN(0x1000);
-    __argdata__ = ABSOLUTE(.) ;
-
-    /* ==================
-       ==== Metadata ====
-       ================== */
-
-    /* Discard sections that difficult post-processing */
-    /DISCARD/ : { *(.group .comment .note) }
-
-    /* Stabs debugging sections. */
-    .stab          0 : { *(.stab) }
-    .stabstr       0 : { *(.stabstr) }
-    .stab.excl     0 : { *(.stab.excl) }
-    .stab.exclstr  0 : { *(.stab.exclstr) }
-    .stab.index    0 : { *(.stab.index) }
-    .stab.indexstr 0 : { *(.stab.indexstr) }
-
-    /* DWARF debug sections.
-       Symbols in the DWARF debugging sections are relative to the beginning
-       of the section so we begin them at 0. */
-
-    /* DWARF 1 */
-    .debug          0 : { *(.debug) }
-    .line           0 : { *(.line) }
-
-    /* GNU DWARF 1 extensions */
-    .debug_srcinfo  0 : { *(.debug_srcinfo) }
-    .debug_sfnames  0 : { *(.debug_sfnames) }
-
-    /* DWARF 1.1 and DWARF 2 */
-    .debug_aranges  0 : { *(.debug_aranges) }
-    .debug_pubnames 0 : { *(.debug_pubnames) }
-
-    /* DWARF 2 */
-    .debug_info     0 : { *(.debug_info) }
-    .debug_abbrev   0 : { *(.debug_abbrev) }
-    .debug_line     0 : { *(.debug_line) }
-    .debug_frame    0 : { *(.debug_frame) }
-    .debug_str      0 : { *(.debug_str) }
-    .debug_loc      0 : { *(.debug_loc) }
-    .debug_macinfo  0 : { *(.debug_macinfo) }
-}

exosphere/linker.specs

@@ -1,4 +0,0 @@
-%rename link                old_link
-
-*link:
-%(old_link) -T %:getenv(TOPDIR /linker.ld) --nmagic --gc-sections

exosphere/loader_stub/Makefile

@@ -1,59 +1,13 @@
 #---------------------------------------------------------------------------------
-.SUFFIXES:
+# Define the atmosphere board and cpu
 #---------------------------------------------------------------------------------
-
-ifeq ($(strip $(DEVKITARM)),)
-$(error "Please set DEVKITARM in your environment. export DEVKITARM=<path to>devkitARM")
-endif
-
-TOPDIR ?= $(CURDIR)
-include $(DEVKITARM)/base_rules
+export ATMOSPHERE_BOARD := nx-hac-001
+export ATMOSPHERE_CPU   := arm-cortex-a57
 
 #---------------------------------------------------------------------------------
-# TARGET is the name of the output
-# BUILD is the directory where object files & intermediate files will be placed
-# SOURCES is a list of directories containing source code
-# DATA is a list of directories containing data files
-# INCLUDES is a list of directories containing header files
+# pull in common atmosphere configuration
 #---------------------------------------------------------------------------------
-TARGET		:=	$(notdir $(CURDIR))
-BUILD		:=	build
-SOURCES		:=	src
-DATA		:=	data
-INCLUDES	:=	include
-
-#---------------------------------------------------------------------------------
-# options for code generation
-#---------------------------------------------------------------------------------
-ARCH	:=	-march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork
-
-CFLAGS	:= \
-		-g \
-		-Os \
-		-ffunction-sections \
-		-fdata-sections \
-		-fomit-frame-pointer \
-		-fno-inline \
-		-std=gnu11 \
-		-Werror \
-		-Wall \
-		$(ARCH) $(DEFINES)
-
-CFLAGS	+=	$(INCLUDE) -D__BPMP__
-
-CXXFLAGS	:= $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11
-
-ASFLAGS	:=	-g $(ARCH)
-LDFLAGS	=	-specs=$(TOPDIR)/linker.specs -g $(ARCH) -Wl,-Map,$(notdir $*.map)
-
-LIBS	:=
-
-#---------------------------------------------------------------------------------
-# list of directories containing libraries, this must be the top level containing
-# include and lib
-#---------------------------------------------------------------------------------
-LIBDIRS	:=
-
+include  $(dir $(abspath $(lastword $(MAKEFILE_LIST))))/../../libraries/config/templates/exosphere.mk
 
 #---------------------------------------------------------------------------------
 # no real need to edit anything past this point unless you need to add additional
@@ -64,16 +18,17 @@ ifneq ($(BUILD),$(notdir $(CURDIR)))
 
 export OUTPUT	:=	$(CURDIR)/$(TARGET)
 export TOPDIR	:=	$(CURDIR)
+export DEPSDIR  :=  $(CURDIR)/$(BUILD)
 
 export VPATH	:=	$(foreach dir,$(SOURCES),$(CURDIR)/$(dir)) \
-			$(foreach dir,$(DATA),$(CURDIR)/$(dir))
+			$(foreach dir,$(DATA),$(CURDIR)/$(dir)) \
+            $(TOPDIR)/../program
 
-export DEPSDIR	:=	$(CURDIR)/$(BUILD)
+CFILES      :=	$(call FIND_SOURCE_FILES,$(SOURCES),c)
+CPPFILES    :=	$(call FIND_SOURCE_FILES,$(SOURCES),cpp)
+SFILES      :=	$(call FIND_SOURCE_FILES,$(SOURCES),s)
 
-CFILES		:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.c)))
-CPPFILES	:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.cpp)))
-SFILES		:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.s)))
-BINFILES	:=	$(foreach dir,$(DATA),$(notdir $(wildcard $(dir)/*.*)))
+BINFILES    := program.lz4 boot_code.lz4
 
 #---------------------------------------------------------------------------------
 # use CXX for linking C++ projects, CC for standard C
@@ -91,29 +46,31 @@ endif
 
 export OFILES_BIN	:=	$(addsuffix .o,$(BINFILES))
 export OFILES_SRC	:=	$(CPPFILES:.cpp=.o) $(CFILES:.c=.o) $(SFILES:.s=.o)
-export OFILES 		:=	$(OFILES_BIN) $(OFILES_SRC)
-export HFILES_BIN	:=	$(addsuffix .h,$(subst .,_,$(BINFILES)))
+export OFILES 	:=	$(OFILES_BIN) $(OFILES_SRC)
+export HFILES_BIN	:=	$(addsuffix .h,$(subst .,_,$(subst -,_,$(BINFILES))))
 
 export INCLUDE	:=	$(foreach dir,$(INCLUDES),-I$(CURDIR)/$(dir)) \
 			$(foreach dir,$(LIBDIRS),-I$(dir)/include) \
-			-I$(CURDIR)/$(BUILD)
+			-I.
 
-export LIBPATHS	:=	$(foreach dir,$(LIBDIRS),-L$(dir)/lib)
+export LIBPATHS	:=	$(foreach dir,$(LIBDIRS),-L$(dir)/lib -L$(dir)/$(ATMOSPHERE_LIBRARY_DIR))
 
-.PHONY: $(BUILD) clean all
+.PHONY: $(BUILD) clean all check_program
 
 #---------------------------------------------------------------------------------
-all: $(BUILD)
+all: $(BUILD) check_program
 
-$(BUILD):
+$(BUILD): check_program
 	@[ -d $@ ] || mkdir -p $@
 	@$(MAKE) --no-print-directory -C $(BUILD) -f $(CURDIR)/Makefile
 
+check_program:
+	@$(MAKE) -C ../program all
+
 #---------------------------------------------------------------------------------
 clean:
 	@echo clean ...
-	@rm -fr $(BUILD) $(TARGET).bin $(TARGET).elf
-
+	@rm -fr $(BUILD) $(OUTPUT).bin $(OUTPUT).elf
 
 #---------------------------------------------------------------------------------
 else
@@ -127,14 +84,14 @@ DEPENDS	:=	$(OFILES:.o=.d)
 all	:	$(OUTPUT).bin
 
 $(OUTPUT).bin	:	$(OUTPUT).elf
-	$(OBJCOPY) -S -O binary $< $@
+	$(OBJCOPY) -S -O binary --set-section-flags .bss=alloc,load,contents $< $@
 	@echo built ... $(notdir $@)
 
-$(OUTPUT).elf	:	$(OFILES)
+$(OUTPUT).elf	:	$(OFILES) ../../../libraries/libexosphere/$(ATMOSPHERE_LIBRARY_DIR)/libexosphere.a
 
-%.elf: $(OFILES)
+%.elf:
 	@echo linking $(notdir $@)
-	@$(LD) $(LDFLAGS) $(OFILES) $(LIBPATHS) $(LIBS) -o $@
+	$(LD) $(LDFLAGS) $(OFILES) $(LIBPATHS) $(LIBS) -o $@
 	@$(NM) -CSn $@ > $(notdir $*.lst)
 
 $(OFILES_SRC)	: $(HFILES_BIN)
@@ -142,7 +99,12 @@ $(OFILES_SRC)	: $(HFILES_BIN)
 #---------------------------------------------------------------------------------
 # you need a rule like this for each extension you use as binary data
 #---------------------------------------------------------------------------------
-%.bin.o	:	%.bin
+%.bin.o	%_bin.h:	%.bin
+#---------------------------------------------------------------------------------
+	@echo $(notdir $<)
+	@$(bin2o)
+
+%.lz4.o	%_lz4.h:	%.lz4
 #---------------------------------------------------------------------------------
 	@echo $(notdir $<)
 	@$(bin2o)

exosphere/loader_stub/loader_stub.ld

@@ -0,0 +1,182 @@
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+
+MEMORY
+{
+    NULL      : ORIGIN = 0,           LENGTH = 4K
+    ldr_stub  : ORIGIN = 0x040030000, LENGTH = 128K
+}
+
+SECTIONS
+{
+	/* =========== CODE section =========== */
+	PROVIDE(__start__ = 0x040030000);
+	. = __start__;
+	__code_start = . ;
+
+	.crt0 :
+	{
+		KEEP (*(.crt0 .crt0.*))
+		. = ALIGN(8);
+	} >ldr_stub
+
+	.text :
+	{
+		*(.text.unlikely .text.*_unlikely .text.unlikely.*)
+		*(.text.exit .text.exit.*)
+		*(.text.startup .text.startup.*)
+		*(.text.hot .text.hot.*)
+		*(.text .stub .text.* .gnu.linkonce.t.*)
+		. = ALIGN(8);
+	} >ldr_stub
+
+	.init :
+	{
+		KEEP( *(.init) )
+		. = ALIGN(8);
+	} >ldr_stub
+
+	.plt :
+	{
+		*(.plt)
+		*(.iplt)
+		. = ALIGN(8);
+	} >ldr_stub
+
+	.fini :
+	{
+		KEEP( *(.fini) )
+		. = ALIGN(8);
+	} >ldr_stub
+
+
+	/* =========== RODATA section =========== */
+	. = ALIGN(8);
+	__rodata_start = . ;
+
+	.rodata :
+	{
+		*(.rodata .rodata.* .gnu.linkonce.r.*)
+		. = ALIGN(8);
+	} >ldr_stub
+
+	.eh_frame_hdr     : { __eh_frame_hdr_start = .; *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) __eh_frame_hdr_end = .; } >ldr_stub
+	.eh_frame         : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } >ldr_stub
+	.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } >ldr_stub
+	.gnu_extab        : ONLY_IF_RO { *(.gnu_extab*) } >ldr_stub
+
+	.hash              : { *(.hash) } >ldr_stub
+
+	/* =========== DATA section =========== */
+	. = ALIGN(8);
+	__data_start = . ;
+
+	.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) } >ldr_stub
+	.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } >ldr_stub
+	.gnu_extab : ONLY_IF_RW { *(.gnu_extab*) } >ldr_stub
+	.exception_ranges : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) } >ldr_stub
+
+	.preinit_array ALIGN(8) :
+	{
+		PROVIDE (__preinit_array_start = .);
+		KEEP (*(.preinit_array))
+		PROVIDE (__preinit_array_end = .);
+	} >ldr_stub
+
+	.init_array ALIGN(8) :
+	{
+		PROVIDE (__init_array_start = .);
+		KEEP (*(SORT(.init_array.*)))
+		KEEP (*(.init_array))
+		PROVIDE (__init_array_end = .);
+	} >ldr_stub
+
+	.fini_array ALIGN(8) :
+	{
+		PROVIDE (__fini_array_start = .);
+		KEEP (*(.fini_array))
+		KEEP (*(SORT(.fini_array.*)))
+		PROVIDE (__fini_array_end = .);
+	} >ldr_stub
+
+	.ctors ALIGN(8) :
+	{
+		KEEP (*crtbegin.o(.ctors)) /* MUST be first -- GCC requires it */
+		KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+		KEEP (*(SORT(.ctors.*)))
+		KEEP (*(.ctors))
+	} >ldr_stub
+
+	.dtors ALIGN(8) :
+	{
+		KEEP (*crtbegin.o(.dtors))
+		KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+		KEEP (*(SORT(.dtors.*)))
+		KEEP (*(.dtors))
+	} >ldr_stub
+
+	__got_start__ = .;
+
+	.got            : { *(.got) *(.igot) } >ldr_stub
+	.got.plt        : { *(.got.plt)  *(.igot.plt) } >ldr_stub
+
+	__got_end__ = .;
+
+	.data ALIGN(8) :
+	{
+		*(.data .data.* .gnu.linkonce.d.*)
+		SORT(CONSTRUCTORS)
+	} >ldr_stub
+
+	__bss_start__ = .;
+	.bss ALIGN(8) :
+	{
+		*(.dynbss)
+		*(.bss .bss.* .gnu.linkonce.b.*)
+		*(COMMON)
+		. = ALIGN(16);
+	} >ldr_stub
+	__bss_end__ = .;
+
+	__end__ = ABSOLUTE(.) ;
+
+	/* ==================
+	   ==== Metadata ====
+	   ================== */
+
+	/* Discard sections that difficult post-processing */
+	/DISCARD/ : { *(.group .comment .note .interp) }
+
+	/* Stabs debugging sections. */
+	.stab          0 : { *(.stab) }
+	.stabstr       0 : { *(.stabstr) }
+	.stab.excl     0 : { *(.stab.excl) }
+	.stab.exclstr  0 : { *(.stab.exclstr) }
+	.stab.index    0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+
+	/* DWARF debug sections.
+	   Symbols in the DWARF debugging sections are relative to the beginning
+	   of the section so we begin them at 0. */
+
+	/* DWARF 1 */
+	.debug          0 : { *(.debug) }
+	.line           0 : { *(.line) }
+
+	/* GNU DWARF 1 extensions */
+	.debug_srcinfo  0 : { *(.debug_srcinfo) }
+	.debug_sfnames  0 : { *(.debug_sfnames) }
+
+	/* DWARF 1.1 and DWARF 2 */
+	.debug_aranges  0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+
+	/* DWARF 2 */
+	.debug_info     0 : { *(.debug_info) }
+	.debug_abbrev   0 : { *(.debug_abbrev) }
+	.debug_line     0 : { *(.debug_line) }
+	.debug_frame    0 : { *(.debug_frame) }
+	.debug_str      0 : { *(.debug_str) }
+	.debug_loc      0 : { *(.debug_loc) }
+	.debug_macinfo  0 : { *(.debug_macinfo) }
+}

exosphere/loader_stub/loader_stub.specs

@@ -0,0 +1,7 @@
+%rename link old_link
+
+*link:
+%(old_link) -T %:getenv(TOPDIR /loader_stub.ld) --gc-sections --nmagic -nostdlib -nostartfiles
+
+*startfile:
+crti%O%s crtbegin%O%s

exosphere/loader_stub/source/secmon_loader_error.cpp

@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <exosphere.hpp>
+#include "secmon_loader_error.hpp"
+
+namespace ams::diag {
+
+    NORETURN void AbortImpl(const char *file, int line, const char *func, const char *expr, u64 value, const char *format, ...) {
+        AMS_UNUSED(file, line, func, expr, value, format);
+        ams::secmon::loader::ErrorReboot();
+    }
+
+    NORETURN void AbortImpl(const char *file, int line, const char *func, const char *expr, u64 value) {
+        AMS_UNUSED(file, line, func, expr, value);
+        ams::secmon::loader::ErrorReboot();
+    }
+
+    NORETURN void AbortImpl() {
+        ams::secmon::loader::ErrorReboot();
+    }
+
+}
+
+namespace ams::secmon::loader {
+
+    NORETURN void ErrorReboot() {
+        /* Invalidate the security engine. */
+        /* TODO */
+
+        /* Reboot. */
+        while (true) {
+            wdt::Reboot();
+        }
+    }
+
+}

exosphere/loader_stub/source/secmon_loader_error.hpp

@@ -13,14 +13,11 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
+#include <exosphere.hpp>
+#pragma once
 
-#ifndef EXOSPHERE_BPMPFW_SC7_H
-#define EXOSPHERE_BPMPFW_SC7_H
+namespace ams::secmon::loader {
 
-#include "utils.h"
+    NORETURN void ErrorReboot();
 
-void sc7_entry_main(void);
-
-void reboot(void);
-
-#endif
+}

exosphere/loader_stub/source/secmon_loader_main.cpp

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <exosphere.hpp>
+#include "secmon_loader_uncompress.hpp"
+#include "program_lz4.h"
+#include "boot_code_lz4.h"
+
+namespace ams::secmon::loader {
+
+    NORETURN void UncompressAndExecute() {
+        /* Uncompress the program image. */
+        Uncompress(secmon::MemoryRegionPhysicalTzramFullProgramImage.GetPointer(), secmon::MemoryRegionPhysicalTzramFullProgramImage.GetSize(), program_lz4, program_lz4_size);
+
+
+        /* Copy the boot image to the end of IRAM */
+        u8 *relocated_boot_code = secmon::MemoryRegionPhysicalIramBootCodeImage.GetEndPointer<u8>() - boot_code_lz4_size;
+        std::memcpy(relocated_boot_code, boot_code_lz4, boot_code_lz4_size);
+
+        /* Uncompress the boot image. */
+        Uncompress(secmon::MemoryRegionPhysicalIramBootCodeImage.GetPointer(), secmon::MemoryRegionPhysicalIramBootCodeImage.GetSize(), relocated_boot_code, boot_code_lz4_size);
+
+
+        /* Jump to the boot image. */
+        reinterpret_cast<void (*)()>(secmon::MemoryRegionPhysicalIramBootCodeImage.GetAddress())();
+
+        /* We will never reach this point. */
+        __builtin_unreachable();
+    }
+
+}

exosphere/loader_stub/source/secmon_loader_uncompress.cpp

@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <exosphere.hpp>
+#include "secmon_loader_uncompress.hpp"
+
+namespace ams::secmon::loader {
+
+    namespace {
+
+        class Lz4Uncompressor {
+            private:
+                const u8 *src;
+                size_t src_size;
+                size_t src_offset;
+                u8 *dst;
+                size_t dst_size;
+                size_t dst_offset;
+            public:
+                Lz4Uncompressor(void *dst, size_t dst_size, const void *src, size_t src_size) : src(static_cast<const u8 *>(src)), src_size(src_size), src_offset(0), dst(static_cast<u8 *>(dst)), dst_size(dst_size), dst_offset(0) {
+                    /* ... */
+                }
+
+                void Uncompress() {
+                    while (true) {
+                        /* Read a control byte. */
+                        const u8 control = this->ReadByte();
+
+                        /* Copy what it specifies we should copy. */
+                        this->Copy(this->GetCopySize(control >> 4));
+
+                        /* If we've exceeded size, we're done. */
+                        if (this->src_offset >= this->src_size) {
+                            break;
+                        }
+
+                        /* Read the wide copy offset. */
+                        u16 wide_offset = this->ReadByte();
+                        AMS_ABORT_UNLESS(this->CanRead());
+                        wide_offset |= (this->ReadByte() << 8);
+
+                        /* Determine the copy size. */
+                        const size_t wide_copy_size = this->GetCopySize(control & 0xF);
+
+                        /* Copy bytes. */
+                        const size_t end_offset = this->dst_offset + wide_copy_size + 4;
+                        for (size_t cur_offset = this->dst_offset; cur_offset < end_offset; this->dst_offset = (++cur_offset)) {
+                            AMS_ABORT_UNLESS(wide_offset <= cur_offset);
+
+                            this->dst[cur_offset] = this->dst[cur_offset - wide_offset];
+                        }
+                    }
+                }
+            private:
+                u8 ReadByte() {
+                    return this->src[this->src_offset++];
+                }
+
+                bool CanRead() const {
+                    return this->src_offset < this->src_size;
+                }
+
+                size_t GetCopySize(u8 control) {
+                    size_t size = control;
+
+                    if (control >= 0xF) {
+                        do {
+                            AMS_ABORT_UNLESS(this->CanRead());
+                            control = this->ReadByte();
+                            size += control;
+                        } while (control == 0xFF);
+                    }
+
+                    return size;
+                }
+
+                void Copy(size_t size) {
+                    __builtin_memcpy(this->dst + this->dst_offset, this->src + this->src_offset, size);
+                    this->dst_offset += size;
+                    this->src_offset += size;
+                }
+        };
+
+    }
+
+    void Uncompress(void *dst, size_t dst_size, const void *src, size_t src_size) {
+        /* Create an execute a decompressor. */
+        Lz4Uncompressor(dst, dst_size, src, src_size).Uncompress();
+    }
+
+}

exosphere/loader_stub/source/secmon_loader_uncompress.hpp

@@ -13,18 +13,11 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
+#include <vapours.hpp>
+#pragma once
 
-#include "utils.h"
-#include "i2c.h"
-#include "timer.h"
+namespace ams::secmon::loader {
 
-void do_shutdown(void) {
-    /* Initialize i2c. */
-    i2c_init();
+    void Uncompress(void *dst, size_t dst_size, const void *src, size_t src_size);
 
-    /* Stop alarm, shutdown. */
-    i2c_stop_rtc_alarm();
-    i2c_send_shutdown_cmd();
-    
-    while (true) { }
 }

exosphere/loader_stub/source/start.s

@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* For some reason GAS doesn't know about it, even with .cpu cortex-a57 */
+#define cpuactlr_el1 s3_1_c15_c2_0
+#define cpuectlr_el1 s3_1_c15_c2_1
+
+.macro      RESET_CORE
+    mov  x0, #(1 << 63)
+    msr  cpuactlr_el1, x0 /* disable regional clock gating */
+    isb
+    mov  x0, #3
+    msr  rmr_el3, x0
+    isb
+    dsb  sy
+    /* Nintendo forgot to copy-paste the branch instruction below. */
+    1:
+        wfi
+        b 1b
+.endm
+
+.macro      ERRATUM_INVALIDATE_BTB_AT_BOOT
+/* Nintendo copy-pasted https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/nvidia/tegra/common/aarch64/tegra_helpers.S#L312 */
+        /*
+        * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+        *
+        * SPDX-License-Identifier: BSD-3-Clause
+        */
+    /* The following comments are mine. */
+
+    /*
+        Enable invalidates of branch target buffer, then flush
+        the entire instruction cache at the local level, and
+        with the reg change, the branch target buffer, then disable
+        invalidates of the branch target buffer again.
+    */
+    mrs  x0, cpuactlr_el1
+    orr  x0, x0, #1
+    msr  cpuactlr_el1, x0
+
+    dsb  sy
+    isb
+    ic   iallu
+    dsb  sy
+    isb
+
+    mrs  x0, cpuactlr_el1
+    bic  x0, x0, #1
+    msr  cpuactlr_el1, x0
+
+.rept 7
+    nop                     /* wait long enough for the write to cpuactlr_el1 to have completed */
+.endr
+
+    /* if the OS lock is set, disable it and request a warm reset */
+    mrs  x0, oslsr_el1
+    ands x0, x0, #2
+    b.eq 2f
+    mov  x0, xzr
+    msr  oslar_el1, x0
+
+    RESET_CORE
+
+.rept 65
+    nop                     /* guard against speculative excecution */
+.endr
+
+    2:
+    /* set the OS lock */
+    mov  x0, #1
+    msr  oslar_el1, x0
+.endm
+
+.section    .crt0.text.start, "ax", %progbits
+.align      6
+.global     _start
+_start:
+    /* mask all interrupts */
+    msr daifset, #0xF
+
+    /* Fixup hardware erratum */
+    ERRATUM_INVALIDATE_BTB_AT_BOOT
+
+    /* Set the stack pointer to a temporary location. */
+    ldr x20, =0x7C020000
+    mov sp, x20
+
+    /* Call our init array functions. */
+    bl __libc_init_array
+
+    /* Uncompress the program and iram boot code images. */
+    b _ZN3ams6secmon6loader20UncompressAndExecuteEv

exosphere/lp0fw/linker.ld

@@ -1,24 +0,0 @@
-OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-
-ENTRY(_start)
-SECTIONS
-{
-    . = 0x40010000;
-
-    __start__ = ABSOLUTE(.);
-
-    .text   : ALIGN(4) { *(.text.start) *(.text*); . = ALIGN(4); }
-    .rodata : ALIGN(4) { *(.rodata*); . = ALIGN(4); }
-    .bss    : ALIGN(8) { __bss_start__ = .; *(.bss* COMMON); . = ALIGN(8); __bss_end__ = .; }
-
-    . = ALIGN(4);
-
-    __end__ = ABSOLUTE(.);
-    
-    __total_size__ = (__end__ - __start__);
-    __executable_size__ = (__end__ - _start);
-    
-    __stack_top__    = 0x40013000;
-    __stack_bottom__ = 0x40012000;
-}

exosphere/lp0fw/linker.specs

@@ -1,7 +0,0 @@
-%rename link                old_link
-
-*link:
-%(old_link) -T %:getenv(TOPDIR /linker.ld) --nmagic --gc-sections
-
-*startfile:
-crti%O%s crtbegin%O%s

exosphere/lp0fw/src/car.c

@@ -1,138 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <stdint.h>
-
-#include "utils.h"
-#include "car.h"
-#include "timer.h"
-#include "pmc.h"
-#include "emc.h"
-#include "lp0.h"
-
-static inline uint32_t get_special_clk_reg(CarDevice dev) {
-    switch (dev) {
-        case CARDEVICE_UARTA: return 0x178;
-        case CARDEVICE_UARTB: return 0x17C;
-        case CARDEVICE_I2C1: return 0x124;
-        case CARDEVICE_I2C5: return 0x128;
-        case CARDEVICE_ACTMON: return 0x3E8;
-        case CARDEVICE_BPMP: return 0;
-        default: reboot();
-    }
-}
-
-static inline uint32_t get_special_clk_val(CarDevice dev) {
-    switch (dev) {
-        case CARDEVICE_UARTA: return 0;
-        case CARDEVICE_UARTB: return 0;
-        case CARDEVICE_I2C1: return (6 << 29);
-        case CARDEVICE_I2C5: return (6 << 29);
-        case CARDEVICE_ACTMON: return (6 << 29);
-        case CARDEVICE_BPMP: return 0;
-        default: reboot();
-    }
-}
-
-static uint32_t g_clk_reg_offsets[NUM_CAR_BANKS] = {0x010, 0x014, 0x018, 0x360, 0x364, 0x280, 0x298};
-static uint32_t g_rst_reg_offsets[NUM_CAR_BANKS] = {0x004, 0x008, 0x00C, 0x358, 0x35C, 0x28C, 0x2A4};
-
-static uint32_t g_clk_clr_reg_offsets[NUM_CAR_BANKS] = {0x324, 0x32C, 0x334, 0x444, 0x44C, 0x228, 0x2A0};
-
-void car_configure_oscillators(void) {
-    /* Enable the crystal oscillator, setting drive strength to the saved value in PMC. */
-    CLK_RST_CONTROLLER_OSC_CTRL_0 = (CLK_RST_CONTROLLER_OSC_CTRL_0 & 0xFFFFFC0E) | 1 | (((APBDEV_PMC_OSC_EDPD_OVER_0 >> 1) & 0x3F) << 4);
-
-    /* Set CLK_M_DIVISOR to 1 (causes actual division by 2.) */
-    CLK_RST_CONTROLLER_SPARE_REG0_0 = (1 << 2);
-    /* Reading the register after writing it is required to ensure value takes. */
-    (void)(CLK_RST_CONTROLLER_SPARE_REG0_0);
-
-    /* Set TIMERUS_USEC_CFG to cycle at 0x60 / 0x5 = 19.2 MHz. */
-    /* Value is (dividend << 8) | (divisor). */
-    TIMERUS_USEC_CFG_0 = 0x45F;
-}
-
-void car_mbist_workaround(void) {
-    /* This code works around MBIST bug. */
-
-    /* Clear LVL2_CLK_GATE_OVR* registers. */
-    CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0 = 0;
-    CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0 = 0;
-    CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0 = 0;
-    CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0 = 0;
-    CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0 = 0;
-
-    /* Clear bit patterns in CAR. */
-    /* L: Reset all but RTC, TMR, GPIO, BPMP Cache (CACHE2). */
-    MAKE_CAR_REG(g_clk_clr_reg_offsets[0]) = MAKE_CAR_REG(g_clk_reg_offsets[0]) & 0x7FFFFECF;
-    /* H: Reset all but MC, PMC, FUSE, EMC. */
-    MAKE_CAR_REG(g_clk_clr_reg_offsets[1]) = MAKE_CAR_REG(g_clk_reg_offsets[1]) & 0xFDFFFF3E;
-    /* U: Reset all but CSITE, IRAM[A-D], BPMP Cache RAM (CRAM2). */
-    MAKE_CAR_REG(g_clk_clr_reg_offsets[2]) = MAKE_CAR_REG(g_clk_reg_offsets[2]) & 0xFE0FFDFF;
-    /* V: Reset all but MSELECT, S/PDIF audio doubler, TZRAM, SE. */
-    MAKE_CAR_REG(g_clk_clr_reg_offsets[3]) = MAKE_CAR_REG(g_clk_reg_offsets[3]) & 0x3FBFFFF7;
-    /* W: Reset all but PCIERX[0-5], ENTROPY. */
-    MAKE_CAR_REG(g_clk_clr_reg_offsets[4]) = MAKE_CAR_REG(g_clk_reg_offsets[4]) & 0xFFDFFF03;
-    /* X: Reset all but ETC, MCLK, MCLK2, I2C6, EMC_DLL, GPU, DBGAPB, PLLG_REF, . */
-    MAKE_CAR_REG(g_clk_clr_reg_offsets[5]) = MAKE_CAR_REG(g_clk_reg_offsets[5]) & 0xDCFFB87F;
-    /* Y: Reset all but MC_CDPA, MC_CCPA. */
-    MAKE_CAR_REG(g_clk_clr_reg_offsets[6]) = MAKE_CAR_REG(g_clk_reg_offsets[6]) & 0xFFFFFCFF;
-
-    /* Enable clock to MC1, if CH1 is enabled in EMC. */
-    if (EMC_FBIO_CFG7_0 & 4) { /* CH1_ENABLE */
-        CLK_RST_CONTROLLER_CLK_ENB_W_SET_0 |= 0x40000000; /* SET_CLK_ENB_MC1 */
-    }
-}
-
-void clk_enable(CarDevice dev) {
-    uint32_t special_reg;
-    if ((special_reg = get_special_clk_reg(dev))) {
-        MAKE_CAR_REG(special_reg) = get_special_clk_val(dev);
-    }
-    MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5]) |= BIT(dev & 0x1F);
-}
-
-void clk_disable(CarDevice dev) {
-    MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5]) &= ~(BIT(dev & 0x1F));
-}
-
-void rst_enable(CarDevice dev) {
-    MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5]) |= BIT(dev & 0x1F);
-}
-
-void rst_disable(CarDevice dev) {
-    MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5]) &= ~(BIT(dev & 0x1F));
-}
-
-void clkrst_enable(CarDevice dev) {
-    clk_enable(dev);
-    rst_disable(dev);
-}
-
-void clkrst_disable(CarDevice dev) {
-    rst_enable(dev);
-    clk_disable(dev);
-}
-
-void clkrst_reboot(CarDevice dev) {
-    clkrst_disable(dev);
-    clkrst_enable(dev);
-}
-
-void clkrst_enable_fuse_regs(bool enable) {
-    CLK_RST_CONTROLLER_MISC_CLK_ENB_0 = ((CLK_RST_CONTROLLER_MISC_CLK_ENB_0 & 0xEFFFFFFF) | ((enable & 1) << 28));
-}

exosphere/lp0fw/src/car.h

@@ -1,110 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef EXOSPHERE_WARMBOOT_BIN_CLOCK_AND_RESET_H
-#define EXOSPHERE_WARMBOOT_BIN_CLOCK_AND_RESET_H
-
-#include <stdint.h>
-
-#define CAR_BASE 0x60006000
-
-#define MAKE_CAR_REG(n) MAKE_REG32(CAR_BASE + n)
-
-#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0 MAKE_CAR_REG(0x048)
-#define CLK_RST_CONTROLLER_OSC_CTRL_0 MAKE_CAR_REG(0x050)
-#define CLK_RST_CONTROLLER_PLLX_BASE_0 MAKE_CAR_REG(0x0E0)
-#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0 MAKE_CAR_REG(0x3A4)
-#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET_0 MAKE_CAR_REG(0x450)
-#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR_0 MAKE_CAR_REG(0x454)
-
-#define CLK_RST_CONTROLLER_SUPER_CCLKG_DIVIDER_0 MAKE_CAR_REG(0x36C)
-#define CLK_RST_CONTROLLER_SUPER_CCLKP_DIVIDER_0 MAKE_CAR_REG(0x374)
-
-#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0 MAKE_CAR_REG(0x128)
-
-#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0 MAKE_CAR_REG(0x62C)
-#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_SOC_0 MAKE_CAR_REG(0x630)
-
-#define CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0 MAKE_CAR_REG(0x388)
-#define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT_0 MAKE_CAR_REG(0x3B4)
-
-#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0 MAKE_CAR_REG(0x0F8)
-#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0 MAKE_CAR_REG(0x0FC)
-#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC_0 MAKE_CAR_REG(0x3A0)
-#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0 MAKE_CAR_REG(0x3A4)
-#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE_0 MAKE_CAR_REG(0x554)
-
-#define CLK_RST_CONTROLLER_CCLKG_BURST_POLICY_0 MAKE_CAR_REG(0x368)
-#define CLK_RST_CONTROLLER_CCLKP_BURST_POLICY_0 MAKE_CAR_REG(0x370)
-
-#define CLK_RST_CONTROLLER_RST_DEVICES_H_0 MAKE_CAR_REG(0x008)
-
-#define CLK_RST_CONTROLLER_SPARE_REG0_0 MAKE_CAR_REG(0x55C)
-
-#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0 MAKE_CAR_REG(0x308)
-#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0 MAKE_CAR_REG(0x310)
-
-#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0 MAKE_CAR_REG(0x30C)
-#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0 MAKE_CAR_REG(0x314)
-#define CLK_RST_CONTROLLER_RST_DEV_V_CLR_0 MAKE_CAR_REG(0x434)
-
-#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0 MAKE_CAR_REG(0x320)
-#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0 MAKE_CAR_REG(0x328)
-#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0 MAKE_CAR_REG(0x330)
-#define CLK_RST_CONTROLLER_CLK_ENB_V_SET_0 MAKE_CAR_REG(0x440)
-#define CLK_RST_CONTROLLER_CLK_ENB_W_SET_0 MAKE_CAR_REG(0x448)
-#define CLK_RST_CONTROLLER_CLK_ENB_Y_SET_0 MAKE_CAR_REG(0x29C)
-
-#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0 MAKE_CAR_REG(0x32C)
-#define CLK_RST_CONTROLLER_CLK_ENB_W_CLR_0 MAKE_CAR_REG(0x44C)
-
-#define NUM_CAR_BANKS 7
-
-typedef enum {
-    CARDEVICE_UARTA = ((0 << 5) | 0x6),
-    CARDEVICE_UARTB = ((0 << 5) | 0x7),
-    CARDEVICE_UARTC = ((1 << 5) | 0x17),
-    CARDEVICE_I2C1 = ((0 << 5) | 0xC),
-    CARDEVICE_I2C5 = ((1 << 5) | 0xF),
-    CARDEVICE_TZRAM = ((3 << 5) | 0x1E),
-    CARDEVICE_SE = ((3 << 5) | 0x1F),
-    CARDEVICE_HOST1X = ((0 << 5) | 0x1C),
-    CARDEVICE_TSEC = ((2 << 5) | 0x13),
-    CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E),
-    CARDEVICE_SOR0 = ((5 << 5) | 0x16),
-    CARDEVICE_SOR1 = ((5 << 5) | 0x17),
-    CARDEVICE_KFUSE = ((1 << 5) | 0x8),
-    CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B),
-    CARDEVICE_CORESIGHT = ((2 << 5) | 0x9),
-    CARDEVICE_ACTMON = ((3 << 5) | 0x17),
-    CARDEVICE_BPMP = ((0 << 5) | 0x1)
-} CarDevice;
-
-void car_configure_oscillators(void);
-void car_mbist_workaround(void);
-
-void clk_enable(CarDevice dev);
-void clk_disable(CarDevice dev);
-void rst_enable(CarDevice dev);
-void rst_disable(CarDevice dev);
-
-void clkrst_enable(CarDevice dev);
-void clkrst_disable(CarDevice dev);
-void clkrst_reboot(CarDevice dev);
-
-void clkrst_enable_fuse_regs(bool enable);
-
-#endif

exosphere/lp0fw/src/cluster.c

@@ -1,163 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include <stdint.h>
- 
-#include "utils.h"
-#include "cluster.h"
-#include "car.h"
-#include "timer.h"
-#include "pmc.h"
-#include "misc.h"
-#include "i2c.h"
-#include "flow.h"
-#include "sysreg.h"
-
-static void cluster_pmc_enable_partition(uint32_t mask, uint32_t toggle) {
-    /* Set toggle if unset. */
-    if (!(APBDEV_PMC_PWRGATE_STATUS_0 & mask)) {
-        APBDEV_PMC_PWRGATE_TOGGLE_0 = toggle;
-    }
-    
-    /* Wait until toggle set. */
-    while (!(APBDEV_PMC_PWRGATE_STATUS_0 & mask)) { }
-
-    /* Remove clamping. */
-    APBDEV_PMC_REMOVE_CLAMPING_CMD_0 = mask;
-    while (APBDEV_PMC_CLAMP_STATUS_0 & mask) { }
-}
-
-void cluster_initialize_cpu(void) {
-    /* Hold CoreSight in reset. */
-    CLK_RST_CONTROLLER_RST_DEV_U_SET_0 = 0x200;
-
-    /* CAR2PMC_CPU_ACK_WIDTH should be set to 0. */
-    CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0 &= 0xFFFFF000;
-    
-    /* Restore SB_AA64_RESET values from PMC scratch. */
-    SB_AA64_RESET_LOW_0 = APBDEV_PMC_SECURE_SCRATCH34_0 | 1;
-    SB_AA64_RESET_HIGH_0 = APBDEV_PMC_SECURE_SCRATCH35_0;
-    
-    /* Set CDIV_ENB for CCLKG/CCLKP. */
-    CLK_RST_CONTROLLER_SUPER_CCLKG_DIVIDER_0 = 0x80000000;
-    CLK_RST_CONTROLLER_SUPER_CCLKP_DIVIDER_0 = 0x80000000;
-    
-    /* Enable CoreSight clock, take CoreSight out of reset. */
-    CLK_RST_CONTROLLER_CLK_ENB_U_SET_0 = 0x200;
-    CLK_RST_CONTROLLER_RST_DEV_U_CLR_0 = 0x200;
-    
-    /* Configure MSELECT to divide by 4, enable MSELECT clock. */
-    CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT_0 = 6; /* (6/2) + 1 = 4. */
-    CLK_RST_CONTROLLER_CLK_ENB_V_SET_0 = 0x8;
-    
-    /* Wait 2 us, then take MSELECT out of reset. */
-    timer_wait(2);
-    CLK_RST_CONTROLLER_RST_DEV_V_CLR_0 = 0x8;
-    
-    /* Set MSELECT WRAP_TO_SLAVE_INCR[0-2], clear ERR_RESP_EN_SLAVE[1-2]. */
-    MSELECT_CONFIG_0 = (MSELECT_CONFIG_0 & 0xFCFFFFFF) | 0x38000000;
-    
-    /* Clear PLLX_ENABLE. */
-    CLK_RST_CONTROLLER_PLLX_BASE_0 &= 0xBFFFFFFF;
-    
-    /* Clear PMC scratch 190, disable PMC DPD then wait 10 us. */
-    APBDEV_PMC_SCRATCH190_0 &= 0xFFFFFFFE;
-    APBDEV_PMC_DPD_SAMPLE_0 = 0;
-    timer_wait(10);
-    
-    /* Configure UART2 via GPIO controller 2 G. */
-    MAKE_REG32(0x6000D108) |= 4;  /* GPIO_CNF */
-    MAKE_REG32(0x6000D118) |= 4;  /* GPIO_OE */
-    MAKE_REG32(0x6000D128) &= ~4; /* GPIO_OUT */
-    
-    /* Set CL_DVFS RSVD0 + TRISTATE, read register to make it stick. */
-    PINMUX_AUX_DVFS_PWM_0 = 0x11;
-    (void)PINMUX_AUX_DVFS_PWM_0;
-    
-    /* Configure I2C. */
-    PINMUX_AUX_PWR_I2C_SCL_0 = 0x40;
-    PINMUX_AUX_PWR_I2C_SDA_0 = 0x40;
-    
-    /* Enable clock to CL_DVFS, and set its source/divider. */
-    CLK_RST_CONTROLLER_CLK_ENB_W_SET_0 = 0x08000000;
-    CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF_0 = 0xE;
-    CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_SOC_0 = 0xE;
-    
-    /* Power on I2C5, wait 5 us, set source + take out of reset. */
-    CLK_RST_CONTROLLER_CLK_ENB_H_SET_0 = 0x8000;
-    CLK_RST_CONTROLLER_RST_DEV_H_SET_0 = 0x8000;
-    timer_wait(5);
-    CLK_RST_CONTROLLER_CLK_SOURCE_I2C5_0 = 0x4;
-    CLK_RST_CONTROLLER_RST_DEV_H_CLR_0 = 0x8000;
-    
-    /* Enable the PMIC, wait 2ms. */
-    i2c_enable_pmic();
-    timer_wait(2000);
-    
-    /* Enable power to the CRAIL partition. */
-    cluster_pmc_enable_partition(1, 0x100);
-    
-    /* Remove SW clamp to CRAIL. */
-    APBDEV_PMC_SET_SW_CLAMP_0 = 0;
-    APBDEV_PMC_REMOVE_CLAMPING_CMD_0 = 1;
-    while (APBDEV_PMC_CLAMP_STATUS_0 & 1) { }
-    
-    /* Nintendo manually counts down from 8. I am not sure why this happens. */
-    {
-        volatile int32_t counter = 8;
-        while (counter >= 0) {
-            counter--;
-        }
-    }
-    
-    /* Power off I2C5. */
-    CLK_RST_CONTROLLER_RST_DEV_H_SET_0 = 0x8000;
-    CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0 = 0x8000;
-    
-    /* Disable clock to CL_DVFS */
-    CLK_RST_CONTROLLER_CLK_ENB_W_CLR_0 = 0x08000000;
-    
-    /* Perform RAM repair if necessary. */
-    flow_perform_ram_repair();
-    
-    /* Enable power to the non-CPU partition. */
-    cluster_pmc_enable_partition(0x8000, 0x10F);
-    
-    /* Enable clock to PLLP_OUT_CPU, wait 2 us. */
-    CLK_RST_CONTROLLER_CLK_ENB_Y_SET_0 = 0x80000000;
-    timer_wait(2);
-    
-    /* Enable clock to CPU, CPUG, wait 10 us. */
-    CLK_RST_CONTROLLER_CLK_ENB_L_SET_0 = 1;
-    CLK_RST_CONTROLLER_CLK_ENB_V_SET_0 = 1;
-    timer_wait(10);
-    
-    /* Set CPU clock sources to PLLP_OUT_0 + state to RUN, wait 10 us. */
-    CLK_RST_CONTROLLER_CCLKG_BURST_POLICY_0 = 0x20004444;
-    CLK_RST_CONTROLLER_CCLKP_BURST_POLICY_0 = 0x20004444;
-    timer_wait(10);
-    
-    /* Take non-CPU out of reset (write CLR_NONCPURESET). */
-    CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR_0 = 0x20000000;
-}
-
-void cluster_power_on_cpu(void) {
-    /*  Enable power to CE0 partition. */
-    cluster_pmc_enable_partition(0x4000, 0x10E);
-    
-    /* Clear CPU reset. */
-    CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR_0 = 0x10001;
-}

exosphere/lp0fw/src/emc.h

@@ -1,71 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef EXOSPHERE_WARMBOOT_BIN_EMC_H
-#define EXOSPHERE_WARMBOOT_BIN_EMC_H
-
-#include "utils.h"
-
-#define EMC_BASE (0x7001B000)
-
-#define EMC0_BASE (0x7001E000)
-#define EMC1_BASE (0x7001F000)
-
-
-#define MAKE_EMC_REG(ofs) (MAKE_REG32(EMC_BASE + ofs))
-
-#define MAKE_EMC0_REG(ofs) (MAKE_REG32(EMC0_BASE + ofs))
-#define MAKE_EMC1_REG(ofs) (MAKE_REG32(EMC1_BASE + ofs))
-
-#define EMC_CFG_0                    MAKE_EMC_REG(0x00C)
-
-#define EMC_ADR_CFG_0                MAKE_EMC_REG(0x10)
-
-#define EMC_TIMING_CONTROL_0         MAKE_EMC_REG(0x028)
-
-#define EMC_SELF_REF_0               MAKE_EMC_REG(0x0E0)
-
-#define EMC_MRW_0                    MAKE_EMC_REG(0x0E8)
-
-#define EMC_FBIO_CFG5_0              MAKE_EMC_REG(0x104)
-
-#define EMC_MRW3_0                   MAKE_EMC_REG(0x138)
-
-#define EMC_AUTO_CAL_CONFIG_0        MAKE_EMC_REG(0x2A4)
-
-#define EMC_REQ_CTRL_0               MAKE_EMC_REG(0x2B0)
-
-#define EMC_EMC_STATUS_0             MAKE_EMC_REG(0x2B4)
-#define EMC0_EMC_STATUS_0            MAKE_EMC0_REG(0x2B4)
-#define EMC1_EMC_STATUS_0            MAKE_EMC1_REG(0x2B4)
-
-#define EMC_CFG_DIG_DLL_0            MAKE_EMC_REG(0x2BC)
-#define EMC0_CFG_DIG_DLL_0           MAKE_EMC0_REG(0x2BC)
-#define EMC1_CFG_DIG_DLL_0           MAKE_EMC1_REG(0x2BC)
-
-#define EMC_ZCAL_INTERVAL_0          MAKE_EMC_REG(0x2E0)
-
-#define EMC_PMC_SCRATCH3_0           MAKE_EMC_REG(0x448)
-
-#define EMC_FBIO_CFG7_0              MAKE_EMC_REG(0x584)
-
-#define EMC_PMACRO_CFG_PM_GLOBAL_0_0 MAKE_EMC_REG(0xC30)
-#define EMC_PMACRO_TRAINING_CTRL_0_0 MAKE_EMC_REG(0xCF8)
-#define EMC_PMACRO_TRAINING_CTRL_1_0 MAKE_EMC_REG(0xCFC)
-
-void emc_configure_pmacro_training(void);
-
-#endif

exosphere/lp0fw/src/fuse.c

@@ -1,75 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include <stdint.h>
-
-#include "utils.h"
-#include "fuse.h"
-#include "car.h"
-#include "pmc.h"
-
-#define NUM_FUSE_BYPASS_ENTRIES 0
-
-bool fuse_check_downgrade_status(void) {
-    /* We aren't going to implement anti-downgrade. */
-    return false;
-}
-
-void fuse_disable_programming(void) {
-    FUSE_REGS->FUSE_DISABLEREGPROGRAM = 1;
-}
-
-static fuse_bypass_data_t g_fuse_bypass_entries[NUM_FUSE_BYPASS_ENTRIES] = {
-    /* No entries here. */
-};
-
-void fuse_configure_fuse_bypass(void) {
-    /* Make all fuse registers visible. */
-    clkrst_enable_fuse_regs(true);
-    
-    /* Configure bypass/override, only if programming is allowed. */
-    if (!(FUSE_REGS->FUSE_DISABLEREGPROGRAM & 1)) {
-        /* Enable write access and flush status. */
-        FUSE_REGS->FUSE_WRITE_ACCESS_SW = (FUSE_REGS->FUSE_WRITE_ACCESS_SW & ~0x1) | 0x10000;
-        
-        /* Enable fuse bypass config. */
-        FUSE_REGS->FUSE_FUSEBYPASS = 1;
-        
-        /* Override fuses. */
-        for (size_t i = 0; i < NUM_FUSE_BYPASS_ENTRIES; i++) {
-            MAKE_FUSE_REG(g_fuse_bypass_entries[i].offset) = g_fuse_bypass_entries[i].value;
-        }
-        
-        /* Disable fuse write access. */
-        FUSE_REGS->FUSE_WRITE_ACCESS_SW |= 1;
-        
-        /* Enable fuse bypass config. */
-        /* I think this is a bug, and Nintendo meant to write 0 here? */
-        FUSE_REGS->FUSE_FUSEBYPASS = 1;
-        
-        /* This...clears the disable programming bit(?). */
-        /* I have no idea why this happens. What? */
-        /* This is probably also either a bug or does nothing. */
-        /* Is this bit even clearable? */
-        FUSE_REGS->FUSE_DISABLEREGPROGRAM &= 0xFFFFFFFE;
-        
-        /* Restore saved private key disable bit. */
-        FUSE_REGS->FUSE_PRIVATEKEYDISABLE |= (APBDEV_PMC_SECURE_SCRATCH21_0 & 0x10);
-        
-        /* Lock private key disable secure scratch. */
-        APBDEV_PMC_SEC_DISABLE2_0 |= 0x4000000;
-    }
-}

exosphere/lp0fw/src/fuse.h

@@ -1,213 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef EXOSPHERE_WARMBOOT_BIN_FUSE_H
-#define EXOSPHERE_WARMBOOT_BIN_FUSE_H
-
-#include <stdbool.h>
-#include <stdint.h>
-
-#include "utils.h"
-
-typedef struct {
-    uint32_t FUSE_FUSECTRL;
-    uint32_t FUSE_FUSEADDR;
-    uint32_t FUSE_FUSERDATA;
-    uint32_t FUSE_FUSEWDATA;
-    uint32_t FUSE_FUSETIME_RD1;
-    uint32_t FUSE_FUSETIME_RD2;
-    uint32_t FUSE_FUSETIME_PGM1;
-    uint32_t FUSE_FUSETIME_PGM2;
-    uint32_t FUSE_PRIV2INTFC_START;
-    uint32_t FUSE_FUSEBYPASS;
-    uint32_t FUSE_PRIVATEKEYDISABLE;
-    uint32_t FUSE_DISABLEREGPROGRAM;
-    uint32_t FUSE_WRITE_ACCESS_SW;
-    uint32_t FUSE_PWR_GOOD_SW;
-    uint32_t _0x38;
-    uint32_t FUSE_PRIV2RESHIFT;
-    uint32_t _0x40[0x3];
-    uint32_t FUSE_FUSETIME_RD3;
-    uint32_t _0x50[0xC];
-    uint32_t FUSE_PRIVATE_KEY0_NONZERO;
-    uint32_t FUSE_PRIVATE_KEY1_NONZERO;
-    uint32_t FUSE_PRIVATE_KEY2_NONZERO;
-    uint32_t FUSE_PRIVATE_KEY3_NONZERO;
-    uint32_t FUSE_PRIVATE_KEY4_NONZERO;
-    uint32_t _0x90[0x1C];
-} tegra_fuse_t;
-
-typedef struct {
-    uint32_t FUSE_PRODUCTION_MODE;
-    uint32_t FUSE_JTAG_SECUREID_VALID;
-    uint32_t FUSE_ODM_LOCK;
-    uint32_t FUSE_OPT_OPENGL_EN;
-    uint32_t FUSE_SKU_INFO;
-    uint32_t FUSE_CPU_SPEEDO_0_CALIB;
-    uint32_t FUSE_CPU_IDDQ_CALIB;
-    uint32_t FUSE_DAC_CRT_CALIB;
-    uint32_t FUSE_DAC_HDTV_CALIB;
-    uint32_t FUSE_DAC_SDTV_CALIB;
-    uint32_t FUSE_OPT_FT_REV;
-    uint32_t FUSE_CPU_SPEEDO_1_CALIB;
-    uint32_t FUSE_CPU_SPEEDO_2_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_0_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_1_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_2_CALIB;
-    uint32_t FUSE_SOC_IDDQ_CALIB;
-    uint32_t FUSE_RESERVED_PRODUCTION_WP;
-    uint32_t FUSE_FA;
-    uint32_t FUSE_RESERVED_PRODUCTION;
-    uint32_t FUSE_HDMI_LANE0_CALIB;
-    uint32_t FUSE_HDMI_LANE1_CALIB;
-    uint32_t FUSE_HDMI_LANE2_CALIB;
-    uint32_t FUSE_HDMI_LANE3_CALIB;
-    uint32_t FUSE_ENCRYPTION_RATE;
-    uint32_t FUSE_PUBLIC_KEY[0x8];
-    uint32_t FUSE_TSENSOR1_CALIB;
-    uint32_t FUSE_TSENSOR2_CALIB;
-    uint32_t FUSE_VSENSOR_CALIB;
-    uint32_t FUSE_OPT_CP_REV;
-    uint32_t FUSE_OPT_PFG;
-    uint32_t FUSE_TSENSOR0_CALIB;
-    uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
-    uint32_t FUSE_SECURITY_MODE;
-    uint32_t FUSE_PRIVATE_KEY[0x5];
-    uint32_t FUSE_ARM_JTAG_DIS;
-    uint32_t FUSE_BOOT_DEVICE_INFO;
-    uint32_t FUSE_RESERVED_SW;
-    uint32_t FUSE_OPT_VP9_DISABLE;
-    uint32_t FUSE_RESERVED_ODM[0x8];
-    uint32_t FUSE_OBS_DIS;
-    uint32_t FUSE_NOR_INFO;
-    uint32_t FUSE_USB_CALIB;
-    uint32_t FUSE_SKU_DIRECT_CONFIG;
-    uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
-    uint32_t FUSE_PACKAGE_INFO;
-    uint32_t FUSE_OPT_VENDOR_CODE;
-    uint32_t FUSE_OPT_FAB_CODE;
-    uint32_t FUSE_OPT_LOT_CODE_0;
-    uint32_t FUSE_OPT_LOT_CODE_1;
-    uint32_t FUSE_OPT_WAFER_ID;
-    uint32_t FUSE_OPT_X_COORDINATE;
-    uint32_t FUSE_OPT_Y_COORDINATE;
-    uint32_t FUSE_OPT_SEC_DEBUG_EN;
-    uint32_t FUSE_OPT_OPS_RESERVED;
-    uint32_t FUSE_SATA_CALIB;
-    uint32_t FUSE_GPU_IDDQ_CALIB;
-    uint32_t FUSE_TSENSOR3_CALIB;
-    uint32_t FUSE_SKU_BOND_OUT_L;
-    uint32_t FUSE_SKU_BOND_OUT_H;
-    uint32_t FUSE_SKU_BOND_OUT_U;
-    uint32_t FUSE_SKU_BOND_OUT_V;
-    uint32_t FUSE_SKU_BOND_OUT_W;
-    uint32_t FUSE_OPT_SAMPLE_TYPE;
-    uint32_t FUSE_OPT_SUBREVISION;
-    uint32_t FUSE_OPT_SW_RESERVED_0;
-    uint32_t FUSE_OPT_SW_RESERVED_1;
-    uint32_t FUSE_TSENSOR4_CALIB;
-    uint32_t FUSE_TSENSOR5_CALIB;
-    uint32_t FUSE_TSENSOR6_CALIB;
-    uint32_t FUSE_TSENSOR7_CALIB;
-    uint32_t FUSE_OPT_PRIV_SEC_EN;
-    uint32_t FUSE_PKC_DISABLE;
-    uint32_t _0x16C;
-    uint32_t _0x170;
-    uint32_t _0x174;
-    uint32_t _0x178;
-    uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
-    uint32_t FUSE_TSENSOR_COMMON;
-    uint32_t FUSE_OPT_CP_BIN;
-    uint32_t FUSE_OPT_GPU_DISABLE;
-    uint32_t FUSE_OPT_FT_BIN;
-    uint32_t FUSE_OPT_DONE_MAP;
-    uint32_t _0x194;
-    uint32_t FUSE_APB2JTAG_DISABLE;
-    uint32_t FUSE_ODM_INFO;
-    uint32_t _0x1A0;
-    uint32_t _0x1A4;
-    uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
-    uint32_t _0x1AC;
-    uint32_t _0x1B0;
-    uint32_t _0x1B4;
-    uint32_t _0x1B8;
-    uint32_t _0x1BC;
-    uint32_t FUSE_WOA_SKU_FLAG;
-    uint32_t FUSE_ECO_RESERVE_1;
-    uint32_t FUSE_GCPLEX_CONFIG_FUSE;
-    uint32_t FUSE_PRODUCTION_MONTH;
-    uint32_t FUSE_RAM_REPAIR_INDICATOR;
-    uint32_t FUSE_TSENSOR9_CALIB;
-    uint32_t _0x1D8;
-    uint32_t FUSE_VMIN_CALIBRATION;
-    uint32_t FUSE_AGING_SENSOR_CALIBRATION;
-    uint32_t FUSE_DEBUG_AUTHENTICATION;
-    uint32_t FUSE_SECURE_PROVISION_INDEX;
-    uint32_t FUSE_SECURE_PROVISION_INFO;
-    uint32_t FUSE_OPT_GPU_DISABLE_CP1;
-    uint32_t FUSE_SPARE_ENDIS;
-    uint32_t FUSE_ECO_RESERVE_0;
-    uint32_t _0x1FC;
-    uint32_t _0x200;
-    uint32_t FUSE_RESERVED_CALIB0;
-    uint32_t FUSE_RESERVED_CALIB1;
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
-    uint32_t FUSE_OPT_CPU_DISABLE;
-    uint32_t FUSE_OPT_CPU_DISABLE_CP1;
-    uint32_t FUSE_TSENSOR10_CALIB;
-    uint32_t FUSE_TSENSOR10_CALIB_AUX;
-    uint32_t FUSE_OPT_RAM_SVOP_DP;
-    uint32_t FUSE_OPT_RAM_SVOP_PDP;
-    uint32_t FUSE_OPT_RAM_SVOP_REG;
-    uint32_t FUSE_OPT_RAM_SVOP_SP;
-    uint32_t FUSE_OPT_RAM_SVOP_SMPDP;
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
-    uint32_t FUSE_OPT_CPU_DISABLE_CP2;
-    uint32_t FUSE_OPT_GPU_DISABLE_CP2;
-    uint32_t FUSE_USB_CALIB_EXT;
-    uint32_t FUSE_RESERVED_FIELD;
-    uint32_t FUSE_OPT_ECC_EN;
-    uint32_t _0x25C;
-    uint32_t _0x260;
-    uint32_t _0x264;
-    uint32_t _0x268;
-    uint32_t _0x26C;
-    uint32_t _0x270;
-    uint32_t _0x274;
-    uint32_t _0x278;
-    uint32_t FUSE_SPARE_REALIGNMENT_REG;
-    uint32_t FUSE_SPARE_BIT[0x20];
-} tegra_fuse_chip_t;
-
-#define FUSE_REGS       ((volatile tegra_fuse_t *)(0x7000F800))
-#define FUSE_CHIP_REGS  ((volatile tegra_fuse_chip_t *)(0x7000F900))
-
-#define MAKE_FUSE_REG(n) MAKE_REG32(0x7000F800 + n)
-
-typedef struct {
-    uint32_t offset;
-    uint32_t value;
-} fuse_bypass_data_t;
-
-bool fuse_check_downgrade_status(void);
-void fuse_configure_fuse_bypass(void);
-void fuse_disable_programming(void);
-
-#endif

exosphere/lp0fw/src/i2c.c

@@ -1,76 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include "i2c.h"
-#include "timer.h"
-
-/* Prototypes for internal commands. */
-void i2c_set_test_master_config_load(void);
-void i2c_write(unsigned int device, uint32_t val, unsigned int num_bytes);
-void i2c_send_byte_command(unsigned int device, unsigned char reg, unsigned char b);
-
-/* Load hardware config for I2C5. */
-void i2c_set_test_master_config_load(void) {
-    /* Set MSTR_CONFIG_LOAD. */
-    I2C_I2C_CONFIG_LOAD_0 = 0x1;
-    
-    while (I2C_I2C_CONFIG_LOAD_0 & 1) {
-        /* Wait forever until it's unset. */
-    }
-}
-
-/* Writes a value to an i2c device. */
-void i2c_write(unsigned int device, uint32_t val, unsigned int num_bytes) {
-    if (num_bytes > 4) {
-        return;
-    }
-
-    /* Set device for 7-bit mode. */
-    I2C_I2C_CMD_ADDR0_0 = device << 1;
-
-    /* Load in data to write. */
-    I2C_I2C_CMD_DATA1_0 = val;
-
-    /* Set config with LENGTH = num_bytes, NEW_MASTER_FSM, DEBOUNCE_CNT = 4T. */
-    I2C_I2C_CNFG_0 = ((num_bytes << 1) - 2) | 0x2800;
-
-    i2c_set_test_master_config_load();
-
-    /* Config |= SEND; */
-    I2C_I2C_CNFG_0 = ((num_bytes << 1) - 2) | 0x2800 | 0x200;
-
-
-    while (I2C_I2C_STATUS_0 & 0x100) {
-        /* Wait until not busy. */
-    }
-    
-    while (I2C_I2C_STATUS_0 & 0xF) {
-        /* Wait until write successful. */
-    }
-}
-
-/* Writes a byte val to reg for given device. */
-void i2c_send_byte_command(unsigned int device, unsigned char reg, unsigned char b) {
-    uint32_t val = (reg) | (b << 8);
-    /* Write 1 byte (reg) + 1 byte (value) */
-    i2c_write(device, val, 2);
-}
-
-/* Enable the PMIC. */
-void i2c_enable_pmic(void) {
-    /* Write 00 to Device 27 Reg 00. */
-    i2c_send_byte_command(27, 0, 0x80);
-}

exosphere/lp0fw/src/i2c.h

@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef EXOSPHERE_WARMBOOT_BIN_I2C_H
-#define EXOSPHERE_WARMBOOT_BIN_I2C_H
-
-#include "utils.h"
-
-/* I2C_BASE = I2C5. */
-#define I2C_BASE (0x7000D000)
-
-#define MAKE_I2C_REG(ofs) (MAKE_REG32(I2C_BASE + ofs))
-
-#define I2C_I2C_CNFG_0                       MAKE_I2C_REG(0x000)
-
-#define I2C_I2C_CMD_ADDR0_0                  MAKE_I2C_REG(0x004)
-
-#define I2C_I2C_CMD_DATA1_0                  MAKE_I2C_REG(0x00C)
-
-#define I2C_I2C_STATUS_0                     MAKE_I2C_REG(0x01C)
-
-#define I2C_INTERRUPT_STATUS_REGISTER_0      MAKE_I2C_REG(0x068)
-
-#define I2C_I2C_CLK_DIVISOR_REGISTER_0       MAKE_I2C_REG(0x06C)
-
-#define I2C_I2C_BUS_CLEAR_CONFIG_0           MAKE_I2C_REG(0x084)
-
-#define I2C_I2C_BUS_CLEAR_STATUS_0           MAKE_I2C_REG(0x088)
-
-
-#define I2C_I2C_CONFIG_LOAD_0                MAKE_I2C_REG(0x08C)
-
-void i2c_enable_pmic(void);
-
-#endif

exosphere/lp0fw/src/lp0.c

@@ -1,98 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "utils.h"
-#include "lp0.h"
-#include "mc.h"
-#include "pmc.h"
-#include "misc.h"
-#include "fuse.h"
-#include "car.h"
-#include "emc.h"
-#include "cluster.h"
-#include "flow.h"
-#include "timer.h"
-#include "secmon.h"
-
-void reboot(void) {
-    /* Write MAIN_RST */
-    APBDEV_PMC_CNTRL_0 = 0x10;
-    while (true) {
-        /* Wait for reboot. */
-    }
-}
-
-void lp0_entry_main(warmboot_metadata_t *meta) {
-    const uint32_t target_firmware = meta->target_firmware;
-    /* Before doing anything else, ensure some sanity. */
-    if (meta->magic != WARMBOOT_MAGIC || target_firmware > ATMOSPHERE_TARGET_FIRMWARE_MAX) {
-        reboot();
-    }
-
-    /* [4.0.0+] First thing warmboot does is disable BPMP access to memory. */
-    if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_4_0_0)  {
-        disable_bpmp_access_to_dram();
-    }
-
-    /* Configure debugging depending on FUSE_PRODUCTION_MODE */
-    misc_configure_device_dbg_settings();
-
-    /* Check for downgrade. */
-    /* NOTE: We implemented this as "return false" */
-    if (fuse_check_downgrade_status()) {
-        reboot();
-    }
-
-    if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_3_0_0) {
-        /* Nintendo's firmware checks APBDEV_PMC_SECURE_SCRATCH32_0 against a per-warmboot binary value here. */
-        /* We won't bother with that. */
-        if (false /* APBDEV_PMC_SECURE_SCRATCH32_0 == WARMBOOT_MAGIC_NUMBER */) {
-            reboot();
-        }
-    }
-
-    /* TODO: Check that we're running at the correct physical address. */
-
-    /* Setup fuses, disable bypass. */
-    fuse_configure_fuse_bypass();
-
-    /* Configure oscillators/timing in CAR. */
-    car_configure_oscillators();
-
-    /* Restore RAM configuration. */
-    misc_restore_ram_svop();
-    emc_configure_pmacro_training();
-
-    /* Setup clock output for all devices, working around mbist bug. */
-    car_mbist_workaround();
-
-    /* Initialize the CPU cluster. */
-    cluster_initialize_cpu();
-
-    secmon_restore_to_tzram(target_firmware);
-
-    /* Power on the CPU cluster. */
-    cluster_power_on_cpu();
-
-    /* Nintendo clears most of warmboot.bin out of IRAM here. We're not gonna bother. */
-    /* memset( ... ); */
-
-    const uint32_t halt_val = (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_4_0_0) ? 0x40000000 : 0x50000000;
-    while (true) {
-        /* Halt the BPMP. */
-        FLOW_CTLR_HALT_COP_EVENTS_0 = halt_val;
-    }
-}

exosphere/lp0fw/src/mc.c

@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include <stdint.h>
-
-#include "mc.h"
-#include "utils.h"
-
-void disable_bpmp_access_to_dram(void) {
-    /* Modify carveout 4 to prevent BPMP access to dram (TZ will fix it). */
-    volatile security_carveout_t *carveout = (volatile security_carveout_t *)(MC_BASE + 0xC08 + 0x50 * (4 - CARVEOUT_ID_MIN));
-    carveout->paddr_low = 0;
-    carveout->paddr_high = 0;
-    carveout->size_big_pages = 1; /* 128 KiB */
-    carveout->client_access_0 = 0;
-    carveout->client_access_1 = 0;
-    carveout->client_access_2 = 0;
-    carveout->client_access_3 = 0;
-    carveout->client_access_4 = 0;
-    carveout->client_force_internal_access_0 = BIT(CSR_AVPCARM7R);
-    carveout->client_force_internal_access_1 = BIT(CSW_AVPCARM7W);
-    carveout->client_force_internal_access_2 = 0;
-    carveout->client_force_internal_access_3 = 0;
-    carveout->client_force_internal_access_4 = 0;
-    /* Set config to LOCKED, TZ-SECURE, untranslated addresses only. */
-    carveout->config = 0x8F;
-}

exosphere/lp0fw/src/mc.h

@@ -1,622 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef EXOSPHERE_WARMBOOT_BIN_MC_H
-#define EXOSPHERE_WARMBOOT_BIN_MC_H
-
-#include <stdint.h>
-
-#define MC_BASE_PHYS 0x70019000
-
-#define MC_BASE  (MC_BASE_PHYS)
-#define MAKE_MC_REG(n) MAKE_REG32(MC_BASE + n)
-
-#define MC_INTSTATUS                                            0x0
-#define MC_INTMASK                                              0x4
-#define MC_ERR_STATUS                                           0x8
-#define MC_ERR_ADR                                              0xc
-#define MC_SMMU_CONFIG                                          0x10
-#define MC_SMMU_TLB_CONFIG                                      0x14
-#define MC_SMMU_PTC_CONFIG                                      0x18
-#define MC_SMMU_PTB_ASID                                        0x1c
-#define MC_SMMU_PTB_DATA                                        0x20
-#define MC_SMMU_TLB_FLUSH                                       0x30
-#define MC_SMMU_PTC_FLUSH                                       0x34
-#define MC_SMMU_ASID_SECURITY                                   0x38
-#define MC_SMMU_ASID_SECURITY_1                                 0x3c
-#define MC_SMMU_ASID_SECURITY_2                                 0x9e0
-#define MC_SMMU_ASID_SECURITY_3                                 0x9e4
-#define MC_SMMU_ASID_SECURITY_4                                 0x9e8
-#define MC_SMMU_ASID_SECURITY_5                                 0x9ec
-#define MC_SMMU_ASID_SECURITY_6                                 0x9f0
-#define MC_SMMU_ASID_SECURITY_7                                 0x9f4
-#define MC_SMMU_AFI_ASID                                        0x238
-#define MC_SMMU_AVPC_ASID                                       0x23c
-#define MC_SMMU_PPCS1_ASID                                      0x298
-#define MC_SMMU_TRANSLATION_ENABLE_0                            0x228
-#define MC_SMMU_TRANSLATION_ENABLE_1                            0x22c
-#define MC_SMMU_TRANSLATION_ENABLE_2                            0x230
-#define MC_SMMU_TRANSLATION_ENABLE_3                            0x234
-#define MC_SMMU_TRANSLATION_ENABLE_4                            0xb98
-#define MC_PCFIFO_CLIENT_CONFIG0                                0xdd0
-#define MC_PCFIFO_CLIENT_CONFIG1                                0xdd4
-#define MC_PCFIFO_CLIENT_CONFIG2                                0xdd8
-#define MC_PCFIFO_CLIENT_CONFIG3                                0xddc
-#define MC_PCFIFO_CLIENT_CONFIG4                                0xde0
-#define MC_EMEM_CFG                                             0x50
-#define MC_EMEM_ADR_CFG                                         0x54
-#define MC_EMEM_ADR_CFG_DEV0                                    0x58
-#define MC_EMEM_ADR_CFG_DEV1                                    0x5c
-#define MC_EMEM_ADR_CFG_CHANNEL_MASK                            0x60
-#define MC_EMEM_ADR_CFG_BANK_MASK_0                             0x64
-#define MC_EMEM_ADR_CFG_BANK_MASK_1                             0x68
-#define MC_EMEM_ADR_CFG_BANK_MASK_2                             0x6c
-#define MC_SECURITY_CFG0                                        0x70
-#define MC_SECURITY_CFG1                                        0x74
-#define MC_SECURITY_CFG3                                        0x9bc
-#define MC_SECURITY_RSV                                         0x7c
-#define MC_EMEM_ARB_CFG                                         0x90
-#define MC_EMEM_ARB_OUTSTANDING_REQ                             0x94
-#define MC_EMEM_ARB_TIMING_RCD                                  0x98
-#define MC_EMEM_ARB_TIMING_RP                                   0x9c
-#define MC_EMEM_ARB_TIMING_RC                                   0xa0
-#define MC_EMEM_ARB_TIMING_RAS                                  0xa4
-#define MC_EMEM_ARB_TIMING_FAW                                  0xa8
-#define MC_EMEM_ARB_TIMING_RRD                                  0xac
-#define MC_EMEM_ARB_TIMING_RAP2PRE                              0xb0
-#define MC_EMEM_ARB_TIMING_WAP2PRE                              0xb4
-#define MC_EMEM_ARB_TIMING_R2R                                  0xb8
-#define MC_EMEM_ARB_TIMING_W2W                                  0xbc
-#define MC_EMEM_ARB_TIMING_R2W                                  0xc0
-#define MC_EMEM_ARB_TIMING_W2R                                  0xc4
-#define MC_EMEM_ARB_TIMING_RFCPB                                0x6c0
-#define MC_EMEM_ARB_TIMING_CCDMW                                0x6c4
-#define MC_EMEM_ARB_REFPB_HP_CTRL                               0x6f0
-#define MC_EMEM_ARB_REFPB_BANK_CTRL                             0x6f4
-#define MC_EMEM_ARB_DA_TURNS                                    0xd0
-#define MC_EMEM_ARB_DA_COVERS                                   0xd4
-#define MC_EMEM_ARB_MISC0                                       0xd8
-#define MC_EMEM_ARB_MISC1                                       0xdc
-#define MC_EMEM_ARB_MISC2                                       0xc8
-#define MC_EMEM_ARB_RING1_THROTTLE                              0xe0
-#define MC_EMEM_ARB_RING3_THROTTLE                              0xe4
-#define MC_EMEM_ARB_NISO_THROTTLE                               0x6b0
-#define MC_EMEM_ARB_OVERRIDE                                    0xe8
-#define MC_EMEM_ARB_RSV                                         0xec
-#define MC_CLKEN_OVERRIDE                                       0xf4
-#define MC_TIMING_CONTROL_DBG                                   0xf8
-#define MC_TIMING_CONTROL                                       0xfc
-#define MC_STAT_CONTROL                                         0x100
-#define MC_STAT_STATUS                                          0x104
-#define MC_STAT_EMC_CLOCK_LIMIT                                 0x108
-#define MC_STAT_EMC_CLOCK_LIMIT_MSBS                            0x10c
-#define MC_STAT_EMC_CLOCKS                                      0x110
-#define MC_STAT_EMC_CLOCKS_MSBS                                 0x114
-#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_LO                    0x118
-#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_LO                    0x158
-#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_HI                    0x11c
-#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_HI                    0x15c
-#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_UPPER                 0xa20
-#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_UPPER                 0xa24
-#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_LO            0x198
-#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_LO            0x1a8
-#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_HI            0x19c
-#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_HI            0x1ac
-#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_UPPER         0xa28
-#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_UPPER         0xa2c
-#define MC_STAT_EMC_FILTER_SET0_ASID                            0x1a0
-#define MC_STAT_EMC_FILTER_SET1_ASID                            0x1b0
-#define MC_STAT_EMC_FILTER_SET0_SLACK_LIMIT                     0x120
-#define MC_STAT_EMC_FILTER_SET1_SLACK_LIMIT                     0x160
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_0                        0x128
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_0                        0x168
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_1                        0x12c
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_1                        0x16c
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_2                        0x130
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_2                        0x170
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_3                        0x134
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_4                        0xb88
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_3                        0x174
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_4                        0xb8c
-#define MC_STAT_EMC_SET0_COUNT                                  0x138
-#define MC_STAT_EMC_SET0_COUNT_MSBS                             0x13c
-#define MC_STAT_EMC_SET1_COUNT                                  0x178
-#define MC_STAT_EMC_SET1_COUNT_MSBS                             0x17c
-#define MC_STAT_EMC_SET0_SLACK_ACCUM                            0x140
-#define MC_STAT_EMC_SET0_SLACK_ACCUM_MSBS                       0x144
-#define MC_STAT_EMC_SET1_SLACK_ACCUM                            0x180
-#define MC_STAT_EMC_SET1_SLACK_ACCUM_MSBS                       0x184
-#define MC_STAT_EMC_SET0_HISTO_COUNT                            0x148
-#define MC_STAT_EMC_SET0_HISTO_COUNT_MSBS                       0x14c
-#define MC_STAT_EMC_SET1_HISTO_COUNT                            0x188
-#define MC_STAT_EMC_SET1_HISTO_COUNT_MSBS                       0x18c
-#define MC_STAT_EMC_SET0_MINIMUM_SLACK_OBSERVED                 0x150
-#define MC_STAT_EMC_SET1_MINIMUM_SLACK_OBSERVED                 0x190
-#define MC_STAT_EMC_SET0_IDLE_CYCLE_COUNT                       0x1b8
-#define MC_STAT_EMC_SET0_IDLE_CYCL_COUNT_MSBS                   0x1bc
-#define MC_STAT_EMC_SET1_IDLE_CYCLE_COUNT                       0x1c8
-#define MC_STAT_EMC_SET1_IDLE_CYCL_COUNT_MSBS                   0x1cc
-#define MC_STAT_EMC_SET0_IDLE_CYCLE_PARTITION_SELECT            0x1c0
-#define MC_STAT_EMC_SET1_IDLE_CYCLE_PARTITION_SELECT            0x1d0
-#define MC_CLIENT_HOTRESET_CTRL                                 0x200
-#define MC_CLIENT_HOTRESET_CTRL_1                               0x970
-#define MC_CLIENT_HOTRESET_STATUS                               0x204
-#define MC_CLIENT_HOTRESET_STATUS_1                             0x974
-#define MC_EMEM_ARB_ISOCHRONOUS_0                               0x208
-#define MC_EMEM_ARB_ISOCHRONOUS_1                               0x20c
-#define MC_EMEM_ARB_ISOCHRONOUS_2                               0x210
-#define MC_EMEM_ARB_ISOCHRONOUS_3                               0x214
-#define MC_EMEM_ARB_ISOCHRONOUS_4                               0xb94
-#define MC_EMEM_ARB_HYSTERESIS_0                                0x218
-#define MC_EMEM_ARB_HYSTERESIS_1                                0x21c
-#define MC_EMEM_ARB_HYSTERESIS_2                                0x220
-#define MC_EMEM_ARB_HYSTERESIS_3                                0x224
-#define MC_EMEM_ARB_HYSTERESIS_4                                0xb84
-#define MC_EMEM_ARB_DHYSTERESIS_0                               0xbb0
-#define MC_EMEM_ARB_DHYSTERESIS_1                               0xbb4
-#define MC_EMEM_ARB_DHYSTERESIS_2                               0xbb8
-#define MC_EMEM_ARB_DHYSTERESIS_3                               0xbbc
-#define MC_EMEM_ARB_DHYSTERESIS_4                               0xbc0
-#define MC_EMEM_ARB_DHYST_CTRL                                  0xbcc
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0                        0xbd0
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1                        0xbd4
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2                        0xbd8
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3                        0xbdc
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4                        0xbe0
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5                        0xbe4
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6                        0xbe8
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7                        0xbec
-#define MC_RESERVED_RSV                                         0x3fc
-#define MC_DISB_EXTRA_SNAP_LEVELS                               0x408
-#define MC_APB_EXTRA_SNAP_LEVELS                                0x2a4
-#define MC_AHB_EXTRA_SNAP_LEVELS                                0x2a0
-#define MC_USBD_EXTRA_SNAP_LEVELS                               0xa18
-#define MC_ISP_EXTRA_SNAP_LEVELS                                0xa08
-#define MC_AUD_EXTRA_SNAP_LEVELS                                0xa10
-#define MC_MSE_EXTRA_SNAP_LEVELS                                0x40c
-#define MC_GK2_EXTRA_SNAP_LEVELS                                0xa40
-#define MC_A9AVPPC_EXTRA_SNAP_LEVELS                            0x414
-#define MC_FTOP_EXTRA_SNAP_LEVELS                               0x2bc
-#define MC_JPG_EXTRA_SNAP_LEVELS                                0xa3c
-#define MC_HOST_EXTRA_SNAP_LEVELS                               0xa14
-#define MC_SAX_EXTRA_SNAP_LEVELS                                0x2c0
-#define MC_DIS_EXTRA_SNAP_LEVELS                                0x2ac
-#define MC_VICPC_EXTRA_SNAP_LEVELS                              0xa1c
-#define MC_HDAPC_EXTRA_SNAP_LEVELS                              0xa48
-#define MC_AVP_EXTRA_SNAP_LEVELS                                0x2a8
-#define MC_USBX_EXTRA_SNAP_LEVELS                               0x404
-#define MC_PCX_EXTRA_SNAP_LEVELS                                0x2b8
-#define MC_SD_EXTRA_SNAP_LEVELS                                 0xa04
-#define MC_DFD_EXTRA_SNAP_LEVELS                                0xa4c
-#define MC_VE_EXTRA_SNAP_LEVELS                                 0x2d8
-#define MC_GK_EXTRA_SNAP_LEVELS                                 0xa00
-#define MC_VE2_EXTRA_SNAP_LEVELS                                0x410
-#define MC_SDM_EXTRA_SNAP_LEVELS                                0xa44
-#define MC_VIDEO_PROTECT_BOM                                    0x648
-#define MC_VIDEO_PROTECT_SIZE_MB                                0x64c
-#define MC_VIDEO_PROTECT_BOM_ADR_HI                             0x978
-#define MC_VIDEO_PROTECT_REG_CTRL                               0x650
-#define MC_ERR_VPR_STATUS                                       0x654
-#define MC_ERR_VPR_ADR                                          0x658
-#define MC_VIDEO_PROTECT_VPR_OVERRIDE                           0x418
-#define MC_VIDEO_PROTECT_VPR_OVERRIDE1                          0x590
-#define MC_IRAM_BOM                                             0x65c
-#define MC_IRAM_TOM                                             0x660
-#define MC_IRAM_ADR_HI                                          0x980
-#define MC_IRAM_REG_CTRL                                        0x964
-#define MC_EMEM_CFG_ACCESS_CTRL                                 0x664
-#define MC_TZ_SECURITY_CTRL                                     0x668
-#define MC_EMEM_ARB_OUTSTANDING_REQ_RING3                       0x66c
-#define MC_EMEM_ARB_OUTSTANDING_REQ_NISO                        0x6b4
-#define MC_EMEM_ARB_RING0_THROTTLE_MASK                         0x6bc
-#define MC_EMEM_ARB_NISO_THROTTLE_MASK                          0x6b8
-#define MC_EMEM_ARB_NISO_THROTTLE_MASK_1                        0xb80
-#define MC_SEC_CARVEOUT_BOM                                     0x670
-#define MC_SEC_CARVEOUT_SIZE_MB                                 0x674
-#define MC_SEC_CARVEOUT_ADR_HI                                  0x9d4
-#define MC_SEC_CARVEOUT_REG_CTRL                                0x678
-#define MC_ERR_SEC_STATUS                                       0x67c
-#define MC_ERR_SEC_ADR                                          0x680
-#define MC_PC_IDLE_CLOCK_GATE_CONFIG                            0x684
-#define MC_STUTTER_CONTROL                                      0x688
-#define MC_RESERVED_RSV_1                                       0x958
-#define MC_DVFS_PIPE_SELECT                                     0x95c
-#define MC_AHB_PTSA_MIN                                         0x4e0
-#define MC_AUD_PTSA_MIN                                         0x54c
-#define MC_MLL_MPCORER_PTSA_RATE                                0x44c
-#define MC_RING2_PTSA_RATE                                      0x440
-#define MC_USBD_PTSA_RATE                                       0x530
-#define MC_USBX_PTSA_MIN                                        0x528
-#define MC_USBD_PTSA_MIN                                        0x534
-#define MC_APB_PTSA_MAX                                         0x4f0
-#define MC_JPG_PTSA_RATE                                        0x584
-#define MC_DIS_PTSA_MIN                                         0x420
-#define MC_AVP_PTSA_MAX                                         0x4fc
-#define MC_AVP_PTSA_RATE                                        0x4f4
-#define MC_RING1_PTSA_MIN                                       0x480
-#define MC_DIS_PTSA_MAX                                         0x424
-#define MC_SD_PTSA_MAX                                          0x4d8
-#define MC_MSE_PTSA_RATE                                        0x4c4
-#define MC_VICPC_PTSA_MIN                                       0x558
-#define MC_PCX_PTSA_MAX                                         0x4b4
-#define MC_ISP_PTSA_RATE                                        0x4a0
-#define MC_A9AVPPC_PTSA_MIN                                     0x48c
-#define MC_RING2_PTSA_MAX                                       0x448
-#define MC_AUD_PTSA_RATE                                        0x548
-#define MC_HOST_PTSA_MIN                                        0x51c
-#define MC_MLL_MPCORER_PTSA_MAX                                 0x454
-#define MC_SD_PTSA_MIN                                          0x4d4
-#define MC_RING1_PTSA_RATE                                      0x47c
-#define MC_JPG_PTSA_MIN                                         0x588
-#define MC_HDAPC_PTSA_MIN                                       0x62c
-#define MC_AVP_PTSA_MIN                                         0x4f8
-#define MC_JPG_PTSA_MAX                                         0x58c
-#define MC_VE_PTSA_MAX                                          0x43c
-#define MC_DFD_PTSA_MAX                                         0x63c
-#define MC_VICPC_PTSA_RATE                                      0x554
-#define MC_GK_PTSA_MAX                                          0x544
-#define MC_VICPC_PTSA_MAX                                       0x55c
-#define MC_SDM_PTSA_MAX                                         0x624
-#define MC_SAX_PTSA_RATE                                        0x4b8
-#define MC_PCX_PTSA_MIN                                         0x4b0
-#define MC_APB_PTSA_MIN                                         0x4ec
-#define MC_GK2_PTSA_MIN                                         0x614
-#define MC_PCX_PTSA_RATE                                        0x4ac
-#define MC_RING1_PTSA_MAX                                       0x484
-#define MC_HDAPC_PTSA_RATE                                      0x628
-#define MC_MLL_MPCORER_PTSA_MIN                                 0x450
-#define MC_GK2_PTSA_MAX                                         0x618
-#define MC_AUD_PTSA_MAX                                         0x550
-#define MC_GK2_PTSA_RATE                                        0x610
-#define MC_ISP_PTSA_MAX                                         0x4a8
-#define MC_DISB_PTSA_RATE                                       0x428
-#define MC_VE2_PTSA_MAX                                         0x49c
-#define MC_DFD_PTSA_MIN                                         0x638
-#define MC_FTOP_PTSA_RATE                                       0x50c
-#define MC_A9AVPPC_PTSA_RATE                                    0x488
-#define MC_VE2_PTSA_MIN                                         0x498
-#define MC_USBX_PTSA_MAX                                        0x52c
-#define MC_DIS_PTSA_RATE                                        0x41c
-#define MC_USBD_PTSA_MAX                                        0x538
-#define MC_A9AVPPC_PTSA_MAX                                     0x490
-#define MC_USBX_PTSA_RATE                                       0x524
-#define MC_FTOP_PTSA_MAX                                        0x514
-#define MC_HDAPC_PTSA_MAX                                       0x630
-#define MC_SD_PTSA_RATE                                         0x4d0
-#define MC_DFD_PTSA_RATE                                        0x634
-#define MC_FTOP_PTSA_MIN                                        0x510
-#define MC_SDM_PTSA_RATE                                        0x61c
-#define MC_AHB_PTSA_RATE                                        0x4dc
-#define MC_SMMU_SMMU_PTSA_MAX                                   0x460
-#define MC_RING2_PTSA_MIN                                       0x444
-#define MC_SDM_PTSA_MIN                                         0x620
-#define MC_APB_PTSA_RATE                                        0x4e8
-#define MC_MSE_PTSA_MIN                                         0x4c8
-#define MC_HOST_PTSA_RATE                                       0x518
-#define MC_VE_PTSA_RATE                                         0x434
-#define MC_AHB_PTSA_MAX                                         0x4e4
-#define MC_SAX_PTSA_MIN                                         0x4bc
-#define MC_SMMU_SMMU_PTSA_MIN                                   0x45c
-#define MC_ISP_PTSA_MIN                                         0x4a4
-#define MC_HOST_PTSA_MAX                                        0x520
-#define MC_SAX_PTSA_MAX                                         0x4c0
-#define MC_VE_PTSA_MIN                                          0x438
-#define MC_GK_PTSA_MIN                                          0x540
-#define MC_MSE_PTSA_MAX                                         0x4cc
-#define MC_DISB_PTSA_MAX                                        0x430
-#define MC_DISB_PTSA_MIN                                        0x42c
-#define MC_SMMU_SMMU_PTSA_RATE                                  0x458
-#define MC_VE2_PTSA_RATE                                        0x494
-#define MC_GK_PTSA_RATE                                         0x53c
-#define MC_PTSA_GRANT_DECREMENT                                 0x960
-#define MC_LATENCY_ALLOWANCE_AVPC_0                             0x2e4
-#define MC_LATENCY_ALLOWANCE_AXIAP_0                            0x3a0
-#define MC_LATENCY_ALLOWANCE_XUSB_1                             0x380
-#define MC_LATENCY_ALLOWANCE_ISP2B_0                            0x384
-#define MC_LATENCY_ALLOWANCE_SDMMCAA_0                          0x3bc
-#define MC_LATENCY_ALLOWANCE_SDMMCA_0                           0x3b8
-#define MC_LATENCY_ALLOWANCE_ISP2_0                             0x370
-#define MC_LATENCY_ALLOWANCE_SE_0                               0x3e0
-#define MC_LATENCY_ALLOWANCE_ISP2_1                             0x374
-#define MC_LATENCY_ALLOWANCE_DC_0                               0x2e8
-#define MC_LATENCY_ALLOWANCE_VIC_0                              0x394
-#define MC_LATENCY_ALLOWANCE_DCB_1                              0x2f8
-#define MC_LATENCY_ALLOWANCE_NVDEC_0                            0x3d8
-#define MC_LATENCY_ALLOWANCE_DCB_2                              0x2fc
-#define MC_LATENCY_ALLOWANCE_TSEC_0                             0x390
-#define MC_LATENCY_ALLOWANCE_DC_2                               0x2f0
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB                  0x694
-#define MC_LATENCY_ALLOWANCE_PPCS_1                             0x348
-#define MC_LATENCY_ALLOWANCE_XUSB_0                             0x37c
-#define MC_LATENCY_ALLOWANCE_PPCS_0                             0x344
-#define MC_LATENCY_ALLOWANCE_TSECB_0                            0x3f0
-#define MC_LATENCY_ALLOWANCE_AFI_0                              0x2e0
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B                   0x698
-#define MC_LATENCY_ALLOWANCE_DC_1                               0x2ec
-#define MC_LATENCY_ALLOWANCE_APE_0                              0x3dc
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C                   0x6a0
-#define MC_LATENCY_ALLOWANCE_A9AVP_0                            0x3a4
-#define MC_LATENCY_ALLOWANCE_GPU2_0                             0x3e8
-#define MC_LATENCY_ALLOWANCE_DCB_0                              0x2f4
-#define MC_LATENCY_ALLOWANCE_HC_1                               0x314
-#define MC_LATENCY_ALLOWANCE_SDMMC_0                            0x3c0
-#define MC_LATENCY_ALLOWANCE_NVJPG_0                            0x3e4
-#define MC_LATENCY_ALLOWANCE_PTC_0                              0x34c
-#define MC_LATENCY_ALLOWANCE_ETR_0                              0x3ec
-#define MC_LATENCY_ALLOWANCE_MPCORE_0                           0x320
-#define MC_LATENCY_ALLOWANCE_VI2_0                              0x398
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB                  0x69c
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB                  0x6a4
-#define MC_LATENCY_ALLOWANCE_SATA_0                             0x350
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A                   0x690
-#define MC_LATENCY_ALLOWANCE_HC_0                               0x310
-#define MC_LATENCY_ALLOWANCE_DC_3                               0x3c8
-#define MC_LATENCY_ALLOWANCE_GPU_0                              0x3ac
-#define MC_LATENCY_ALLOWANCE_SDMMCAB_0                          0x3c4
-#define MC_LATENCY_ALLOWANCE_ISP2B_1                            0x388
-#define MC_LATENCY_ALLOWANCE_NVENC_0                            0x328
-#define MC_LATENCY_ALLOWANCE_HDA_0                              0x318
-#define MC_MIN_LENGTH_APE_0                                     0xb34
-#define MC_MIN_LENGTH_DCB_2                                     0x8a8
-#define MC_MIN_LENGTH_A9AVP_0                                   0x950
-#define MC_MIN_LENGTH_TSEC_0                                    0x93c
-#define MC_MIN_LENGTH_DC_1                                      0x898
-#define MC_MIN_LENGTH_AXIAP_0                                   0x94c
-#define MC_MIN_LENGTH_ISP2B_0                                   0x930
-#define MC_MIN_LENGTH_VI2_0                                     0x944
-#define MC_MIN_LENGTH_DCB_0                                     0x8a0
-#define MC_MIN_LENGTH_DCB_1                                     0x8a4
-#define MC_MIN_LENGTH_PPCS_1                                    0x8f4
-#define MC_MIN_LENGTH_NVJPG_0                                   0xb3c
-#define MC_MIN_LENGTH_HDA_0                                     0x8c4
-#define MC_MIN_LENGTH_NVENC_0                                   0x8d4
-#define MC_MIN_LENGTH_SDMMC_0                                   0xb18
-#define MC_MIN_LENGTH_ISP2B_1                                   0x934
-#define MC_MIN_LENGTH_HC_1                                      0x8c0
-#define MC_MIN_LENGTH_DC_3                                      0xb20
-#define MC_MIN_LENGTH_AVPC_0                                    0x890
-#define MC_MIN_LENGTH_VIC_0                                     0x940
-#define MC_MIN_LENGTH_ISP2_0                                    0x91c
-#define MC_MIN_LENGTH_HC_0                                      0x8bc
-#define MC_MIN_LENGTH_SE_0                                      0xb38
-#define MC_MIN_LENGTH_NVDEC_0                                   0xb30
-#define MC_MIN_LENGTH_SATA_0                                    0x8fc
-#define MC_MIN_LENGTH_DC_0                                      0x894
-#define MC_MIN_LENGTH_XUSB_1                                    0x92c
-#define MC_MIN_LENGTH_DC_2                                      0x89c
-#define MC_MIN_LENGTH_SDMMCAA_0                                 0xb14
-#define MC_MIN_LENGTH_GPU_0                                     0xb04
-#define MC_MIN_LENGTH_ETR_0                                     0xb44
-#define MC_MIN_LENGTH_AFI_0                                     0x88c
-#define MC_MIN_LENGTH_PPCS_0                                    0x8f0
-#define MC_MIN_LENGTH_ISP2_1                                    0x920
-#define MC_MIN_LENGTH_XUSB_0                                    0x928
-#define MC_MIN_LENGTH_MPCORE_0                                  0x8cc
-#define MC_MIN_LENGTH_TSECB_0                                   0xb48
-#define MC_MIN_LENGTH_SDMMCA_0                                  0xb10
-#define MC_MIN_LENGTH_GPU2_0                                    0xb40
-#define MC_MIN_LENGTH_SDMMCAB_0                                 0xb1c
-#define MC_MIN_LENGTH_PTC_0                                     0x8f8
-#define MC_EMEM_ARB_OVERRIDE_1                                  0x968
-#define MC_VIDEO_PROTECT_GPU_OVERRIDE_0                         0x984
-#define MC_VIDEO_PROTECT_GPU_OVERRIDE_1                         0x988
-#define MC_EMEM_ARB_STATS_0                                     0x990
-#define MC_EMEM_ARB_STATS_1                                     0x994
-#define MC_MTS_CARVEOUT_BOM                                     0x9a0
-#define MC_MTS_CARVEOUT_SIZE_MB                                 0x9a4
-#define MC_MTS_CARVEOUT_ADR_HI                                  0x9a8
-#define MC_MTS_CARVEOUT_REG_CTRL                                0x9ac
-#define MC_ERR_MTS_STATUS                                       0x9b0
-#define MC_ERR_MTS_ADR                                          0x9b4
-#define MC_ERR_GENERALIZED_CARVEOUT_STATUS                      0xc00
-#define MC_ERR_GENERALIZED_CARVEOUT_ADR                         0xc04
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2     0xd74
-#define MC_SECURITY_CARVEOUT4_CFG0                              0xcf8
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2                    0xd10
-#define MC_SECURITY_CARVEOUT4_SIZE_128KB                        0xd04
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4                    0xc28
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1     0xc30
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4     0xc8c
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0     0xd1c
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1     0xd70
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0     0xc2c
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4     0xd7c
-#define MC_SECURITY_CARVEOUT3_SIZE_128KB                        0xcb4
-#define MC_SECURITY_CARVEOUT2_CFG0                              0xc58
-#define MC_SECURITY_CARVEOUT1_CFG0                              0xc08
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2     0xc84
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0                    0xc68
-#define MC_SECURITY_CARVEOUT3_BOM                               0xcac
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2                    0xc70
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3     0xd78
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0     0xc7c
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4                    0xd18
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1                    0xcbc
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3     0xc38
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2     0xc34
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2                    0xcc0
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2                    0xd60
-#define MC_SECURITY_CARVEOUT3_CFG0                              0xca8
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0                    0xcb8
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3     0xc88
-#define MC_SECURITY_CARVEOUT2_SIZE_128KB                        0xc64
-#define MC_SECURITY_CARVEOUT5_BOM_HI                            0xd50
-#define MC_SECURITY_CARVEOUT1_SIZE_128KB                        0xc14
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3                    0xd14
-#define MC_SECURITY_CARVEOUT1_BOM                               0xc0c
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4     0xd2c
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4                    0xd68
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4                    0xcc8
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0                    0xd58
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2     0xd24
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3                    0xcc4
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4                    0xc78
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1                    0xc1c
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0                    0xc18
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3     0xd28
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1                    0xd5c
-#define MC_SECURITY_CARVEOUT3_BOM_HI                            0xcb0
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3     0xcd8
-#define MC_SECURITY_CARVEOUT2_BOM_HI                            0xc60
-#define MC_SECURITY_CARVEOUT4_BOM_HI                            0xd00
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3                    0xd64
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4     0xcdc
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1     0xc80
-#define MC_SECURITY_CARVEOUT5_SIZE_128KB                        0xd54
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1     0xd20
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2     0xcd4
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1                    0xd0c
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3                    0xc74
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0     0xccc
-#define MC_SECURITY_CARVEOUT4_BOM                               0xcfc
-#define MC_SECURITY_CARVEOUT5_CFG0                              0xd48
-#define MC_SECURITY_CARVEOUT2_BOM                               0xc5c
-#define MC_SECURITY_CARVEOUT5_BOM                               0xd4c
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3                    0xc24
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0     0xd6c
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1     0xcd0
-#define MC_SECURITY_CARVEOUT1_BOM_HI                            0xc10
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2                    0xc20
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4     0xc3c
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1                    0xc6c
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0                    0xd08
-#define MC_ERR_APB_ASID_UPDATE_STATUS                           0x9d0
-#define MC_DA_CONFIG0                                           0x9dc
-
-/* Virtual aliases */
-#define VIRT_MC_SECURITY_CFG3   MAKE_MC_REG(MC_SECURITY_CFG3)
-
-/* Memory Controller clients */
-#define CLIENT_ACCESS_NUM_CLIENTS   32
-typedef enum {
-    /* _ACCESS0 */
-    CSR_PTCR = (0 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0A = (1 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0AB = (2 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0B = (3 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0BB = (4 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0C = (5 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0CB = (6 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_AFIR = (14 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_AVPCARM7R = (15 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAYHC = (16 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAYHCB = (17 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_HDAR = (21 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_HOST1XDMAR = (22 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_HOST1XR = (23 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_NVENCSRD = (28 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_PPCSAHBDMAR = (29 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_PPCSAHBSLVR = (30 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_SATAR = (31 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    
-    /* _ACCESS1 */
-    CSR_VDEBSEVR = (34 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSR_VDEMBER = (35 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSR_VDEMCER = (36 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSR_VDETPER = (37 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSR_MPCORELPR = (38 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSR_MPCORER = (39 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_NVENCSWR = (43 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_AFIW = (49 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_AVPCARM7W = (50 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_HDAW = (53 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_HOST1XW = (54 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_MPCORELPW = (56 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_MPCOREW = (57 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_PPCSAHBDMAW = (59 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_PPCSAHBSLVW = (60 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_SATAW = (61 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_VDEBSEVW = (62 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_VDEDBGW = (63 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    
-    /* _ACCESS2 */
-    CSW_VDEMBEW = (64 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_VDETPMW = (65 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_ISPRA = (68 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_ISPWA = (70 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_ISPWB = (71 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_XUSB_HOSTR = (74 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_XUSB_HOSTW = (75 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_XUSB_DEVR = (76 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_XUSB_DEVW = (77 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_ISPRAB = (78 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_ISPWAB = (80 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_ISPWBB = (81 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_TSECSRD = (84 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_TSECSWR = (85 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_A9AVPSCR = (86 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_A9AVPSCW = (87 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_GPUSRD = (88 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_GPUSWR = (89 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_DISPLAYT = (90 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    
-    /* _ACCESS3 */
-    CSR_SDMMCRA = (96 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_SDMMCRAA = (97 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_SDMMCR = (98 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_SDMMCRAB = (99 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_SDMMCWA = (100 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_SDMMCWAA = (101 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_SDMMCW = (102 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_SDMMCWAB = (103 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_VICSRD = (108 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_VICSWR = (109 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_VIW = (114 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_DISPLAYD = (115 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_NVDECSRD = (120 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_NVDECSWR = (121 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_APER = (122 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_APEW = (123 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_NVJPGSRD = (126 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_NVJPGSWR = (127 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    
-    /* _ACCESS4 */
-    CSR_SESRD = (128 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSW_SESWR = (129 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSR_AXIAPR = (130 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSW_AXIAPW = (131 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSR_ETRR = (132 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSW_ETRW = (133 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSR_TSECSRDB = (134 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSW_TSECSWRB = (135 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSR_GPUSRD2 = (136 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSW_GPUSWR2 = (137 - (CLIENT_ACCESS_NUM_CLIENTS * 4))
-} McClient;
-
-/* Memory Controller carveouts */
-#define CARVEOUT_ID_MIN 1
-#define CARVEOUT_ID_MAX 5
-typedef struct {
-    uint32_t config;
-    uint32_t paddr_low;
-    uint32_t paddr_high;
-    uint32_t size_big_pages;
-    uint32_t client_access_0;
-    uint32_t client_access_1;
-    uint32_t client_access_2;
-    uint32_t client_access_3;
-    uint32_t client_access_4;
-    uint32_t client_force_internal_access_0;
-    uint32_t client_force_internal_access_1;
-    uint32_t client_force_internal_access_2;
-    uint32_t client_force_internal_access_3;
-    uint32_t client_force_internal_access_4;
-    uint8_t padding[0x18];
-} security_carveout_t;
-
-void disable_bpmp_access_to_dram(void);
-
-#endif

exosphere/lp0fw/src/misc.c

@@ -1,52 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include <stdint.h>
-
-#include "utils.h"
-#include "misc.h"
-#include "fuse.h"
-#include "sysreg.h"
-#include "pmc.h"
-
-void misc_configure_device_dbg_settings(void) {
-    /* Set APB_MISC_PP_CONFIG_CTL_TBE (enables RTCK daisy-chaining). */
-    APB_MISC_PP_CONFIG_CTL_0 = 0x80;
-    
-    /* Configure JTAG and debug bits. */
-    if (FUSE_CHIP_REGS->FUSE_SECURITY_MODE == 1) {
-        uint32_t secure_boot_val = 0b0100;      /* Set NIDEN for aarch64. */
-        uint32_t pp_config_ctl_val = 0x40;      /* Set APB_MISC_PP_CONFIG_CTL_JTAG. */
-        if (APBDEV_PMC_STICKY_BITS_0 & 0x40) {
-            pp_config_ctl_val = 0x0;
-        } else {
-            secure_boot_val = 0b1101;           /* Set SPNIDEN, NIDEN, DBGEN for aarch64. */
-        }
-        SB_PFCFG_0 = (SB_PFCFG_0 & ~0b1111) | secure_boot_val;      /* Configure debug bits. */
-        APB_MISC_PP_CONFIG_CTL_0 |= pp_config_ctl_val;              /* Configure JTAG. */
-    }
-    
-    /* Set HDA_LPBK_DIS if FUSE_SECURITY_MODE is set (disables HDA codec loopback). */
-    APBDEV_PMC_STICKY_BITS_0 |= FUSE_CHIP_REGS->FUSE_SECURITY_MODE;
-    
-    /* Set E_INPUT in PINMUX_AUX_GPIO_PA6_0 (needed by the XUSB and SATA controllers). */
-    PINMUX_AUX_GPIO_PA6_0 |= 0x40;
-}
-
-void misc_restore_ram_svop(void) {
-    /* This sets CFG2TMC_RAM_SVOP_PDP to 0x2. */
-    APB_MISC_GP_ASDBGREG_0 = (APB_MISC_GP_ASDBGREG_0 & 0xFCFFFFFF) | 0x02000000;
-}

exosphere/lp0fw/src/pmc.h

@@ -1,57 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef EXOSPHERE_WARMBOOT_BIN_PMC_H
-#define EXOSPHERE_WARMBOOT_BIN_PMC_H
-
-#include "utils.h"
-
-#define PMC_BASE (0x7000E400)
-
-#define MAKE_PMC_REG(ofs) (MAKE_REG32(PMC_BASE + ofs))
-
-#define APBDEV_PMC_CNTRL_0                  MAKE_PMC_REG(0x000)
-#define APBDEV_PMC_DPD_SAMPLE_0             MAKE_PMC_REG(0x020)
-#define APBDEV_PMC_DPD_ENABLE_0             MAKE_PMC_REG(0x024)
-#define APBDEV_PMC_CLAMP_STATUS_0           MAKE_PMC_REG(0x02C)
-#define APBDEV_PMC_PWRGATE_TOGGLE_0         MAKE_PMC_REG(0x030)
-#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0    MAKE_PMC_REG(0x034)
-#define APBDEV_PMC_PWRGATE_STATUS_0         MAKE_PMC_REG(0x038)
-#define APBDEV_PMC_SCRATCH12_0              MAKE_PMC_REG(0x080)
-#define APBDEV_PMC_SCRATCH13_0              MAKE_PMC_REG(0x084)
-#define APBDEV_PMC_SCRATCH18_0              MAKE_PMC_REG(0x098)
-#define APBDEV_PMC_SCRATCH190_0             MAKE_PMC_REG(0x818)
-#define APBDEV_PMC_OSC_EDPD_OVER_0          MAKE_PMC_REG(0x1A4)
-#define APBDEV_PMC_STICKY_BITS_0            MAKE_PMC_REG(0x2C0)
-#define APBDEV_PMC_SEC_DISABLE2_0           MAKE_PMC_REG(0x2C4)
-#define APBDEV_PMC_WEAK_BIAS_0              MAKE_PMC_REG(0x2C8)
-#define APBDEV_PMC_SECURE_SCRATCH21_0       MAKE_PMC_REG(0x334)
-#define APBDEV_PMC_SECURE_SCRATCH32_0       MAKE_PMC_REG(0x360)
-#define APBDEV_PMC_SECURE_SCRATCH34_0       MAKE_PMC_REG(0x368)
-#define APBDEV_PMC_SECURE_SCRATCH35_0       MAKE_PMC_REG(0x36C)
-#define APBDEV_PMC_SECURE_SCRATCH112_0      MAKE_PMC_REG(0xB18)
-#define APBDEV_PMC_SECURE_SCRATCH113_0      MAKE_PMC_REG(0xB1C)
-#define APBDEV_PMC_SECURE_SCRATCH114_0      MAKE_PMC_REG(0xB20)
-#define APBDEV_PMC_SECURE_SCRATCH115_0      MAKE_PMC_REG(0xB24)
-#define APBDEV_PMC_FUSE_CTRL                MAKE_PMC_REG(0x450)
-#define APBDEV_PMC_IO_DPD3_REQ_0            MAKE_PMC_REG(0x45C)
-#define APBDEV_PMC_IO_DPD3_STATUS_0         MAKE_PMC_REG(0x460)
-#define APBDEV_PMC_IO_DPD4_REQ_0            MAKE_PMC_REG(0x464)
-#define APBDEV_PMC_IO_DPD4_STATUS_0         MAKE_PMC_REG(0x468)
-#define APBDEV_PMC_SET_SW_CLAMP_0           MAKE_PMC_REG(0x47C)
-#define APBDEV_PMC_DDR_CNTRL_0              MAKE_PMC_REG(0x4E4)
-
-#endif

exosphere/lp0fw/src/se.c

@@ -1,252 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include <string.h>
-
-#include "utils.h"
-#include "lp0.h"
-#include "se.h"
-
-static void trigger_se_blocking_op(unsigned int op, void *dst, size_t dst_size, const void *src, size_t src_size);
-
-/* Initialize a SE linked list. */
-static void __attribute__((__noinline__)) ll_init(volatile se_ll_t *ll, void *buffer, size_t size) {
-    ll->num_entries = 0; /* 1 Entry. */
-
-    if (buffer != NULL) {
-        ll->addr_info.address = (uint32_t) buffer;
-        ll->addr_info.size = (uint32_t) size;
-    } else {
-        ll->addr_info.address = 0;
-        ll->addr_info.size = 0;
-    }
-}
-
-void se_check_error_status_reg(void) {
-    if (se_get_regs()->SE_ERR_STATUS) {
-        reboot();
-    }
-}
-
-void se_check_for_error(void) {
-    volatile tegra_se_t *se = se_get_regs();
-    if (se->SE_INT_STATUS & 0x10000 || se->SE_STATUS & 3 || se->SE_ERR_STATUS) {
-        reboot();
-    }
-}
-
-void se_verify_flags_cleared(void) {
-    if (se_get_regs()->SE_STATUS & 3) {
-        reboot();
-    }
-}
-
-void clear_aes_keyslot(unsigned int keyslot) {
-    volatile tegra_se_t *se = se_get_regs();
-    
-    if (keyslot >= KEYSLOT_AES_MAX) {
-        reboot();
-    }
-
-    /* Zero out the whole keyslot and IV. */
-    for (unsigned int i = 0; i < 0x10; i++) {
-        se->SE_CRYPTO_KEYTABLE_ADDR = (keyslot << 4) | i;
-        se->SE_CRYPTO_KEYTABLE_DATA = 0;
-    }
-}
-
-void clear_rsa_keyslot(unsigned int keyslot) {
-    volatile tegra_se_t *se = se_get_regs();
-    
-    if (keyslot >= KEYSLOT_RSA_MAX) {
-        reboot();
-    }
-
-    /* Zero out the whole keyslot. */
-    for (unsigned int i = 0; i < 0x40; i++) {
-        /* Select Keyslot Modulus[i] */
-        se->SE_RSA_KEYTABLE_ADDR = (keyslot << 7) | i | 0x40;
-        se->SE_RSA_KEYTABLE_DATA = 0;
-    }
-    for (unsigned int i = 0; i < 0x40; i++) {
-        /* Select Keyslot Expontent[i] */
-        se->SE_RSA_KEYTABLE_ADDR = (keyslot << 7) | i;
-        se->SE_RSA_KEYTABLE_DATA = 0;
-    }
-}
-
-void clear_aes_keyslot_iv(unsigned int keyslot) {
-    volatile tegra_se_t *se = se_get_regs();
-    
-    if (keyslot >= KEYSLOT_AES_MAX) {
-        reboot();
-    }
-
-    for (size_t i = 0; i < (0x10 >> 2); i++) {
-        se->SE_CRYPTO_KEYTABLE_ADDR = (keyslot << 4) | 8 | i;
-        se->SE_CRYPTO_KEYTABLE_DATA = 0;
-    }
-}
-
-
-void trigger_se_blocking_op(unsigned int op, void *dst, size_t dst_size, const void *src, size_t src_size) {
-    volatile tegra_se_t *se = se_get_regs();
-    se_ll_t in_ll;
-    se_ll_t out_ll;
-
-    ll_init(&in_ll, (void *)src, src_size);
-    ll_init(&out_ll, dst, dst_size);
-
-    /* Set the LLs. */
-    se->SE_IN_LL_ADDR = (uint32_t)(&in_ll);
-    se->SE_OUT_LL_ADDR = (uint32_t) (&out_ll);
-
-    /* Set registers for operation. */
-    se->SE_ERR_STATUS = se->SE_ERR_STATUS;
-    se->SE_INT_STATUS = se->SE_INT_STATUS;
-    se->SE_OPERATION = op;
-
-    while (!(se->SE_INT_STATUS & 0x10)) { /* Wait a while */ }
-    se_check_for_error();
-}
-
-/* Secure AES Functionality. */
-void se_perform_aes_block_operation(void *dst, size_t dst_size, const void *src, size_t src_size) {
-    uint8_t block[0x10] = {0};
-
-    if (src_size > sizeof(block) || dst_size > sizeof(block)) {
-        reboot();
-    }
-
-    /* Load src data into block. */
-    if (src_size != 0) {
-        memcpy(block, src, src_size);
-    }
-
-    /* Trigger AES operation. */
-    se_get_regs()->SE_CRYPTO_LAST_BLOCK = 0;
-    trigger_se_blocking_op(OP_START, block, sizeof(block), block, sizeof(block));
-
-    /* Copy output data into dst. */
-    if (dst_size != 0) {
-        memcpy(dst, block, dst_size);
-    }
-}
-
-void se_aes_ecb_encrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size, unsigned int config_high) {
-    volatile tegra_se_t *se = se_get_regs();
-    
-    if (keyslot >= KEYSLOT_AES_MAX || dst_size != 0x10 || src_size != 0x10) {
-        reboot();
-    }
-
-    /* Set configuration high (256-bit vs 128-bit) based on parameter. */
-    se->SE_CONFIG = (ALG_AES_ENC | DST_MEMORY) | (config_high << 16);
-    se->SE_CRYPTO_CONFIG = keyslot << 24 | 0x100;
-    se_perform_aes_block_operation(dst, 0x10, src, 0x10);
-}
-
-void se_aes_ecb_decrypt_block(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) {
-    volatile tegra_se_t *se = se_get_regs();
-    
-    if (keyslot >= KEYSLOT_AES_MAX || dst_size != 0x10 || src_size != 0x10) {
-        reboot();
-    }
-
-    se->SE_CONFIG = (ALG_AES_DEC | DST_MEMORY);
-    se->SE_CRYPTO_CONFIG = keyslot << 24;
-    se_perform_aes_block_operation(dst, 0x10, src, 0x10);
-}
-
-void shift_left_xor_rb(uint8_t *key) {
-    uint8_t prev_high_bit = 0;
-    for (unsigned int i = 0; i < 0x10; i++) {
-        uint8_t cur_byte = key[0xF - i];
-        key[0xF - i] = (cur_byte << 1) | (prev_high_bit);
-        prev_high_bit = cur_byte >> 7;
-    }
-    if (prev_high_bit) {
-        key[0xF] ^= 0x87;
-    }
-}
-
-void se_compute_aes_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size, unsigned int config_high) {
-    volatile tegra_se_t *se = se_get_regs();
-    
-    if (keyslot >= KEYSLOT_AES_MAX) {
-        reboot();
-    }
-
-    /* Generate the derived key, to be XOR'd with final output block. */
-    uint8_t ALIGN(16) derived_key[0x10] = {0};
-    se_aes_ecb_encrypt_block(keyslot, derived_key, sizeof(derived_key), derived_key, sizeof(derived_key), config_high);
-    shift_left_xor_rb(derived_key);
-    if (data_size & 0xF) {
-        shift_left_xor_rb(derived_key);
-    }
-
-    se->SE_CONFIG = (ALG_AES_ENC | DST_HASHREG) | (config_high << 16);
-    se->SE_CRYPTO_CONFIG = (keyslot << 24) | (0x145);
-    clear_aes_keyslot_iv(keyslot);
-
-    unsigned int num_blocks = (data_size + 0xF) >> 4;
-    /* Handle aligned blocks. */
-    if (num_blocks > 1) {
-        se->SE_CRYPTO_LAST_BLOCK = num_blocks - 2;
-        trigger_se_blocking_op(OP_START, NULL, 0, data, data_size);
-        se->SE_CRYPTO_CONFIG |= 0x80;
-    }
-
-    /* Create final block. */
-    uint8_t ALIGN(16) last_block[0x10] = {0};
-    if (data_size & 0xF) {
-        memcpy(last_block, data + (data_size & ~0xF), data_size & 0xF);
-        last_block[data_size & 0xF] = 0x80; /* Last block = data || 100...0 */
-    } else if (data_size >= 0x10) {
-        memcpy(last_block, data + data_size - 0x10, 0x10);
-    }
-
-    for (unsigned int i = 0; i < 0x10; i++) {
-        last_block[i] ^= derived_key[i];
-    }
-
-    /* Perform last operation. */
-    se->SE_CRYPTO_LAST_BLOCK = 0;
-    trigger_se_blocking_op(OP_START, NULL, 0, last_block, sizeof(last_block));
-
-    /* Copy output CMAC. */
-    for (unsigned int i = 0; i < (cmac_size >> 2); i++) {
-        ((uint32_t *)cmac)[i] = ((volatile uint32_t *)se->SE_HASH_RESULT)[i];
-    }
-}
-
-void se_compute_aes_256_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size) {
-    se_compute_aes_cmac(keyslot, cmac, cmac_size, data, data_size, 0x202);
-}
-
-void se_aes_256_cbc_decrypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size) {
-    volatile tegra_se_t *se = se_get_regs();
-    
-    if (keyslot >= KEYSLOT_AES_MAX || src_size < 0x10) {
-        reboot();
-    }
-
-    se->SE_CONFIG = (ALG_AES_DEC | DST_MEMORY) | (0x202 << 16);
-    se->SE_CRYPTO_CONFIG = (keyslot << 24) | 0x66;
-    clear_aes_keyslot_iv(keyslot);
-    se->SE_CRYPTO_LAST_BLOCK = (src_size >> 4) - 1;
-    trigger_se_blocking_op(OP_START, dst, dst_size, src, src_size);
-}

exosphere/lp0fw/src/se.h

@@ -1,176 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef EXOSPHERE_WARMBOOT_BIN_SE_H
-#define EXOSPHERE_WARMBOOT_BIN_SE_H
-
-#define SE_BASE 0x70012000
-#define MAKE_SE_REG(n) MAKE_REG32(SE_BASE + n)
-
-#define KEYSLOT_SWITCH_LP0TZRAMKEY 0x2
-#define KEYSLOT_SWITCH_SRKGENKEY 0x8
-#define KEYSLOT_SWITCH_PACKAGE2KEY 0x8
-#define KEYSLOT_SWITCH_TEMPKEY 0x9
-#define KEYSLOT_SWITCH_SESSIONKEY 0xA
-#define KEYSLOT_SWITCH_RNGKEY 0xB
-#define KEYSLOT_SWITCH_MASTERKEY 0xC
-#define KEYSLOT_SWITCH_DEVICEKEY 0xD
-
-/* This keyslot was added in 4.0.0. */
-#define KEYSLOT_SWITCH_4XNEWDEVICEKEYGENKEY 0xD
-#define KEYSLOT_SWITCH_4XNEWCONSOLEKEYGENKEY 0xE
-#define KEYSLOT_SWITCH_4XOLDDEVICEKEY 0xF
-
-/* This keyslot was added in 5.0.0. */
-#define KEYSLOT_SWITCH_5XNEWDEVICEKEYGENKEY 0xA
-
-#define KEYSLOT_AES_MAX 0x10
-#define KEYSLOT_RSA_MAX 0x2
-
-#define KEYSIZE_AES_MAX 0x20
-#define KEYSIZE_RSA_MAX 0x100
-
-#define ALG_SHIFT (12)
-#define ALG_DEC_SHIFT (8)
-#define ALG_NOP (0 << ALG_SHIFT)
-#define ALG_AES_ENC (1 << ALG_SHIFT)
-#define ALG_AES_DEC ((1 << ALG_DEC_SHIFT) | ALG_NOP)
-#define ALG_RNG (2 << ALG_SHIFT)
-#define ALG_SHA (3 << ALG_SHIFT)
-#define ALG_RSA (4 << ALG_SHIFT)
-
-#define DST_SHIFT (2)
-#define DST_MEMORY (0 << DST_SHIFT)
-#define DST_HASHREG (1 << DST_SHIFT)
-#define DST_KEYTAB (2 << DST_SHIFT)
-#define DST_SRK (3 << DST_SHIFT)
-#define DST_RSAREG (4 << DST_SHIFT)
-
-#define ENCMODE_SHIFT (24)
-#define DECMODE_SHIFT (16)
-#define ENCMODE_SHA256 (5 << ENCMODE_SHIFT)
-
-#define HASH_DISABLE (0x0)
-#define HASH_ENABLE (0x1)
-
-#define OP_ABORT 0
-#define OP_START 1
-#define OP_RESTART 2
-#define OP_CTX_SAVE 3
-#define OP_RESTART_IN 4
-
-#define CTX_SAVE_SRC_SHIFT 29
-#define CTX_SAVE_SRC_STICKY_BITS (0 << CTX_SAVE_SRC_SHIFT)
-#define CTX_SAVE_SRC_KEYTABLE_AES (2 << CTX_SAVE_SRC_SHIFT)
-#define CTX_SAVE_SRC_KEYTABLE_RSA (1 << CTX_SAVE_SRC_SHIFT)
-#define CTX_SAVE_SRC_MEM (4 << CTX_SAVE_SRC_SHIFT)
-#define CTX_SAVE_SRC_SRK (6 << CTX_SAVE_SRC_SHIFT)
-
-#define CTX_SAVE_KEY_LOW_BITS 0
-#define CTX_SAVE_KEY_HIGH_BITS 1
-#define CTX_SAVE_KEY_ORIGINAL_IV 2
-#define CTX_SAVE_KEY_UPDATED_IV 3
-
-#define CTX_SAVE_STICKY_BIT_INDEX_SHIFT 24
-#define CTX_SAVE_KEY_INDEX_SHIFT 8
-#define CTX_SAVE_RSA_KEY_INDEX_SHIFT 16
-#define CTX_SAVE_RSA_KEY_BLOCK_INDEX_SHIFT 12
-
-#define RSA_2048_BYTES 0x100
-
-typedef struct {
-    uint32_t SE_SE_SECURITY;
-    uint32_t SE_TZRAM_SECURITY;
-    uint32_t SE_OPERATION;
-    uint32_t SE_INT_ENABLE;
-    uint32_t SE_INT_STATUS;
-    uint32_t SE_CONFIG;
-    uint32_t SE_IN_LL_ADDR;
-    uint32_t SE_IN_CUR_BYTE_ADDR;
-    uint32_t SE_IN_CUR_LL_ID;
-    uint32_t SE_OUT_LL_ADDR;
-    uint32_t SE_OUT_CUR_BYTE_ADDR;
-    uint32_t SE_OUT_CUR_LL_ID;
-    uint32_t SE_HASH_RESULT[0x10];
-    uint32_t SE_CTX_SAVE_CONFIG;
-    uint32_t _0x74[0x63];
-    uint32_t SE_SHA_CONFIG;
-    uint32_t SE_SHA_MSG_LENGTH[0x4];
-    uint32_t SE_SHA_MSG_LEFT[0x4];
-    uint32_t _0x224[0x17];
-    uint32_t SE_CRYPTO_SECURITY_PERKEY;
-    uint32_t SE_CRYPTO_KEYTABLE_ACCESS[0x10];
-    uint32_t _0x2C4[0x10];
-    uint32_t SE_CRYPTO_CONFIG;
-    uint32_t SE_CRYPTO_LINEAR_CTR[0x4];
-    uint32_t SE_CRYPTO_LAST_BLOCK;
-    uint32_t SE_CRYPTO_KEYTABLE_ADDR;
-    uint32_t SE_CRYPTO_KEYTABLE_DATA;
-    uint32_t _0x324[0x3];
-    uint32_t SE_CRYPTO_KEYTABLE_DST;
-    uint32_t _0x334[0x3];
-    uint32_t SE_RNG_CONFIG;
-    uint32_t SE_RNG_SRC_CONFIG;
-    uint32_t SE_RNG_RESEED_INTERVAL;
-    uint32_t _0x34C[0x2D];
-    uint32_t SE_RSA_CONFIG;
-    uint32_t SE_RSA_KEY_SIZE;
-    uint32_t SE_RSA_EXP_SIZE;
-    uint32_t SE_RSA_SECURITY_PERKEY;
-    uint32_t SE_RSA_KEYTABLE_ACCESS[0x2];
-    uint32_t _0x418[0x2];
-    uint32_t SE_RSA_KEYTABLE_ADDR;
-    uint32_t SE_RSA_KEYTABLE_DATA;
-    uint32_t SE_RSA_OUTPUT[0x40];
-    uint32_t _0x528[0xB6];
-    uint32_t SE_STATUS;
-    uint32_t SE_ERR_STATUS;
-    uint32_t SE_MISC;
-    uint32_t SE_SPARE;
-    uint32_t SE_ENTROPY_DEBUG_COUNTER;
-    uint32_t _0x814;
-    uint32_t _0x818;
-    uint32_t _0x81C;
-    uint32_t _0x820[0x5F8];
-} tegra_se_t;
-
-typedef struct {
-    uint32_t address;
-    uint32_t size;
-} se_addr_info_t;
-
-typedef struct {
-    uint32_t num_entries; /* Set to total entries - 1 */
-    se_addr_info_t addr_info; /* This should really be an array...but for our use case it works. */
-} se_ll_t;
-
-static inline volatile tegra_se_t *se_get_regs(void) {
-    return (volatile tegra_se_t *)SE_BASE;
-}
-
-void se_check_error_status_reg(void);
-void se_check_for_error(void);
-
-void se_verify_flags_cleared(void);
-
-void clear_aes_keyslot(unsigned int keyslot);
-void clear_rsa_keyslot(unsigned int keyslot);
-void clear_aes_keyslot_iv(unsigned int keyslot);
-
-void se_compute_aes_256_cmac(unsigned int keyslot, void *cmac, size_t cmac_size, const void *data, size_t data_size);
-void se_aes_256_cbc_decrypt(unsigned int keyslot, void *dst, size_t dst_size, const void *src, size_t src_size);
-
-#endif

exosphere/lp0fw/src/secmon.c

@@ -1,115 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <stdint.h>
-
-#include "utils.h"
-#include "lp0.h"
-#include "secmon.h"
-#include "se.h"
-#include "fuse.h"
-#include "pmc.h"
-
-/* "private" functions. */
-static bool secmon_should_clear_aes_keyslot(unsigned int keyslot);
-static void secmon_clear_unused_keyslots(void);
-static void secmon_decrypt_saved_image(void *dst, const void *src, size_t size);
-
-void secmon_restore_to_tzram(const uint32_t target_firmware) {
-    /* Newer warmboot binaries clear the untouched keyslots for safety. */
-    if (target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_5_0_0) {
-        secmon_clear_unused_keyslots();
-    }
-
-    /* Decrypt Secure Monitor from DRAM into TZRAM. */
-    void *tzram_src = (void *)(0x80010000);
-    void *tzram_dst = (void *)(target_firmware >= ATMOSPHERE_TARGET_FIRMWARE_5_0_0 ? 0x7C012000 : 0x7C010000);
-    const size_t tzram_size = 0xE000;
-    secmon_decrypt_saved_image(tzram_dst, tzram_src, tzram_size);
-
-    /* Nintendo clears DRAM, but I'm not sure why, given they lock out BPMP access to DRAM. */
-    for (size_t i = 0; i < tzram_size/sizeof(uint32_t); i++) {
-        ((volatile uint32_t *)tzram_src)[i] = 0;
-    }
-
-    /* Make security engine require secure busmaster. */
-    se_get_regs()->SE_TZRAM_SECURITY = 0;
-
-    /* TODO: se_verify_keys_unreadable(); */
-
-    /* TODO: pmc_lockout_wb_scratch_registers(); */
-
-    /* Disable fuse programming. */
-    fuse_disable_programming();
-}
-
-void secmon_decrypt_saved_image(void *dst, const void *src, size_t size) {
-    /* First, AES-256-CBC decrypt the image into TZRAM. */
-    se_aes_256_cbc_decrypt(KEYSLOT_SWITCH_LP0TZRAMKEY, dst, size, src, size);
-
-    /* Next, calculate CMAC. */
-    uint32_t tzram_cmac[4] = {0, 0, 0, 0};
-    se_compute_aes_256_cmac(KEYSLOT_SWITCH_LP0TZRAMKEY, tzram_cmac, sizeof(tzram_cmac), dst, size);
-
-    /* Validate the MAC against saved one in PMC scratch. */
-    if (tzram_cmac[0] != APBDEV_PMC_SECURE_SCRATCH112_0 ||
-        tzram_cmac[1] != APBDEV_PMC_SECURE_SCRATCH113_0 ||
-        tzram_cmac[2] != APBDEV_PMC_SECURE_SCRATCH114_0 ||
-        tzram_cmac[3] != APBDEV_PMC_SECURE_SCRATCH115_0) {
-        reboot();
-    }
-
-    /* Clear the PMC scratch registers that hold the CMAC. */
-    APBDEV_PMC_SECURE_SCRATCH112_0 = 0;
-    APBDEV_PMC_SECURE_SCRATCH113_0 = 0;
-    APBDEV_PMC_SECURE_SCRATCH114_0 = 0;
-    APBDEV_PMC_SECURE_SCRATCH115_0 = 0;
-
-    /* Clear keyslot now that we're done with it. */
-    clear_aes_keyslot(KEYSLOT_SWITCH_LP0TZRAMKEY);
-}
-
-bool secmon_should_clear_aes_keyslot(unsigned int keyslot) {
-    /* We'll just compare keyslot against a hardcoded list of keys. */
-    static const uint8_t saved_keyslots[6] = {
-        KEYSLOT_SWITCH_LP0TZRAMKEY,
-        KEYSLOT_SWITCH_SESSIONKEY,
-        KEYSLOT_SWITCH_RNGKEY,
-        KEYSLOT_SWITCH_MASTERKEY,
-        KEYSLOT_SWITCH_DEVICEKEY,
-        KEYSLOT_SWITCH_4XOLDDEVICEKEY
-    };
-
-    for (unsigned int i = 0; i < sizeof(saved_keyslots)/sizeof(saved_keyslots[0]); i++) {
-        if (keyslot == saved_keyslots[i]) {
-            return false;
-        }
-    }
-    return true;
-}
-
-void secmon_clear_unused_keyslots(void) {
-    /* Clear unused keyslots. */
-    for (unsigned int i = 0; i < KEYSLOT_AES_MAX; i++) {
-        if (secmon_should_clear_aes_keyslot(i)) {
-            clear_aes_keyslot(i);
-        }
-        clear_aes_keyslot_iv(i);
-    }
-    for (unsigned int i = 0; i < KEYSLOT_RSA_MAX; i++) {
-        clear_rsa_keyslot(i);
-    }
-}

exosphere/lp0fw/src/sysreg.h

@@ -1,46 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef EXOSPHERE_WARMBOOT_BIN_SYSREG_H
-#define EXOSPHERE_WARMBOOT_BIN_SYSREG_H
-
-#include <stdint.h>
-
-
-#define SYSREG_BASE  (0x6000C000)
-
-#define SB_BASE (SYSREG_BASE + 0x200)
-
-#define MAKE_SYSREG(n) MAKE_REG32(SYSREG_BASE + n)
-#define MAKE_SB_REG(n) MAKE_REG32(SB_BASE + n)
-
-#define AHB_ARBITRATION_DISABLE_0 MAKE_SYSREG(0x004)
-
-#define SB_CSR_0 MAKE_SB_REG(0x00)
-#define SB_PIROM_START_0 MAKE_SB_REG(0x04)
-#define SB_PFCFG_0 MAKE_SB_REG(0x08)
-#define SB_SECURE_SPAREREG_0_0 MAKE_SB_REG(0x0C)
-#define SB_SECURE_SPAREREG_1_0 MAKE_SB_REG(0x10)
-#define SB_SECURE_SPAREREG_2_0 MAKE_SB_REG(0x14)
-#define SB_SECURE_SPAREREG_3_0 MAKE_SB_REG(0x18)
-#define SB_SECURE_SPAREREG_4_0 MAKE_SB_REG(0x1C)
-#define SB_SECURE_SPAREREG_5_0 MAKE_SB_REG(0x20)
-#define SB_SECURE_SPAREREG_6_0 MAKE_SB_REG(0x24)
-#define SB_SECURE_SPAREREG_7_0 MAKE_SB_REG(0x28)
-#define SB_AA64_RESET_LOW_0 MAKE_SB_REG(0x30)
-#define SB_AA64_RESET_HIGH_0 MAKE_SB_REG(0x34)
-
-#endif

exosphere/lp0fw/src/utils.h

@@ -1,39 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef EXOSPHERE_WARMBOOT_BIN_UTILS_H
-#define EXOSPHERE_WARMBOOT_BIN_UTILS_H
-
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <vapours/ams_version.h>
-
-#define BIT(n)      (1u   << (n))
-#define BITL(n)     (1ull << (n))
-#define MASK(n)     (BIT(n) - 1)
-#define MASKL(n)    (BITL(n) - 1)
-#define MASK2(a,b)  (MASK(a) & ~MASK(b))
-#define MASK2L(a,b) (MASKL(a) & ~MASKL(b))
-
-#define MAKE_REG32(a)   (*(volatile uint32_t *)(a))
-
-#define ALIGN(m)        __attribute__((aligned(m)))
-#define PACKED          __attribute__((packed))
-
-#define ALINLINE        __attribute__((always_inline))
-
-#endif

exosphere/program/Makefile

@@ -0,0 +1,124 @@
+#---------------------------------------------------------------------------------
+# Define the atmosphere board and cpu
+#---------------------------------------------------------------------------------
+export ATMOSPHERE_BOARD := nx-hac-001
+export ATMOSPHERE_CPU   := arm-cortex-a57
+
+#---------------------------------------------------------------------------------
+# pull in common atmosphere configuration
+#---------------------------------------------------------------------------------
+include  $(dir $(abspath $(lastword $(MAKEFILE_LIST))))/../../libraries/config/templates/exosphere.mk
+
+#---------------------------------------------------------------------------------
+# no real need to edit anything past this point unless you need to add additional
+# rules for different file extensions
+#---------------------------------------------------------------------------------
+ifneq ($(BUILD),$(notdir $(CURDIR)))
+#---------------------------------------------------------------------------------
+
+export OUTPUT	:=	$(CURDIR)/$(TARGET)
+export TOPDIR	:=	$(CURDIR)
+export DEPSDIR  :=  $(CURDIR)/$(BUILD)
+
+export VPATH	:=	$(foreach dir,$(SOURCES),$(CURDIR)/$(dir)) \
+			$(foreach dir,$(DATA),$(CURDIR)/$(dir)) \
+			$(TOPDIR)/sc7fw \
+			$(TOPDIR)/rebootstub
+
+CFILES      :=	$(call FIND_SOURCE_FILES,$(SOURCES),c)
+CPPFILES    :=	$(call FIND_SOURCE_FILES,$(SOURCES),cpp)
+SFILES      :=	$(call FIND_SOURCE_FILES,$(SOURCES),s)
+
+BINFILES    := sc7fw.bin rebootstub.bin
+
+#---------------------------------------------------------------------------------
+# use CXX for linking C++ projects, CC for standard C
+#---------------------------------------------------------------------------------
+ifeq ($(strip $(CPPFILES)),)
+#---------------------------------------------------------------------------------
+	export LD	:=	$(CC)
+#---------------------------------------------------------------------------------
+else
+#---------------------------------------------------------------------------------
+	export LD	:=	$(CXX)
+#---------------------------------------------------------------------------------
+endif
+#---------------------------------------------------------------------------------
+
+export OFILES_BIN	:=	$(addsuffix .o,$(BINFILES))
+export OFILES_SRC	:=	$(CPPFILES:.cpp=.o) $(CFILES:.c=.o) $(SFILES:.s=.o)
+export OFILES 	:=	$(OFILES_BIN) $(OFILES_SRC)
+export HFILES_BIN	:=	$(addsuffix .h,$(subst .,_,$(subst -,_,$(BINFILES))))
+
+export INCLUDE	:=	$(foreach dir,$(INCLUDES),-I$(CURDIR)/$(dir)) \
+			$(foreach dir,$(LIBDIRS),-I$(dir)/include) \
+			-I.
+
+export LIBPATHS	:=	$(foreach dir,$(LIBDIRS),-L$(dir)/lib -L$(dir)/$(ATMOSPHERE_LIBRARY_DIR))
+
+.PHONY: $(BUILD) clean all
+
+#---------------------------------------------------------------------------------
+all: $(BUILD) check_libexo
+
+$(BUILD): check_libexo check_firmwares
+	@[ -d $@ ] || mkdir -p $@
+	@$(MAKE) --no-print-directory -C $(BUILD) -f $(CURDIR)/Makefile
+
+check_libexo:
+	@$(MAKE) --no-print-directory -C ../../libraries/libexosphere arm64
+
+check_firmwares:
+	@$(MAKE) -C $(TOPDIR)/sc7fw all
+	@$(MAKE) -C $(TOPDIR)/rebootstub all
+
+#---------------------------------------------------------------------------------
+clean:
+	@echo clean ...
+	@$(MAKE) -C $(TOPDIR)/sc7fw clean
+	@$(MAKE) -C $(TOPDIR)/rebootstub clean
+	@rm -fr $(BUILD) $(OUTPUT).bin $(OUTPUT).elf *.lz4
+
+#---------------------------------------------------------------------------------
+else
+.PHONY:	all
+
+DEPENDS	:=	$(OFILES:.o=.d)
+
+#---------------------------------------------------------------------------------
+# main targets
+#---------------------------------------------------------------------------------
+all	:	$(OUTPUT).lz4
+
+$(OUTPUT).lz4	:	$(OUTPUT).bin
+	@python ../split_program.py $(OUTPUT).bin $(dir $(OUTPUT))
+	@echo built ... $(notdir $@)
+
+$(OUTPUT).bin	:	$(OUTPUT).elf
+	$(OBJCOPY) -S -O binary --set-section-flags .bss=alloc,load,contents $< $@
+	@echo built ... $(notdir $@)
+
+$(OUTPUT).elf	:	$(OFILES) ../../../libraries/libexosphere/$(ATMOSPHERE_LIBRARY_DIR)/libexosphere.a
+
+secmon_crt0_cpp.o secmon_make_page_table.o : CFLAGS += -fno-builtin
+
+%.elf:
+	@echo linking $(notdir $@)
+	$(LD) $(LDFLAGS) $(OFILES) $(LIBPATHS) $(LIBS) -o $@
+	@$(NM) -CSn $@ > $(notdir $*.lst)
+
+$(OFILES_SRC)	: $(HFILES_BIN)
+
+#---------------------------------------------------------------------------------
+# you need a rule like this for each extension you use as binary data
+#---------------------------------------------------------------------------------
+%.bin.o	%_bin.h:	%.bin
+#---------------------------------------------------------------------------------
+	@echo $(notdir $<)
+	@$(bin2o)
+
+-include $(DEPENDS)
+
+#---------------------------------------------------------------------------------------
+endif
+#---------------------------------------------------------------------------------------

exosphere/program/program.ld

@@ -0,0 +1,285 @@
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+
+MEMORY
+{
+    NULL           : ORIGIN = 0,           LENGTH = 4K
+    unused_region  : ORIGIN =      0x1000, LENGTH = 4K
+    iram_boot_code : ORIGIN = 0x040032000, LENGTH = 48K
+    tzram          : ORIGIN = 0x07C010000, LENGTH = 64K
+
+    /* Warmboot code follows the vectors in memory. */
+    /* However, we can't know for sure how big warmboot is, so we'll just say it's 2K. */
+    warmboot_text : ORIGIN = ORIGIN(tzram) + 10K, LENGTH = 2K
+
+    main       : ORIGIN = 0x1F00C0000, LENGTH = 48K
+    tzram_boot : ORIGIN = 0x1F01C0000, LENGTH = 8K
+
+    glob       : ORIGIN = 0x040032000, LENGTH = 64K
+}
+
+SECTIONS
+{
+	.metadata :
+	{
+        . = ALIGN(8);
+		KEEP (*(.metadata .metadata.*))
+		. = ALIGN(8);
+	} >unused_region AT>glob
+
+    PROVIDE(__glob_start__ = ORIGIN(glob));
+    . = __glob_start__;
+
+    __bootcode_start__ = ABSOLUTE(.);
+
+	.crt0 :
+	{
+		KEEP (*(.crt0 .crt0.*))
+        KEEP (secmon_crt0_cpp.o(.text*))
+        KEEP (secmon_make_page_table.o(.text*))
+		*(.crt0.rodata*)
+        secmon_crt0_cpp.o(.rodata*)
+        secmon_make_page_table.o(.rodata*)
+		*(.crt0.data*)
+        secmon_crt0_cpp.o(.data*)
+        secmon_make_page_table.o(.data*)
+		. = ALIGN(8);
+	} >iram_boot_code AT>glob
+
+	.preinit_array ALIGN(8) :
+	{
+		PROVIDE (__preinit_array_start = .);
+		KEEP (*(.preinit_array))
+		PROVIDE (__preinit_array_end = .);
+	} >iram_boot_code AT>glob
+
+	.init_array ALIGN(8) :
+	{
+		PROVIDE (__init_array_start = .);
+		KEEP (*(SORT(.init_array.*)))
+		KEEP (*(.init_array))
+		PROVIDE (__init_array_end = .);
+	} >iram_boot_code AT>glob
+
+	.fini_array ALIGN(8) :
+	{
+		PROVIDE (__fini_array_start = .);
+		KEEP (*(.fini_array))
+		KEEP (*(SORT(.fini_array.*)))
+		PROVIDE (__fini_array_end = .);
+	} >iram_boot_code AT>glob
+
+	.ctors ALIGN(8) :
+	{
+		KEEP (*crtbegin.o(.ctors)) /* MUST be first -- GCC requires it */
+		KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+		KEEP (*(SORT(.ctors.*)))
+		KEEP (*(.ctors))
+	} >iram_boot_code AT>glob
+
+	.dtors ALIGN(8) :
+	{
+		KEEP (*crtbegin.o(.dtors))
+		KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+		KEEP (*(SORT(.dtors.*)))
+		KEEP (*(.dtors))
+	} >iram_boot_code AT>glob
+
+    __bootcode_end__ = ABSOLUTE(.);
+
+    __program_start__ = ABSOLUTE(.);
+
+    .tzram_boot_volatile_data : {
+		KEEP (*(.volatile_keys .volatile_keys.*))
+    } >tzram_boot AT>glob
+
+    .tzram_boot_volatile_data.fill : {
+        FILL(0x00000000);
+        . = ORIGIN(tzram_boot) + 0x7FF;
+        BYTE(0x00);
+    } >tzram_boot AT>glob
+
+    .tzram_boot_code :
+    {
+        KEEP(secmon_main.o(.text*))
+        KEEP(secmon_boot_functions.o(.text*))
+        KEEP (secmon_boot_cache.o(.text*))
+        KEEP(secmon_boot_config.o(.text*))
+        KEEP(secmon_boot_setup.o(.text*))
+        KEEP(secmon_package2.o(.text*))
+        secmon_main.o(.rodata*)
+        secmon_boot_functions.o(.rodata*)
+        secmon_boot_cache.o(.rodata*)
+        secmon_boot_config.o(.rodata*)
+        secmon_boot_setup.o(.rodata*)
+        secmon_package2.o(.rodata*)
+        secmon_main.o(.data*)
+        secmon_boot_functions.o(.data*)
+        secmon_boot_cache.o(.data*)
+        secmon_boot_config.o(.data*)
+        secmon_boot_setup.o(.data*)
+        secmon_package2.o(.data*)
+        . = ALIGN(8);
+    } >tzram_boot AT>glob
+
+    .tzram_boot_code.bss :
+    {
+        __boot_bss_start__ = ABSOLUTE(.);
+        secmon_main.o(.bss* COMMON)
+        secmon_boot_functions.o(.bss* COMMON)
+        secmon_boot_cache.o(.bss* COMMON)
+        secmon_boot_config.o(.bss* COMMON)
+        secmon_boot_setup.o(.bss* COMMON)
+        secmon_package2.o(.bss* COMMON)
+        __boot_bss_end__ = ABSOLUTE(.);
+    } >tzram_boot AT>glob
+
+    .tzram_boot_code.fill :
+    {
+        FILL(0x00000000);
+        . = ORIGIN(tzram_boot) + LENGTH(tzram_boot) - 1;
+        BYTE(0x00);
+    } > tzram_boot AT>glob
+
+    .vectors :
+    {
+        KEEP (*(.vectors*))
+        . = ALIGN(0x100);
+    } >main AT>glob
+
+
+    .warmboot :
+    {
+        KEEP (*(.warmboot.text.start)) /* Should be first */
+        KEEP (*(.warmboot.text*))
+        KEEP(secmon_setup_warm.o(.text*))
+        KEEP(tsec_*.o(.text*))
+        KEEP (*(.warmboot.rodata*))
+        KEEP(secmon_setup_warm.o(.rodata*))
+        KEEP(tsec_*.o(.rodata*))
+        KEEP (*(.warmboot.data*))
+        KEEP(secmon_setup_warm.o(.data*))
+        KEEP(tsec_*.o(.data*))
+    } >warmboot_text AT>glob
+
+	.text ORIGIN(main) + SIZEOF(.vectors) + SIZEOF(.warmboot) :
+	{
+		*(.text.unlikely .text.*_unlikely .text.unlikely.*)
+		*(.text.exit .text.exit.*)
+		*(.text.startup .text.startup.*)
+		*(.text.hot .text.hot.*)
+		*(.text .stub .text.* .gnu.linkonce.t.*)
+		. = ALIGN(8);
+	} >main AT>glob
+
+	.init :
+	{
+		KEEP( *(.init) )
+		. = ALIGN(8);
+	} >main AT>glob
+
+	.plt :
+	{
+		*(.plt)
+		*(.iplt)
+		. = ALIGN(8);
+	} >main AT>glob
+
+	.fini :
+	{
+		KEEP( *(.fini) )
+		. = ALIGN(8);
+	} >main AT>glob
+
+
+	/* =========== RODATA section =========== */
+	. = ALIGN(8);
+	__rodata_start = . ;
+
+	.rodata :
+	{
+		*(.rodata .rodata.* .gnu.linkonce.r.*)
+		. = ALIGN(8);
+	} >main AT>glob
+
+	.eh_frame_hdr     : { __eh_frame_hdr_start = .; *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) __eh_frame_hdr_end = .; } >main AT>glob
+	.eh_frame         : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } >main AT>glob
+	.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } >main AT>glob
+	.gnu_extab        : ONLY_IF_RO { *(.gnu_extab*) } >main AT>glob
+
+	.hash              : { *(.hash) } >main AT>glob
+
+	/* =========== DATA section =========== */
+	. = ALIGN(8);
+	__data_start = . ;
+
+	.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) } >main AT>glob
+	.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } >main AT>glob
+	.gnu_extab : ONLY_IF_RW { *(.gnu_extab*) } >main AT>glob
+	.exception_ranges : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) } >main AT>glob
+
+	__got_start__ = .;
+
+	.got            : { *(.got) *(.igot) } >main AT>glob
+	.got.plt        : { *(.got.plt)  *(.igot.plt) } >main AT>glob
+
+	__got_end__ = .;
+
+	.data ALIGN(8) :
+	{
+		*(.data .data.* .gnu.linkonce.d.*)
+		SORT(CONSTRUCTORS)
+	} >main AT>glob
+
+	.bss ALIGN(8) (NOLOAD) :
+	{
+        __bss_start__ = ABSOLUTE(.);
+		*(.dynbss)
+		*(.bss .bss.* .gnu.linkonce.b.*)
+		*(COMMON)
+		. = ALIGN(16);
+        __bss_end__ = ABSOLUTE(.);
+	} >main AT>glob
+
+    __program_end__ = ABSOLUTE(.);
+
+	/* ==================
+	   ==== Metadata ====
+	   ================== */
+
+	/* Discard sections that difficult post-processing */
+	/DISCARD/ : { *(.group .comment .note .interp) }
+
+	/* Stabs debugging sections. */
+	.stab          0 : { *(.stab) }
+	.stabstr       0 : { *(.stabstr) }
+	.stab.excl     0 : { *(.stab.excl) }
+	.stab.exclstr  0 : { *(.stab.exclstr) }
+	.stab.index    0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+
+	/* DWARF debug sections.
+	   Symbols in the DWARF debugging sections are relative to the beginning
+	   of the section so we begin them at 0. */
+
+	/* DWARF 1 */
+	.debug          0 : { *(.debug) }
+	.line           0 : { *(.line) }
+
+	/* GNU DWARF 1 extensions */
+	.debug_srcinfo  0 : { *(.debug_srcinfo) }
+	.debug_sfnames  0 : { *(.debug_sfnames) }
+
+	/* DWARF 1.1 and DWARF 2 */
+	.debug_aranges  0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+
+	/* DWARF 2 */
+	.debug_info     0 : { *(.debug_info) }
+	.debug_abbrev   0 : { *(.debug_abbrev) }
+	.debug_line     0 : { *(.debug_line) }
+	.debug_frame    0 : { *(.debug_frame) }
+	.debug_str      0 : { *(.debug_str) }
+	.debug_loc      0 : { *(.debug_loc) }
+	.debug_macinfo  0 : { *(.debug_macinfo) }
+}

exosphere/program/program.specs

@@ -0,0 +1,4 @@
+%rename link old_link
+
+*link:
+%(old_link) -T %:getenv(TOPDIR /program.ld) --gc-sections --nmagic -nostdlib -nostartfiles

exosphere/program/rebootstub/Makefile

@@ -1,59 +1,13 @@
 #---------------------------------------------------------------------------------
-.SUFFIXES:
+# Define the atmosphere board and cpu
 #---------------------------------------------------------------------------------
-
-ifeq ($(strip $(DEVKITARM)),)
-$(error "Please set DEVKITARM in your environment. export DEVKITARM=<path to>devkitARM")
-endif
-
-TOPDIR ?= $(CURDIR)
-include $(DEVKITARM)/base_rules
+export ATMOSPHERE_BOARD := nx-hac-001
+export ATMOSPHERE_CPU   := arm7tdmi
 
 #---------------------------------------------------------------------------------
-# TARGET is the name of the output
-# BUILD is the directory where object files & intermediate files will be placed
-# SOURCES is a list of directories containing source code
-# DATA is a list of directories containing data files
-# INCLUDES is a list of directories containing header files
+# pull in common atmosphere configuration
 #---------------------------------------------------------------------------------
-TARGET		:=	$(notdir $(CURDIR))
-BUILD		:=	build
-SOURCES		:=	src
-DATA		:=	data
-INCLUDES	:=	include ../../libraries/libvapours/include
-
-#---------------------------------------------------------------------------------
-# options for code generation
-#---------------------------------------------------------------------------------
-ARCH	:=	-march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork
-
-CFLAGS	:= \
-		-g \
-		-Os \
-		-ffunction-sections \
-		-fdata-sections \
-		-fomit-frame-pointer \
-		-fno-inline \
-		-std=gnu11 \
-		-Werror \
-		-Wall \
-		$(ARCH) $(DEFINES)
-
-CFLAGS	+=	$(INCLUDE) -D__BPMP__
-
-CXXFLAGS	:= $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11
-
-ASFLAGS	:=	-g $(ARCH)
-LDFLAGS	=	-specs=$(TOPDIR)/linker.specs -g $(ARCH) -Wl,-Map,$(notdir $*.map)
-
-LIBS	:=
-
-#---------------------------------------------------------------------------------
-# list of directories containing libraries, this must be the top level containing
-# include and lib
-#---------------------------------------------------------------------------------
-LIBDIRS	:=
-
+include  $(dir $(abspath $(lastword $(MAKEFILE_LIST))))/../../../libraries/config/templates/exosphere.mk
 
 #---------------------------------------------------------------------------------
 # no real need to edit anything past this point unless you need to add additional
@@ -64,16 +18,14 @@ ifneq ($(BUILD),$(notdir $(CURDIR)))
 
 export OUTPUT	:=	$(CURDIR)/$(TARGET)
 export TOPDIR	:=	$(CURDIR)
+export DEPSDIR  :=  $(CURDIR)/$(BUILD)
 
 export VPATH	:=	$(foreach dir,$(SOURCES),$(CURDIR)/$(dir)) \
 			$(foreach dir,$(DATA),$(CURDIR)/$(dir))
 
-export DEPSDIR	:=	$(CURDIR)/$(BUILD)
-
-CFILES		:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.c)))
-CPPFILES	:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.cpp)))
-SFILES		:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.s)))
-BINFILES	:=	$(foreach dir,$(DATA),$(notdir $(wildcard $(dir)/*.*)))
+CFILES      :=	$(call FIND_SOURCE_FILES,$(SOURCES),c)
+CPPFILES    :=	$(call FIND_SOURCE_FILES,$(SOURCES),cpp)
+SFILES      :=	$(call FIND_SOURCE_FILES,$(SOURCES),s)
 
 #---------------------------------------------------------------------------------
 # use CXX for linking C++ projects, CC for standard C
@@ -91,29 +43,31 @@ endif
 
 export OFILES_BIN	:=	$(addsuffix .o,$(BINFILES))
 export OFILES_SRC	:=	$(CPPFILES:.cpp=.o) $(CFILES:.c=.o) $(SFILES:.s=.o)
-export OFILES 		:=	$(OFILES_BIN) $(OFILES_SRC)
-export HFILES_BIN	:=	$(addsuffix .h,$(subst .,_,$(BINFILES)))
+export OFILES 	:=	$(OFILES_BIN) $(OFILES_SRC)
+export HFILES_BIN	:=	$(addsuffix .h,$(subst .,_,$(subst -,_,$(BINFILES))))
 
 export INCLUDE	:=	$(foreach dir,$(INCLUDES),-I$(CURDIR)/$(dir)) \
 			$(foreach dir,$(LIBDIRS),-I$(dir)/include) \
-			-I$(CURDIR)/$(BUILD)
+			-I.
 
-export LIBPATHS	:=	$(foreach dir,$(LIBDIRS),-L$(dir)/lib)
+export LIBPATHS	:=	$(foreach dir,$(LIBDIRS),-L$(dir)/lib -L$(dir)/$(ATMOSPHERE_LIBRARY_DIR))
 
 .PHONY: $(BUILD) clean all
 
 #---------------------------------------------------------------------------------
-all: $(BUILD)
+all: $(BUILD) check_libexo
 
-$(BUILD):
+$(BUILD): check_libexo
 	@[ -d $@ ] || mkdir -p $@
 	@$(MAKE) --no-print-directory -C $(BUILD) -f $(CURDIR)/Makefile
 
+check_libexo:
+	@$(MAKE) --no-print-directory -C ../../../libraries/libexosphere arm
+
 #---------------------------------------------------------------------------------
 clean:
 	@echo clean ...
-	@rm -fr $(BUILD) $(TARGET).bin $(TARGET).elf
-
+	@rm -fr $(BUILD) $(OUTPUT).bin $(OUTPUT).elf *.lz4
 
 #---------------------------------------------------------------------------------
 else
@@ -127,14 +81,14 @@ DEPENDS	:=	$(OFILES:.o=.d)
 all	:	$(OUTPUT).bin
 
 $(OUTPUT).bin	:	$(OUTPUT).elf
-	$(OBJCOPY) -S -O binary $< $@
+	$(OBJCOPY) -S -O binary --set-section-flags .bss=alloc,load,contents $< $@
 	@echo built ... $(notdir $@)
 
-$(OUTPUT).elf	:	$(OFILES)
+$(OUTPUT).elf	:	$(OFILES) ../../../../libraries/libexosphere/$(ATMOSPHERE_LIBRARY_DIR)/libexosphere.a
 
-%.elf: $(OFILES)
+%.elf:
 	@echo linking $(notdir $@)
-	@$(LD) $(LDFLAGS) $(OFILES) $(LIBPATHS) $(LIBS) -o $@
+	$(LD) $(LDFLAGS) $(OFILES) $(LIBPATHS) $(LIBS) -o $@
 	@$(NM) -CSn $@ > $(notdir $*.lst)
 
 $(OFILES_SRC)	: $(HFILES_BIN)
@@ -142,7 +96,7 @@ $(OFILES_SRC)	: $(HFILES_BIN)
 #---------------------------------------------------------------------------------
 # you need a rule like this for each extension you use as binary data
 #---------------------------------------------------------------------------------
-%.bin.o	:	%.bin
+%.bin.o	%_bin.h:	%.bin
 #---------------------------------------------------------------------------------
 	@echo $(notdir $<)
 	@$(bin2o)

exosphere/program/rebootstub/rebootstub.ld

@@ -0,0 +1,183 @@
+OUTPUT_ARCH(arm)
+ENTRY(reset)
+
+MEMORY
+{
+    NULL   : ORIGIN = 0,          LENGTH = 4K
+    rebootstub  : ORIGIN = 0x4003F000, LENGTH = 4K
+}
+
+
+SECTIONS
+{
+	/* =========== CODE section =========== */
+	PROVIDE(__start__ = ORIGIN(rebootstub));
+	. = __start__;
+	__code_start = . ;
+
+	.vectors :
+	{
+		KEEP (*(.vectors .vectors.*))
+		. = ALIGN(8);
+	} >rebootstub
+
+	.text :
+	{
+		*(.text.unlikely .text.*_unlikely .text.unlikely.*)
+		*(.text.exit .text.exit.*)
+		*(.text.startup .text.startup.*)
+		*(.text.hot .text.hot.*)
+		*(.text .stub .text.* .gnu.linkonce.t.*)
+		. = ALIGN(8);
+	} >rebootstub
+
+	.init :
+	{
+		KEEP( *(.init) )
+		. = ALIGN(8);
+	} >rebootstub
+
+	.plt :
+	{
+		*(.plt)
+		*(.iplt)
+		. = ALIGN(8);
+	} >rebootstub
+
+	.fini :
+	{
+		KEEP( *(.fini) )
+		. = ALIGN(8);
+	} >rebootstub
+
+
+	/* =========== RODATA section =========== */
+	. = ALIGN(8);
+	__rodata_start = . ;
+
+	.rodata :
+	{
+		*(.rodata .rodata.* .gnu.linkonce.r.*)
+		. = ALIGN(8);
+	} >rebootstub
+
+	.eh_frame_hdr     : { __eh_frame_hdr_start = .; *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) __eh_frame_hdr_end = .; } >rebootstub
+	.eh_frame         : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } >rebootstub
+	.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } >rebootstub
+	.gnu_extab        : ONLY_IF_RO { *(.gnu_extab*) } >rebootstub
+
+	.hash              : { *(.hash) } >rebootstub
+
+	/* =========== DATA section =========== */
+	. = ALIGN(8);
+	__data_start = . ;
+
+	.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) } >rebootstub
+	.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } >rebootstub
+	.gnu_extab : ONLY_IF_RW { *(.gnu_extab*) } >rebootstub
+	.exception_ranges : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) } >rebootstub
+
+	.preinit_array ALIGN(8) :
+	{
+		PROVIDE (__preinit_array_start = .);
+		KEEP (*(.preinit_array))
+		PROVIDE (__preinit_array_end = .);
+	} >rebootstub
+
+	.init_array ALIGN(8) :
+	{
+		PROVIDE (__init_array_start = .);
+		KEEP (*(SORT(.init_array.*)))
+		KEEP (*(.init_array))
+		PROVIDE (__init_array_end = .);
+	} >rebootstub
+
+	.fini_array ALIGN(8) :
+	{
+		PROVIDE (__fini_array_start = .);
+		KEEP (*(.fini_array))
+		KEEP (*(SORT(.fini_array.*)))
+		PROVIDE (__fini_array_end = .);
+	} >rebootstub
+
+	.ctors ALIGN(8) :
+	{
+		KEEP (*crtbegin.o(.ctors)) /* MUST be first -- GCC requires it */
+		KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+		KEEP (*(SORT(.ctors.*)))
+		KEEP (*(.ctors))
+	} >rebootstub
+
+	.dtors ALIGN(8) :
+	{
+		KEEP (*crtbegin.o(.dtors))
+		KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+		KEEP (*(SORT(.dtors.*)))
+		KEEP (*(.dtors))
+	} >rebootstub
+
+	__got_start__ = .;
+
+	.got            : { *(.got) *(.igot) } >rebootstub
+	.got.plt        : { *(.got.plt)  *(.igot.plt) } >rebootstub
+
+	__got_end__ = .;
+
+	.data ALIGN(8) :
+	{
+		*(.data .data.* .gnu.linkonce.d.*)
+		SORT(CONSTRUCTORS)
+	} >rebootstub
+
+	__bss_start__ = .;
+	.bss ALIGN(8) :
+	{
+		*(.dynbss)
+		*(.bss .bss.* .gnu.linkonce.b.*)
+		*(COMMON)
+		. = ALIGN(16);
+	} >rebootstub
+	__bss_end__ = .;
+
+	__end__ = ABSOLUTE(.) ;
+
+	/* ==================
+	   ==== Metadata ====
+	   ================== */
+
+	/* Discard sections that difficult post-processing */
+	/DISCARD/ : { *(.group .comment .note .interp) }
+
+	/* Stabs debugging sections. */
+	.stab          0 : { *(.stab) }
+	.stabstr       0 : { *(.stabstr) }
+	.stab.excl     0 : { *(.stab.excl) }
+	.stab.exclstr  0 : { *(.stab.exclstr) }
+	.stab.index    0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+
+	/* DWARF debug sections.
+	   Symbols in the DWARF debugging sections are relative to the beginning
+	   of the section so we begin them at 0. */
+
+	/* DWARF 1 */
+	.debug          0 : { *(.debug) }
+	.line           0 : { *(.line) }
+
+	/* GNU DWARF 1 extensions */
+	.debug_srcinfo  0 : { *(.debug_srcinfo) }
+	.debug_sfnames  0 : { *(.debug_sfnames) }
+
+	/* DWARF 1.1 and DWARF 2 */
+	.debug_aranges  0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+
+	/* DWARF 2 */
+	.debug_info     0 : { *(.debug_info) }
+	.debug_abbrev   0 : { *(.debug_abbrev) }
+	.debug_line     0 : { *(.debug_line) }
+	.debug_frame    0 : { *(.debug_frame) }
+	.debug_str      0 : { *(.debug_str) }
+	.debug_loc      0 : { *(.debug_loc) }
+	.debug_macinfo  0 : { *(.debug_macinfo) }
+}

exosphere/program/rebootstub/rebootstub.specs

@@ -0,0 +1,7 @@
+%rename link old_link
+
+*link:
+%(old_link) -T %:getenv(TOPDIR /rebootstub.ld) --gc-sections --nmagic -nostdlib -nostartfiles
+
+*startfile:
+crti%O%s crtbegin%O%s

exosphere/program/rebootstub/source/rebootstub_exception_vectors.s

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+.section    .vectors, "ax", %progbits
+.align      3
+.global     reset
+reset:
+    b _ZN3ams10rebootstub4MainEv
+
+.global     _ZN3ams10rebootstub10RebootTypeE
+_ZN3ams10rebootstub10RebootTypeE:
+.word 0x00000001

exosphere/program/rebootstub/source/rebootstub_main.s

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+.section    .text._ZN3ams10rebootstub4MainEv, "ax", %progbits
+.align      3
+.global     _ZN3ams10rebootstub4MainEv
+_ZN3ams10rebootstub4MainEv:
+    /* Get the reboot type. */
+    ldr r0, =_ZN3ams10rebootstub10RebootTypeE
+    ldr r0, [r0]
+
+    /* If the reboot type is power off, perform a power off. */
+    cmp r0, #0
+    beq _ZN3ams10rebootstub8PowerOffEv
+
+    /* Otherwise, clear all registers jump to the reboot payload in iram. */
+    ldr r0, =0x52425430 /* RBT0 */
+    mov r1, #0
+    mov r2, #0
+    mov r3, #0
+    mov r4, #0
+    mov r5, #0
+    mov r5, #0
+    mov r6, #0
+    mov r7, #0
+    mov r8, #0
+    mov r9, #0
+    mov r10, #0
+    mov r11, #0
+    mov r12, #0
+    mov r9, #0
+    mov lr, #0
+    ldr sp, =0x40010000
+    ldr pc, =0x40010000
+
+    /* Infinite loop. */
+    1: b 1b

exosphere/program/rebootstub/source/rebootstub_power_off.cpp

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <exosphere.hpp>
+
+namespace ams::rebootstub {
+
+    NORETURN void Halt() {
+        while (true) {
+            reg::Write(secmon::MemoryRegionPhysicalDeviceFlowController.GetAddress() + FLOW_CTLR_HALT_COP_EVENTS, FLOW_REG_BITS_ENUM(HALT_COP_EVENTS_MODE, FLOW_MODE_STOP),
+                                                                                                                  FLOW_REG_BITS_ENUM(HALT_COP_EVENTS_JTAG,        ENABLED));
+        }
+
+        __builtin_unreachable();
+    }
+
+    NORETURN void PowerOff() {
+        /* Ensure that i2c5 is usable. */
+        clkrst::EnableI2c5Clock();
+
+        /* Initialize i2c5. */
+        i2c::Initialize(i2c::Port_5);
+
+        /* Stop rtc alarms. */
+        rtc::StopAlarm();
+
+        /* Perform a pmic power off. */
+        pmic::PowerOff();
+
+        /* Halt the bpmp. */
+        Halt();
+
+        /* This can never be reached. */
+        __builtin_unreachable();
+    }
+
+}
+
+namespace ams::diag {
+
+    void AbortImpl() {
+        /* Halt the bpmp. */
+        rebootstub::Halt();
+
+        /* This can never be reached. */
+        __builtin_unreachable();
+    }
+
+}

exosphere/program/sc7fw/Makefile

@@ -0,0 +1,108 @@
+#---------------------------------------------------------------------------------
+# Define the atmosphere board and cpu
+#---------------------------------------------------------------------------------
+export ATMOSPHERE_BOARD := nx-hac-001
+export ATMOSPHERE_CPU   := arm7tdmi
+
+#---------------------------------------------------------------------------------
+# pull in common atmosphere configuration
+#---------------------------------------------------------------------------------
+include  $(dir $(abspath $(lastword $(MAKEFILE_LIST))))/../../../libraries/config/templates/exosphere.mk
+
+#---------------------------------------------------------------------------------
+# no real need to edit anything past this point unless you need to add additional
+# rules for different file extensions
+#---------------------------------------------------------------------------------
+ifneq ($(BUILD),$(notdir $(CURDIR)))
+#---------------------------------------------------------------------------------
+
+export OUTPUT	:=	$(CURDIR)/$(TARGET)
+export TOPDIR	:=	$(CURDIR)
+export DEPSDIR  :=  $(CURDIR)/$(BUILD)
+
+export VPATH	:=	$(foreach dir,$(SOURCES),$(CURDIR)/$(dir)) \
+			$(foreach dir,$(DATA),$(CURDIR)/$(dir))
+
+CFILES      :=	$(call FIND_SOURCE_FILES,$(SOURCES),c)
+CPPFILES    :=	$(call FIND_SOURCE_FILES,$(SOURCES),cpp)
+SFILES      :=	$(call FIND_SOURCE_FILES,$(SOURCES),s)
+
+#---------------------------------------------------------------------------------
+# use CXX for linking C++ projects, CC for standard C
+#---------------------------------------------------------------------------------
+ifeq ($(strip $(CPPFILES)),)
+#---------------------------------------------------------------------------------
+	export LD	:=	$(CC)
+#---------------------------------------------------------------------------------
+else
+#---------------------------------------------------------------------------------
+	export LD	:=	$(CXX)
+#---------------------------------------------------------------------------------
+endif
+#---------------------------------------------------------------------------------
+
+export OFILES_BIN	:=	$(addsuffix .o,$(BINFILES))
+export OFILES_SRC	:=	$(CPPFILES:.cpp=.o) $(CFILES:.c=.o) $(SFILES:.s=.o)
+export OFILES 	:=	$(OFILES_BIN) $(OFILES_SRC)
+export HFILES_BIN	:=	$(addsuffix .h,$(subst .,_,$(subst -,_,$(BINFILES))))
+
+export INCLUDE	:=	$(foreach dir,$(INCLUDES),-I$(CURDIR)/$(dir)) \
+			$(foreach dir,$(LIBDIRS),-I$(dir)/include) \
+			-I.
+
+export LIBPATHS	:=	$(foreach dir,$(LIBDIRS),-L$(dir)/lib -L$(dir)/$(ATMOSPHERE_LIBRARY_DIR))
+
+.PHONY: $(BUILD) clean all
+
+#---------------------------------------------------------------------------------
+all: $(BUILD) check_libexo
+
+$(BUILD): check_libexo
+	@[ -d $@ ] || mkdir -p $@
+	@$(MAKE) --no-print-directory -C $(BUILD) -f $(CURDIR)/Makefile
+
+check_libexo:
+	@$(MAKE) --no-print-directory -C ../../../libraries/libexosphere arm
+
+#---------------------------------------------------------------------------------
+clean:
+	@echo clean ...
+	@rm -fr $(BUILD) $(OUTPUT).bin $(OUTPUT).elf *.lz4
+
+#---------------------------------------------------------------------------------
+else
+.PHONY:	all
+
+DEPENDS	:=	$(OFILES:.o=.d)
+
+#---------------------------------------------------------------------------------
+# main targets
+#---------------------------------------------------------------------------------
+all	:	$(OUTPUT).bin
+
+$(OUTPUT).bin	:	$(OUTPUT).elf
+	$(OBJCOPY) -S -O binary --set-section-flags .bss=alloc,load,contents $< $@
+	@echo built ... $(notdir $@)
+
+$(OUTPUT).elf	:	$(OFILES) ../../../../libraries/libexosphere/$(ATMOSPHERE_LIBRARY_DIR)/libexosphere.a
+
+%.elf:
+	@echo linking $(notdir $@)
+	$(LD) $(LDFLAGS) $(OFILES) $(LIBPATHS) $(LIBS) -o $@
+	@$(NM) -CSn $@ > $(notdir $*.lst)
+
+$(OFILES_SRC)	: $(HFILES_BIN)
+
+#---------------------------------------------------------------------------------
+# you need a rule like this for each extension you use as binary data
+#---------------------------------------------------------------------------------
+%.bin.o	%_bin.h:	%.bin
+#---------------------------------------------------------------------------------
+	@echo $(notdir $<)
+	@$(bin2o)
+
+-include $(DEPENDS)
+
+#---------------------------------------------------------------------------------------
+endif
+#---------------------------------------------------------------------------------------

exosphere/program/sc7fw/sc7fw.ld

@@ -0,0 +1,183 @@
+OUTPUT_ARCH(arm)
+ENTRY(reset)
+
+MEMORY
+{
+    NULL   : ORIGIN = 0,          LENGTH = 4K
+    sc7fw  : ORIGIN = 0x40003000, LENGTH = 4K
+}
+
+
+SECTIONS
+{
+	/* =========== CODE section =========== */
+	PROVIDE(__start__ = ORIGIN(sc7fw));
+	. = __start__;
+	__code_start = . ;
+
+	.vectors :
+	{
+		KEEP (*(.vectors .vectors.*))
+		. = ALIGN(8);
+	} >sc7fw
+
+	.text :
+	{
+		*(.text.unlikely .text.*_unlikely .text.unlikely.*)
+		*(.text.exit .text.exit.*)
+		*(.text.startup .text.startup.*)
+		*(.text.hot .text.hot.*)
+		*(.text .stub .text.* .gnu.linkonce.t.*)
+		. = ALIGN(8);
+	} >sc7fw
+
+	.init :
+	{
+		KEEP( *(.init) )
+		. = ALIGN(8);
+	} >sc7fw
+
+	.plt :
+	{
+		*(.plt)
+		*(.iplt)
+		. = ALIGN(8);
+	} >sc7fw
+
+	.fini :
+	{
+		KEEP( *(.fini) )
+		. = ALIGN(8);
+	} >sc7fw
+
+
+	/* =========== RODATA section =========== */
+	. = ALIGN(8);
+	__rodata_start = . ;
+
+	.rodata :
+	{
+		*(.rodata .rodata.* .gnu.linkonce.r.*)
+		. = ALIGN(8);
+	} >sc7fw
+
+	.eh_frame_hdr     : { __eh_frame_hdr_start = .; *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) __eh_frame_hdr_end = .; } >sc7fw
+	.eh_frame         : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } >sc7fw
+	.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } >sc7fw
+	.gnu_extab        : ONLY_IF_RO { *(.gnu_extab*) } >sc7fw
+
+	.hash              : { *(.hash) } >sc7fw
+
+	/* =========== DATA section =========== */
+	. = ALIGN(8);
+	__data_start = . ;
+
+	.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) } >sc7fw
+	.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } >sc7fw
+	.gnu_extab : ONLY_IF_RW { *(.gnu_extab*) } >sc7fw
+	.exception_ranges : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) } >sc7fw
+
+	.preinit_array ALIGN(8) :
+	{
+		PROVIDE (__preinit_array_start = .);
+		KEEP (*(.preinit_array))
+		PROVIDE (__preinit_array_end = .);
+	} >sc7fw
+
+	.init_array ALIGN(8) :
+	{
+		PROVIDE (__init_array_start = .);
+		KEEP (*(SORT(.init_array.*)))
+		KEEP (*(.init_array))
+		PROVIDE (__init_array_end = .);
+	} >sc7fw
+
+	.fini_array ALIGN(8) :
+	{
+		PROVIDE (__fini_array_start = .);
+		KEEP (*(.fini_array))
+		KEEP (*(SORT(.fini_array.*)))
+		PROVIDE (__fini_array_end = .);
+	} >sc7fw
+
+	.ctors ALIGN(8) :
+	{
+		KEEP (*crtbegin.o(.ctors)) /* MUST be first -- GCC requires it */
+		KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+		KEEP (*(SORT(.ctors.*)))
+		KEEP (*(.ctors))
+	} >sc7fw
+
+	.dtors ALIGN(8) :
+	{
+		KEEP (*crtbegin.o(.dtors))
+		KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+		KEEP (*(SORT(.dtors.*)))
+		KEEP (*(.dtors))
+	} >sc7fw
+
+	__got_start__ = .;
+
+	.got            : { *(.got) *(.igot) } >sc7fw
+	.got.plt        : { *(.got.plt)  *(.igot.plt) } >sc7fw
+
+	__got_end__ = .;
+
+	.data ALIGN(8) :
+	{
+		*(.data .data.* .gnu.linkonce.d.*)
+		SORT(CONSTRUCTORS)
+	} >sc7fw
+
+	__bss_start__ = .;
+	.bss ALIGN(8) :
+	{
+		*(.dynbss)
+		*(.bss .bss.* .gnu.linkonce.b.*)
+		*(COMMON)
+		. = ALIGN(16);
+	} >sc7fw
+	__bss_end__ = .;
+
+	__end__ = ABSOLUTE(.) ;
+
+	/* ==================
+	   ==== Metadata ====
+	   ================== */
+
+	/* Discard sections that difficult post-processing */
+	/DISCARD/ : { *(.group .comment .note .interp) }
+
+	/* Stabs debugging sections. */
+	.stab          0 : { *(.stab) }
+	.stabstr       0 : { *(.stabstr) }
+	.stab.excl     0 : { *(.stab.excl) }
+	.stab.exclstr  0 : { *(.stab.exclstr) }
+	.stab.index    0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+
+	/* DWARF debug sections.
+	   Symbols in the DWARF debugging sections are relative to the beginning
+	   of the section so we begin them at 0. */
+
+	/* DWARF 1 */
+	.debug          0 : { *(.debug) }
+	.line           0 : { *(.line) }
+
+	/* GNU DWARF 1 extensions */
+	.debug_srcinfo  0 : { *(.debug_srcinfo) }
+	.debug_sfnames  0 : { *(.debug_sfnames) }
+
+	/* DWARF 1.1 and DWARF 2 */
+	.debug_aranges  0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+
+	/* DWARF 2 */
+	.debug_info     0 : { *(.debug_info) }
+	.debug_abbrev   0 : { *(.debug_abbrev) }
+	.debug_line     0 : { *(.debug_line) }
+	.debug_frame    0 : { *(.debug_frame) }
+	.debug_str      0 : { *(.debug_str) }
+	.debug_loc      0 : { *(.debug_loc) }
+	.debug_macinfo  0 : { *(.debug_macinfo) }
+}

exosphere/program/sc7fw/sc7fw.specs

@@ -0,0 +1,7 @@
+%rename link old_link
+
+*link:
+%(old_link) -T %:getenv(TOPDIR /sc7fw.ld) --gc-sections --nmagic -nostdlib -nostartfiles
+
+*startfile:
+crti%O%s crtbegin%O%s

exosphere/program/sc7fw/source/sc7fw_dram.cpp

@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <exosphere.hpp>
+#include "sc7fw_util.hpp"
+#include "sc7fw_dram.hpp"
+
+namespace ams::sc7fw {
+
+    namespace {
+
+        constexpr inline const uintptr_t PMC = secmon::MemoryRegionPhysicalDevicePmc.GetAddress();
+
+        void UpdateEmcTiming() {
+            /* Enable timing update. */
+            reg::Write(EMC_ADDRESS(EMC_TIMING_CONTROL), EMC_REG_BITS_ENUM(TIMING_CONTROL_TIMING_UPDATE, ENABLED));
+
+            /* Wait for the timing update to complete. */
+            while (!reg::HasValue(EMC_ADDRESS(EMC_EMC_STATUS), EMC_REG_BITS_ENUM(EMC_STATUS_TIMING_UPDATE_STALLED, DONE))) {
+                /* ... */
+            }
+        }
+
+        void RequestAllPadsPowerDown(uintptr_t addr, uintptr_t expected) {
+            constexpr u32 DpdAllRequestValue = reg::Encode(PMC_REG_BITS_ENUM(IO_DPD_REQ_CODE, DPD_ON)) | 0x0FFFFFFF;
+            const auto RequestAddress = addr;
+            const auto StatusAddress  = addr + 4;
+
+            /* Request all pads enter power down. */
+            reg::Write(PMC + RequestAddress, DpdAllRequestValue);
+
+            /* Wait until the status reflects our expectation (and all pads are shut down). */
+            while (reg::Read(PMC + StatusAddress) != expected) { /* ... */ }
+
+            /* Wait a little while to allow the power down status to propagate. */
+            SpinLoop(0x20);
+        };
+
+    }
+
+    void SaveEmcFsp() {
+        /* We require that the RAM is LPDDR4. */
+        AMS_ABORT_UNLESS(reg::HasValue(EMC_ADDRESS(EMC_FBIO_CFG5), EMC_REG_BITS_ENUM(FBIO_CFG5_DRAM_TYPE, LPDDR4)));
+
+        /* Read the frequency set points from MRW3. */
+        constexpr u32 FspShift = 6;
+        constexpr u32 FspBits  = 2;
+        constexpr u32 FspMask  = ((1u << FspBits) - 1) << FspShift;
+        static_assert(FspMask == 0x000000C0);
+        const u32 fsp = (reg::Read(EMC_ADDRESS(EMC_MRW3)) & FspMask) >> FspShift;
+
+        /* Write the fsp to PMC_SCRATCH18, where it will be restored to MRW3 by brom. */
+        reg::ReadWrite(PMC + APBDEV_PMC_SCRATCH18, REG_BITS_VALUE(FspShift, FspBits, fsp));
+
+        /* Write the fsp twice to PMC_SCRATCH12, where it will be restored to MRW12 by brom. */
+        reg::ReadWrite(PMC + APBDEV_PMC_SCRATCH12, REG_BITS_VALUE(FspShift, FspBits, fsp), REG_BITS_VALUE(FspShift + 8, FspBits, fsp));
+
+        /* Write the fsp twice to PMC_SCRATCH13, where it will be restored to MRW13 by brom. */
+        reg::ReadWrite(PMC + APBDEV_PMC_SCRATCH13, REG_BITS_VALUE(FspShift, FspBits, fsp), REG_BITS_VALUE(FspShift + 8, FspBits, fsp));
+    }
+
+    void EnableSdramSelfRefresh() {
+        /* We require that the RAM is dual-channel. */
+        AMS_ABORT_UNLESS(reg::HasValue(EMC_ADDRESS(EMC_FBIO_CFG7), EMC_REG_BITS_ENUM(FBIO_CFG7_CH1_ENABLE, ENABLE)));
+
+        /* Disable RAM's ability to dynamically self-refresh, and to opportunistically perform powerdown. */
+        reg::Write(EMC_ADDRESS(EMC_CFG), EMC_REG_BITS_ENUM(CFG_DYN_SELF_REF,     DISABLED),
+                                         EMC_REG_BITS_ENUM(CFG_DRAM_ACPD,    NO_POWERDOWN));
+
+        /* Update the EMC timing. */
+        UpdateEmcTiming();
+
+        /* Wait five microseconds. */
+        util::WaitMicroSeconds(5);
+
+        /* Disable ZQ calibration. */
+        reg::Write(EMC_ADDRESS(EMC_ZCAL_INTERVAL), 0);
+
+        /* Disable automatic calibration. */
+        reg::Write(EMC_ADDRESS(EMC_AUTO_CAL_CONFIG), EMC_REG_BITS_ENUM(AUTO_CAL_CONFIG_AUTO_CAL_MEASURE_STALL,  ENABLE),
+                                                     EMC_REG_BITS_ENUM(AUTO_CAL_CONFIG_AUTO_CAL_UPDATE_STALL,   ENABLE),
+                                                     EMC_REG_BITS_ENUM(AUTO_CAL_CONFIG_AUTO_CAL_START,         DISABLE));
+
+        /* Get whether digital delay locked loops are enabled. */
+        const bool has_dll = reg::HasValue(EMC_ADDRESS(EMC_CFG_DIG_DLL), EMC_REG_BITS_ENUM(CFG_DIG_DLL_CFG_DLL_EN,  ENABLED));
+        if (has_dll) {
+            /* If they are, disable them. */
+            reg::ReadWrite(EMC_ADDRESS(EMC_CFG_DIG_DLL), EMC_REG_BITS_ENUM(CFG_DIG_DLL_CFG_DLL_EN,  DISABLED));
+        }
+
+        /* Update the EMC timing. */
+        UpdateEmcTiming();
+
+        /* If dll was enabled, wait until both EMC0 and EMC1 have dll disabled. */
+        if (has_dll) {
+            while (!reg::HasValue(EMC0_ADDRESS(EMC_CFG_DIG_DLL), EMC_REG_BITS_ENUM(CFG_DIG_DLL_CFG_DLL_EN, DISABLED))) { /* ... */ }
+            while (!reg::HasValue(EMC1_ADDRESS(EMC_CFG_DIG_DLL), EMC_REG_BITS_ENUM(CFG_DIG_DLL_CFG_DLL_EN, DISABLED))) { /* ... */ }
+        }
+
+        /* Stall all reads and writes. */
+        reg::Write(EMC_ADDRESS(EMC_REQ_CTRL), EMC_REG_BITS_VALUE(REQ_CTRL_STALL_ALL_READS,  1),
+                                              EMC_REG_BITS_VALUE(REQ_CTRL_STALL_ALL_WRITES, 1));
+
+        /* Wait until both EMC0 and EMC1 have no outstanding transactions. */
+        while (!reg::HasValue(EMC0_ADDRESS(EMC_EMC_STATUS), EMC_REG_BITS_ENUM(EMC_STATUS_NO_OUTSTANDING_TRANSACTIONS, COMPLETED))) { /* ... */ }
+        while (!reg::HasValue(EMC1_ADDRESS(EMC_EMC_STATUS), EMC_REG_BITS_ENUM(EMC_STATUS_NO_OUTSTANDING_TRANSACTIONS, COMPLETED))) { /* ... */ }
+
+        /* Enable self-refresh. */
+        reg::Write(EMC_ADDRESS(EMC_SELF_REF), EMC_REG_BITS_ENUM(SELF_REF_SREF_DEV_SELECTN,    BOTH),
+                                              EMC_REG_BITS_ENUM(SELF_REF_SELF_REF_CMD,     ENABLED));
+
+        /* Wait until both EMC and EMC1 are in self-refresh. */
+        const auto desired = reg::HasValue(EMC_ADDRESS(EMC_ADR_CFG), EMC_REG_BITS_ENUM(ADR_CFG_EMEM_NUMDEV, N2)) ? EMC_REG_BITS_ENUM(EMC_STATUS_DRAM_IN_SELF_REFRESH,      BOTH_ENABLED)
+                                                                                                                 : EMC_REG_BITS_ENUM(EMC_STATUS_DRAM_DEV0_IN_SELF_REFRESH,      ENABLED);
+
+        /* NOTE: Nintendo's sc7 entry firmware has a bug here. */
+        /* Instead of waiting for both EMCs to report self-refresh, they just read the EMC_STATUS for each EMC. */
+        /* This is incorrect, per documentation. */
+        while (!reg::HasValue(EMC0_ADDRESS(EMC_EMC_STATUS), desired)) { /* ... */ }
+        while (!reg::HasValue(EMC1_ADDRESS(EMC_EMC_STATUS), desired)) { /* ... */ }
+    }
+
+    void EnableEmcAllSegmentsRefresh() {
+        constexpr int MR17_PASR_Segment = 17;
+
+        /* Write zeros to MR17_PASR_Segment to enable refresh for all segments for dev0. */
+        reg::Write(EMC_ADDRESS(EMC_MRW), EMC_REG_BITS_ENUM (MRW_DEV_SELECTN,              DEV0),
+                                         EMC_REG_BITS_ENUM (MRW_CNT,                      EXT1),
+                                         EMC_REG_BITS_VALUE(MRW_MA,          MR17_PASR_Segment),
+                                         EMC_REG_BITS_VALUE(MRW_OP,                          0));
+
+        /* If dev1 exists, do the same for dev1. */
+        if (reg::HasValue(EMC_ADDRESS(EMC_ADR_CFG), EMC_REG_BITS_ENUM(ADR_CFG_EMEM_NUMDEV, N2))) {
+            reg::Write(EMC_ADDRESS(EMC_MRW), EMC_REG_BITS_ENUM (MRW_DEV_SELECTN,              DEV1),
+                                             EMC_REG_BITS_ENUM (MRW_CNT,                      EXT1),
+                                             EMC_REG_BITS_VALUE(MRW_MA,          MR17_PASR_Segment),
+                                             EMC_REG_BITS_VALUE(MRW_OP,                          0));
+        }
+    }
+
+    void EnableDdrDeepPowerDown() {
+        /* Read and decode the parameters Nintendo stores in EMC_PMC_SCRATCH3. */
+        const u32 scratch3   = reg::Read(EMC_ADDRESS(EMC_PMC_SCRATCH3));
+        const bool weak_bias = (scratch3 & reg::EncodeMask(EMC_REG_BITS_MASK(PMC_SCRATCH3_WEAK_BIAS))) == reg::EncodeValue(EMC_REG_BITS_ENUM(PMC_SCRATCH3_WEAK_BIAS, ENABLED));
+        const u32 ddr_cntrl  = (scratch3 & reg::EncodeMask(EMC_REG_BITS_MASK(PMC_SCRATCH3_DDR_CNTRL)));
+
+        /* Write the decoded value to PMC_DDR_CNTRL. */
+        reg::Write(PMC + APBDEV_PMC_DDR_CNTRL, ddr_cntrl);
+
+        /* If weak bias is enabled, set all VTT_E_WB bits in APBDEV_PMC_WEAK_BIAS. */
+        if (weak_bias) {
+            constexpr u32 WeakBiasVttEWbAll = 0x7FFF0000;
+            reg::Write(PMC + APBDEV_PMC_WEAK_BIAS, WeakBiasVttEWbAll);
+        }
+
+        /* Request that DPD3 pads power down. */
+        constexpr u32 EristaDpd3Mask = 0x0FFFFFFF;
+        constexpr u32 MarikoDpd3Mask = 0x0FFF9FFF;
+        if (fuse::GetSocType() == fuse::SocType_Erista) {
+            RequestAllPadsPowerDown(APBDEV_PMC_IO_DPD3_REQ, EristaDpd3Mask);
+        } else {
+            RequestAllPadsPowerDown(APBDEV_PMC_IO_DPD3_REQ, MarikoDpd3Mask);
+        }
+
+        /* Request that DPD4 pads power down. */
+        constexpr u32 Dpd4Mask = 0x0FFF1FFF;
+        RequestAllPadsPowerDown(APBDEV_PMC_IO_DPD4_REQ, Dpd4Mask);
+    }
+
+}

exosphere/program/sc7fw/source/sc7fw_dram.hpp

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <exosphere.hpp>
+
+namespace ams::sc7fw {
+
+    void SaveEmcFsp();
+    void EnableSdramSelfRefresh();
+    void EnableEmcAllSegmentsRefresh();
+    void EnableDdrDeepPowerDown();
+
+}

exosphere/program/sc7fw/source/sc7fw_exception_vectors.s

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+.section    .vectors, "ax", %progbits
+.align      3
+.global     reset
+reset:
+    b _start
+    b _ZN3ams5sc7fw16ExceptionHandlerEv

exosphere/program/sc7fw/source/sc7fw_main.cpp

@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <exosphere.hpp>
+#include "sc7fw_util.hpp"
+#include "sc7fw_dram.hpp"
+
+namespace ams::sc7fw {
+
+    namespace {
+
+        constexpr inline const uintptr_t PMC = secmon::MemoryRegionPhysicalDevicePmc.GetAddress();
+
+        void DisableCrail() {
+            /* Wait for CRAIL to be off. */
+            while (!reg::HasValue(PMC + APBDEV_PMC_PWRGATE_STATUS, PMC_REG_BITS_ENUM(PWRGATE_STATUS_CRAIL, OFF))) { /* ... */ }
+
+            /* Set CRAIL to be clamped. */
+            reg::ReadWrite(PMC + APBDEV_PMC_SET_SW_CLAMP, PMC_REG_BITS_VALUE(SET_SW_CLAMP_CRAIL, 1));
+
+            /* Wait for CRAIL to be clamped. */
+            while (!reg::HasValue(PMC + APBDEV_PMC_CLAMP_STATUS, PMC_REG_BITS_ENUM(CLAMP_STATUS_CRAIL, ENABLE))) { /* ... */ }
+
+            /* Spin loop for a short while, to allow time for the clamp to take effect. */
+            sc7fw::SpinLoop(10);
+
+            /* Initialize i2c-5. */
+            i2c::Initialize(i2c::Port_5);
+
+            /* Disable the voltage to CPU. */
+            pmic::DisableVddCpu(fuse::GetRegulator());
+
+            /* Wait 700 microseconds to ensure voltage is disabled. */
+            util::WaitMicroSeconds(700);
+        }
+
+        void DisableAllInterrupts() {
+            /* Disable all interrupts for bpmp in all interrupt controllers. */
+            reg::Write(PRI_ICTLR(ICTLR_COP_IER_CLR),   ~0u);
+            reg::Write(SEC_ICTLR(ICTLR_COP_IER_CLR),   ~0u);
+            reg::Write(TRI_ICTLR(ICTLR_COP_IER_CLR),   ~0u);
+            reg::Write(QUAD_ICTLR(ICTLR_COP_IER_CLR),  ~0u);
+            reg::Write(PENTA_ICTLR(ICTLR_COP_IER_CLR), ~0u);
+            reg::Write(HEXA_ICTLR(ICTLR_COP_IER_CLR),  ~0u);
+        }
+
+        void EnterSc7() {
+            /* Disable read buffering and write buffering in the BPMP cache. */
+            reg::ReadWrite(AVP_CACHE_ADDRESS(AVP_CACHE_CONFIG), AVP_CACHE_REG_BITS_ENUM(DISABLE_WB, TRUE),
+                                                                AVP_CACHE_REG_BITS_ENUM(DISABLE_RB, TRUE));
+
+            /* Ensure the CPU Rail is turned off. */
+            DisableCrail();
+
+            /* Disable all interrupts. */
+            DisableAllInterrupts();
+
+            /* Save the EMC FSP */
+            SaveEmcFsp();
+
+            /* Enable self-refresh for DRAM */
+            EnableSdramSelfRefresh();
+
+            /* Enable refresh for all EMC devices. */
+            EnableEmcAllSegmentsRefresh();
+
+            /* Enable deep power-down for ddr. */
+            EnableDdrDeepPowerDown();
+
+            /* Enable pad sampling during deep sleep. */
+            reg::ReadWrite(PMC + APBDEV_PMC_DPD_SAMPLE, PMC_REG_BITS_ENUM(DPD_SAMPLE_ON, ENABLE));
+            reg::Read(PMC + APBDEV_PMC_DPD_SAMPLE);
+
+            /* Wait a while for pad sampling to be enabled. */
+            sc7fw::SpinLoop(0x128);
+
+            /* Enter deep sleep. */
+            reg::ReadWrite(PMC + APBDEV_PMC_DPD_ENABLE, PMC_REG_BITS_ENUM(DPD_ENABLE_ON, ENABLE));
+
+            /* Wait forever until we're asleep. */
+            AMS_INFINITE_LOOP();
+        }
+
+    }
+
+    void Main() {
+        EnterSc7();
+    }
+
+    NORETURN void ExceptionHandler() {
+        /* Write enable to MAIN_RESET. */
+        reg::Write(PMC + APBDEV_PMC_CNTRL, PMC_REG_BITS_ENUM(CNTRL_MAIN_RESET, ENABLE));
+
+        /* Wait forever until we're reset. */
+        AMS_INFINITE_LOOP();
+    }
+
+}
+
+namespace ams::diag {
+
+    void AbortImpl() {
+        sc7fw::ExceptionHandler();
+    }
+
+}

exosphere/program/sc7fw/source/sc7fw_start.s

@@ -14,27 +14,22 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-.section .text.start
-.align 4
-.global _start
+.section    .text.start, "ax", %progbits
+.align      3
+.global     _start
 _start:
-    b crt0
-.global _reboot
-    b reboot
+    /* Set CPSR_cf and CPSR_cf. */
+    msr cpsr_f, #0xC0
+    msr cpsr_cf, #0xD3
 
-.global crt0
-.type crt0, %function
-crt0:
-    @ setup to call sc7_entry_main
-    msr cpsr_cxsf, #0xD3
-    ldr sp, =__stack_top__
-    ldr lr, =reboot
-    b sc7_entry_main
+    /* Set the stack pointer. */
+    ldr sp, =0x40005000
 
+    /* Set our link register to the exception handler. */
+    ldr lr, =_ZN3ams5sc7fw16ExceptionHandlerEv
 
-.global spinlock_wait
-.type spinlock_wait, %function
-spinlock_wait:
-    subs r0, r0, #1
-    bgt spinlock_wait
-    bx lr
+    /* Invoke main. */
+    bl _ZN3ams5sc7fw4MainEv
+
+    /* Infinite loop. */
+    1: b 1b

exosphere/program/sc7fw/source/sc7fw_util.hpp

@@ -13,8 +13,11 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
+#pragma once
+#include <exosphere.hpp>
 
-#include "rsa_common.h"
+namespace ams::sc7fw {
 
-/* Instantiate the shared RSA data inside a single translation unit. */
-rsa_shared_data_t g_rsa_shared_data = {};
+    void SpinLoop(unsigned int num);
+
+}

exosphere/program/sc7fw/source/sc7fw_util_asm.s

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+.section    .text._ZN3ams5sc7fw8SpinLoopEj, "ax", %progbits
+.global     _ZN3ams5sc7fw8SpinLoopEj
+.thumb_func
+.syntax unified
+_ZN3ams5sc7fw8SpinLoopEj:
+    1:
+        /* Subtract one from the count. */
+        subs r0, r0, #1
+
+        /* If we aren't at zero, continue looping. */
+        bgt  1b
+
+        /* Return. */
+        bx lr

exosphere/program/source/boot/secmon_boot.hpp

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#include <exosphere.hpp>
+
+namespace ams::secmon::boot {
+
+    void MakePageTable();
+    void UnmapPhysicalIdentityMapping();
+    void UnmapDram();
+
+    void InitializeColdBoot();
+
+    bool VerifySignature(void *sig, size_t sig_size, const void *mod, size_t mod_size, const void *msg, size_t msg_size);
+    bool VerifyHash(const void *hash, uintptr_t msg, size_t msg_size);
+
+    bool VerifyBootConfigSignature(pkg1::BootConfig &bc, const void *mod, size_t mod_size);
+    bool VerifyBootConfigEcid(const pkg1::BootConfig &bc);
+
+    void CalculatePackage2Hash(se::Sha256Hash *dst, const pkg2::Package2Meta &meta, uintptr_t package2_start);
+
+    bool VerifyPackage2Signature(pkg2::Package2Header &header, const void *mod, size_t mod_size);
+    void DecryptPackage2(void *dst, size_t dst_size, const void *src, size_t src_size, const void *key, size_t key_size, const void *iv, size_t iv_size, u8 key_generation);
+
+    bool VerifyPackage2Meta(const pkg2::Package2Meta &meta);
+    bool VerifyPackage2Version(const pkg2::Package2Meta &meta);
+    bool VerifyPackage2Payloads(const pkg2::Package2Meta &meta, uintptr_t payload_address);
+
+}

exosphere/program/source/boot/secmon_boot_cache.cpp

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2018-2020 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <exosphere.hpp>
+#include "secmon_boot_cache.hpp"
+
+namespace ams::secmon::boot {
+
+    #include "../secmon_cache_impl.inc"
+
+}