git subrepo push libraries

subrepo:
  subdir:   "libraries"
  merged:   "0c0bb815"
upstream:
  origin:   "https://github.com/Atmosphere-NX/Atmosphere-libs"
  branch:   "master"
  commit:   "0c0bb815"
git-subrepo:
  version:  "0.4.1"
  origin:   "???"
  commit:   "???"

.gitignore

@@ -79,9 +79,8 @@ dkms.conf
 *.nam
 *.til
 
-# KEYS file for sept-secondary.
+# Compiled python files.
 *.pyc
-sept/sept-secondary/KEYS.py
 
 .**/
 
@@ -96,4 +95,6 @@ sept/sept-secondary/KEYS.py
 **/build_nintendo_nx_x64
 **/build_nintendo_nx_x86
 
+package3
+
 stratosphere/test/

Makefile

@@ -13,9 +13,29 @@ ifneq (, $(strip $(shell git status --porcelain 2>/dev/null)))
     AMSREV := $(AMSREV)-dirty
 endif
 
-COMPONENTS := fusee stratosphere mesosphere exosphere thermosphere troposphere libraries
+COMPONENTS := fusee stratosphere mesosphere exosphere emummc thermosphere troposphere libraries
 
 all: $(COMPONENTS)
+	$(eval MAJORVER = $(shell grep 'define ATMOSPHERE_RELEASE_VERSION_MAJOR\b' libraries/libvapours/include/vapours/ams/ams_api_version.h \
+		| tr -s [:blank:] \
+		| cut -d' ' -f3))
+	$(eval MINORVER = $(shell grep 'define ATMOSPHERE_RELEASE_VERSION_MINOR\b' libraries/libvapours/include/vapours/ams/ams_api_version.h \
+		| tr -s [:blank:] \
+		| cut -d' ' -f3))
+	$(eval MICROVER = $(shell grep 'define ATMOSPHERE_RELEASE_VERSION_MICRO\b' libraries/libvapours/include/vapours/ams/ams_api_version.h \
+		| tr -s [:blank:] \
+		| cut -d' ' -f3))
+	$(eval S_MAJORVER = $(shell grep 'define ATMOSPHERE_SUPPORTED_HOS_VERSION_MAJOR\b' libraries/libvapours/include/vapours/ams/ams_api_version.h \
+		| tr -s [:blank:] \
+		| cut -d' ' -f3))
+	$(eval S_MINORVER = $(shell grep 'define ATMOSPHERE_SUPPORTED_HOS_VERSION_MINOR\b' libraries/libvapours/include/vapours/ams/ams_api_version.h \
+		| tr -s [:blank:] \
+		| cut -d' ' -f3))
+	$(eval S_MICROVER = $(shell grep 'define ATMOSPHERE_SUPPORTED_HOS_VERSION_MICRO\b' libraries/libvapours/include/vapours/ams/ams_api_version.h \
+		| tr -s [:blank:] \
+		| cut -d' ' -f3))
+	@python fusee/build_package3.py $(CURDIR) release $(AMSHASH) $(MAJORVER) $(MINORVER) $(MICROVER) 0 $(S_MAJORVER) $(S_MINORVER) $(S_MICROVER) 0
+	@echo "Built package3!"
 
 thermosphere:
 	$(MAKE) -C thermosphere all
@@ -32,10 +52,10 @@ mesosphere: exosphere libraries
 troposphere: stratosphere
 	$(MAKE) -C troposphere all
 
-sept: exosphere
+emummc:
-	$(MAKE) -C sept all
+	$(MAKE) -C emummc all
 
-fusee: exosphere mesosphere stratosphere sept
+fusee: exosphere mesosphere stratosphere
 	$(MAKE) -C $@ all
 
 libraries:
@@ -43,6 +63,12 @@ libraries:
 
 clean:
 	$(MAKE) -C fusee clean
+	$(MAKE) -C emummc clean
+	$(MAKE) -C libraries clean
+	$(MAKE) -C exosphere clean
+	$(MAKE) -C thermosphere clean
+	$(MAKE) -C mesosphere clean
+	$(MAKE) -C stratosphere clean
 	rm -rf out
 
 dist-no-debug: all
@@ -60,27 +86,18 @@ dist-no-debug: all
 	rm -rf out
 	mkdir atmosphere-$(AMSVER)
 	mkdir atmosphere-$(AMSVER)/atmosphere
-	mkdir atmosphere-$(AMSVER)/sept
 	mkdir atmosphere-$(AMSVER)/switch
 	mkdir -p atmosphere-$(AMSVER)/atmosphere/fatal_errors
 	mkdir -p atmosphere-$(AMSVER)/atmosphere/config_templates
 	mkdir -p atmosphere-$(AMSVER)/atmosphere/config
 	mkdir -p atmosphere-$(AMSVER)/atmosphere/flags
-	touch atmosphere-$(AMSVER)/atmosphere/flags/clean_stratosphere_for_0.19.0.flag
+	cp fusee/fusee.bin atmosphere-$(AMSVER)/atmosphere/reboot_payload.bin
-	cp fusee/fusee-primary/fusee-primary.bin atmosphere-$(AMSVER)/atmosphere/reboot_payload.bin
+	cp fusee/package3 atmosphere-$(AMSVER)/atmosphere/package3
-	cp fusee/fusee-mtc/fusee-mtc.bin atmosphere-$(AMSVER)/atmosphere/fusee-mtc.bin
+	cp config_templates/stratosphere.ini atmosphere-$(AMSVER)/atmosphere/config_templates/stratosphere.ini
-	cp fusee/fusee-secondary/fusee-secondary-experimental.bin atmosphere-$(AMSVER)/atmosphere/fusee-secondary.bin
-	cp fusee/fusee-secondary/fusee-secondary-experimental.bin atmosphere-$(AMSVER)/sept/payload.bin
-	cp sept/sept-primary/sept-primary.bin atmosphere-$(AMSVER)/sept/sept-primary.bin
-	cp sept/sept-secondary/sept-secondary.bin atmosphere-$(AMSVER)/sept/sept-secondary.bin
-	cp sept/sept-secondary/sept-secondary_00.enc atmosphere-$(AMSVER)/sept/sept-secondary_00.enc
-	cp sept/sept-secondary/sept-secondary_01.enc atmosphere-$(AMSVER)/sept/sept-secondary_01.enc
-	cp sept/sept-secondary/sept-secondary_dev_00.enc atmosphere-$(AMSVER)/sept/sept-secondary_dev_00.enc
-	cp sept/sept-secondary/sept-secondary_dev_01.enc atmosphere-$(AMSVER)/sept/sept-secondary_dev_01.enc
-	cp config_templates/BCT.ini atmosphere-$(AMSVER)/atmosphere/config_templates/BCT.ini
 	cp config_templates/override_config.ini atmosphere-$(AMSVER)/atmosphere/config_templates/override_config.ini
 	cp config_templates/system_settings.ini atmosphere-$(AMSVER)/atmosphere/config_templates/system_settings.ini
 	cp config_templates/exosphere.ini atmosphere-$(AMSVER)/atmosphere/config_templates/exosphere.ini
+	mkdir config_templates/kip_patches
 	cp -r config_templates/kip_patches atmosphere-$(AMSVER)/atmosphere/kip_patches
 	cp -r config_templates/hbl_html atmosphere-$(AMSVER)/atmosphere/hbl_html
 	mkdir -p atmosphere-$(AMSVER)/stratosphere_romfs/atmosphere/contents/0100000000000008
@@ -107,14 +124,10 @@ dist-no-debug: all
 	cp troposphere/reboot_to_payload/reboot_to_payload.nro atmosphere-$(AMSVER)/switch/reboot_to_payload.nro
 	cp troposphere/daybreak/daybreak.nro atmosphere-$(AMSVER)/switch/daybreak.nro
 	cd atmosphere-$(AMSVER); zip -r ../atmosphere-$(AMSVER).zip ./*; cd ../;
-	cp fusee/fusee-secondary/fusee-secondary.bin atmosphere-$(AMSVER)/atmosphere/fusee-secondary.bin
+	rm -rf atmosphere-$(AMSVER)
-	cp fusee/fusee-secondary/fusee-secondary.bin atmosphere-$(AMSVER)/sept/payload.bin
-	cd atmosphere-$(AMSVER); zip -r ../atmosphere-$(AMSVER)-WITHOUT_MESOSPHERE.zip ./*; cd ../;
-	rm -r atmosphere-$(AMSVER)
 	mkdir out
 	mv atmosphere-$(AMSVER).zip out/atmosphere-$(AMSVER).zip
-	mv atmosphere-$(AMSVER)-WITHOUT_MESOSPHERE.zip out/atmosphere-$(AMSVER)-WITHOUT_MESOSPHERE.zip
+	cp fusee/fusee.bin out/fusee.bin
-	cp fusee/fusee-primary/fusee-primary.bin out/fusee-primary.bin
 
 dist: dist-no-debug
 	$(eval MAJORVER = $(shell grep 'define ATMOSPHERE_RELEASE_VERSION_MAJOR\b' libraries/libvapours/include/vapours/ams/ams_api_version.h \
@@ -129,12 +142,8 @@ dist: dist-no-debug
 	$(eval AMSVER = $(MAJORVER).$(MINORVER).$(MICROVER)-$(AMSREV))
 	rm -rf atmosphere-$(AMSVER)-debug
 	mkdir atmosphere-$(AMSVER)-debug
-	cp fusee/fusee-primary/fusee-primary.elf atmosphere-$(AMSVER)-debug/fusee-primary.elf
+	cp fusee/loader_stub/loader_stub.elf atmosphere-$(AMSVER)-debug/fusee-loader-stub.elf
-	cp fusee/fusee-mtc/fusee-mtc.elf atmosphere-$(AMSVER)-debug/fusee-mtc.elf
+	cp fusee/program/program.elf atmosphere-$(AMSVER)-debug/fusee-program.elf
-	cp fusee/fusee-secondary/fusee-secondary-experimental.elf atmosphere-$(AMSVER)-debug/fusee-secondary.elf
-	cp sept/sept-primary/sept-primary.elf atmosphere-$(AMSVER)-debug/sept-primary.elf
-	cp sept/sept-secondary/sept-secondary.elf atmosphere-$(AMSVER)-debug/sept-secondary.elf
-	cp sept/sept-secondary/key_derivation/key_derivation.elf atmosphere-$(AMSVER)-debug/sept-secondary-key-derivation.elf
 	cp exosphere/loader_stub/loader_stub.elf atmosphere-$(AMSVER)-debug/exosphere-loader-stub.elf
 	cp exosphere/program/program.elf atmosphere-$(AMSVER)-debug/exosphere-program.elf
 	cp exosphere/warmboot/warmboot.elf atmosphere-$(AMSVER)-debug/exosphere-warmboot.elf

config_templates/BCT.ini

@@ -1,12 +0,0 @@
-BCT0
-[stage1]
-stage2_path = atmosphere/fusee-secondary.bin
-stage2_mtc_path = atmosphere/fusee-mtc.bin
-stage2_addr = 0xF0000000
-stage2_entrypoint = 0xF0000000
-
-[stratosphere]
-; To force-enable nogc, add nogc = 1
-; To force-disable nogc, add nogc = 0
-
-; To opt out of using Atmosphere's NCM reimplementation, add disable_ncm = 1

config_templates/stratosphere.ini

@@ -0,0 +1,4 @@
+[stratosphere]
+; To force-enable nogc, add nogc = 1
+; To force-disable nogc, add nogc = 0
+

docs/building.md

@@ -21,12 +21,4 @@ Building Atmosphère is a very straightforward process that relies almost exclus
 3. Install the following library via python's package manager `pip`, required by [exosphere](components/exosphere.md):
     + `lz4`
 
-4. (Optional) In order to build [sept](components/sept.md) the pycryptodome PyPi package is required, which can be installed by running `pip install pycryptodome` under the installed Python environment of your choice or by installing the complete zip package to support the `make dist` recipe. This is an optional step included for advanced users who have the ability to provide the necessary encryption/signing keys themselves.
+4. Finally, clone the Atmosphère repository and run `make` under its root directory.
-
-5. It is, instead, possible to build [sept](components/sept.md) by providing previously encrypted/signed binaries distributed by official Atmosphère release packages. In order to do so, export the following variables in your current environment:
-    + `SEPT_00_ENC_PATH` (must point to the `sept-secondary_00.enc` file)
-    + `SEPT_01_ENC_PATH` (must point to the `sept-secondary_01.enc` file)
-    + `SEPT_DEV_00_ENC_PATH` (must point to the `sept-secondary_dev_00.enc` file)
-    + `SEPT_DEV_01_ENC_PATH` (must point to the `sept-secondary_dev_01.enc` file)
-
-6. Finally, clone the Atmosphère repository and run `make` under its root directory.

docs/changelog.md

@@ -1,4 +1,66 @@
 # Changelog
+## 1.0.0
++ `fusee` was completely re-written in C++ to use the same atmosphere-libs APIs as the rest of atmosphere's code.
+  + The rewrite was performed with a big emphasis on ensuring a good boot speed, and generally boot should be much faster than it was previously.
+    + Depending on SD card/environment, boot speed may now be slightly faster than, roughly the same as, or slightly slower than when booting with hekate.
+    + The obvious low-hanging fruit for performance improvements has been picked, so hopefully the improved performance is to everybody's liking.
+  + SD card compatibility was improved: fusee should now have SD card compatibility identical to the official OS driver.
+  + **Please Note**: various components were renamed (fusee-primary.bin -> fusee.bin, fusee-secondary.bin -> package3).
+    + If you use another bootloader (like hekate), you may need to update your configuration to use the new layout.
+  + **Please Note**: BCT.ini no longer exists, nogc configuration has been moved to `/atmosphere/stratosphere.ini`.
+    + If you rely on custom nogc configuration, please be sure to update accordingly.
+  + Custom splash screen BMP parsing is no longer supported (as it slows down boot for 99% of users).
+    + To compensate for this, a script to insert a custom splash screen into a `package3` binary has been added to the `utilities` folder of the atmosphere repository.
+    + The release build should be equivalent to running the following command from the root of the atmosphere repository: `python utilities/insert_splash_screen.py img/splash.png fusee/package3`
++ A number of pending changes were made, following the end of the relevant testing periods:
+  + `mesosphere` is no longer opt-out, and stratosphere code will begin depending on its being present/in use.
+  + `NCM` is no longer opt-out.
+  + The cleanup to ease the transition from < 0.19.0 to 0.19.0 has been removed.
++ General system stability improvements to enhance the user's experience.
+## 0.20.1
++ An issue was fixed that caused severely degraded performance after wake-from-sleep on Mariko hardware.
+  + This was due to Mariko MTC resulting in a frequency of 1599.999MHz instead of 1600MHz.
+  + Due to this off-by-one, Nintendo's EMC management code failed to initialize/take over, and after wake from sleep RAM would be in a strange state.
++ General system stability improvements to enhance the user's experience.
+## 0.20.0
++ DRAM training (MTC) was implemented for Mariko hardware, increasing RAM speed from 204MHz to 1600MHz.
+  + This significantly optimizes Mariko boot speed, cutting boot time roughly in half.
+  + Typical boot time reductions (measured as "select fusee" to "home menu visible"):
+    + Normal (Iowa): ~35 seconds -> ~18 seconds.
+    + Lite (Hoag): ~65 seconds -> ~30 seconds.
+  + NOTE: Work is being started on a re-written `fusee` component, with an eye specifically towards ensuring a good boot speed.
+    + With any luck, boot will be much much faster on all units (Mariko and Erista) in an upcoming release.
++ Sept was replaced, and deleted from the repository.
+  + Erista units now use a custom TSEC firmware to manage key derivation.
+    + For more details, contact SciresM#0524 on discord.
+  + This has a number of benefits, including:
+    + This greatly simplifies key derivation logic by making it consistent on all firmwares.
+      + Fusee no longer accesses/uses keyblobs at all, so units which have accidentally destroyed/lost keyblobs can boot without them.
+    + This greatly increases stability (sept was the biggest source of boot failures).
+    + This improves boot speed (sept rebooted multiple times, performed hardware init multiple times, and was generally very slow).
+    + Atmosphère build process is now much saner.
++ A number of improvements were made to the dmnt cheat engine.
+  + Cheats which take in a memory region operand may now use types "2" or "3" to perform accesses relative to the alias/aslr regions, respectively.
+  + Support was added for an "else" opcode in the cheat engine, to make writing certain conditional logic more natural.
+  + Support was added for a cheat orchestrator homebrew (like edizon) to detach from a cheat process/set the master cheat programmatically.
++ Daybreak now provides a warning when attempting to install a firmware newer than the highest version atmosphère knows it supports.
+  + To facilitate this, exosphere now exposes the supported HOS version via an extension ConfigItem.
++ A number of minor issues were fixed, including:
+  + Several mesosphere debug SVC implementations were updated to reflect the semantics of the latest kernel.
+  + Support was fixed for deriving BIS encryption keys on certain prototype hardware.
++ General system stability improvements to enhance the user's experience.
+## 0.19.5
++ Support was added for 12.1.0.
++ LayeredFS support was added for OpenDataStorageWithProgramIndex commands.
+  + Certain games using newer (7.0.0+ APIs) which include multiple programs under a single title previously could not be modified.
+  + These are now supported as normal, and LayeredFS should have 100% compatibility again.
++ A number of minor issues were fixed, including:
+  + The Reboot to Payload NRO was updated to allow the OS to save state prior to rebooting (thanks @AuroraWright)!
+  + An issue was fixed that could cause dns.mitm to fail when games requested resolution of an empty string.
+  + An issue was fixed that caused a memory leak in the erpt system module.
+    + This would eventually cause a system crash after ~540 reports were generated without rebooting.
++ A number of minor improvements were made to improve mesosphere's accuracy.
++ General system stability improvements to enhance the user's experience.
 ## 0.19.4
 + Support was added for 12.0.3.
 + A number of minor issues were fixed, including:

docs/components/fusee.md

@@ -1,22 +1,8 @@
 # fusée
 fusée is a custom bootloader used to start the Atmosphère environment.
-It is divided into three sub-components: fusée-primary, fusée-mtc and fusée-secondary.
 
-fusée is also capable of chainloading other payloads (e.g.: Android).
+## fusée
-
+fusée is the first piece of Atmosphère's code that runs on the hardware.
-fusée's behavior can be configured via the [BCT.ini](../features/configurations.md) file located on the SD card.
-
-## fusée-primary
-fusée-primary is the first piece of Atmosphère's code that runs on the hardware.
 It is distributed as a standalone payload designed to be launched via RCM by abusing the CVE-2018-6242 vulnerability.
 
-This payload is responsible for all the low-level hardware initialization required by the Nintendo Switch, plus the extra task of initializing the SD card and reading the next fusée sub-components from it.
+This payload is responsible for all the low-level hardware initialization required by the Nintendo Switch, setting up the cryptosystem, mounting/emulating the eMMC, injecting/patching system modules, and launching the exosphère component.
-
-## fusée-mtc
-fusée-mtc is an optional, but heavily recommended sub-component that performs DRAM memory training.
-This ensures a proper environment for running the final fusée sub-component.
-
-## fusée-secondary
-fusée-secondary is the last fusée sub-component that runs on the system.
-It is responsible for configuring and bootstrapping the Atmosphère environment by mimicking the Horizon OS's design.
-This includes setting up the cryptosystem, mounting or emulating the eMMC, injecting or patching system modules and launching the exosphère component.

docs/components/sept.md

@@ -1,14 +0,0 @@
-# sept
-Sept is a payload that facilitates booting Atmosphère when targeting firmware version 7.0.0+.
-
-It consists of a primary and a secondary payload.
-
-## sept-primary
-sept-primary is essentially a stand-in for Nintendo's package1ldr, on 7.0.0+. To use it, the caller (normally fusée-secondary) loads the sept-primary binary to `0x4003F000`, loads the 7.0.0+ TSEC firmware to `0x40010F00`, and loads a signed, encrypted payload to `0x40016FE0`.
-
-This signed, encrypted payload is normally sept-secondary.
-
-## sept-secondary
-sept-secondary is a payload that performs 7.0.0+ key derivation, and then chainloads to `sept/payload.bin`.
-
-It is normally stored encrypted/signed. Therefore, if one wishes to build sept-secondary instead of using release builds, one must bring their own keys.

docs/features/cheats.md

@@ -19,6 +19,8 @@ This behavior ensures that cheat codes are only loaded when the user would want
 
 In cases where `dmnt` has not activated the cheat manager, but the user wants to make it do so anyway, the cheat manager's service API provides a `ForceOpenCheatProcess` command that homebrew can use. This command will cause the cheat manager to try to force itself to attach to the process.
 
+In cases where `dmnt` has activated the cheat manager, but the user wants to use an alternate debugger, the cheat manager's service API provides a `ForceCloseCheatProcess` command that homebrew can use. This command will cause the cheat manager to detach itself from the process.
+
 By default, all cheat codes listed in the loaded .txt file will be toggled on. This is configurable by the user by editing the `atmosphere!dmnt_cheats_enabled_by_default` [system setting](configurations.md).
 
 Users may use homebrew programs to toggle cheats on and off at runtime via the cheat manager's service API.
@@ -40,30 +42,30 @@ The following provides documentation of the instruction format for the virtual m
 
 Typically, instruction type is encoded in the upper nybble of the first instruction u32.
 
-### Code Type 0: Store Static Value to Memory
+### Code Type 0x0: Store Static Value to Memory
-Code type 0 allows writing a static value to a memory address.
+Code type 0x0 allows writing a static value to a memory address.
 
 #### Encoding
 `0TMR00AA AAAAAAAA VVVVVVVV (VVVVVVVV)`
 
 + T: Width of memory write (1, 2, 4, or 8 bytes).
-+ M: Memory region to write to (0 = Main NSO, 1 = Heap).
++ M: Memory region to write to (0 = Main NSO, 1 = Heap, 2 = Alias, 3 = Aslr).
 + R: Register to use as an offset from memory region base.
 + A: Immediate offset to use from memory region base.
 + V: Value to write.
 
 ---
 
-### Code Type 1: Begin Conditional Block
+### Code Type 0x1: Begin Conditional Block
-Code type 1 performs a comparison of the contents of memory to a static value.
+Code type 0x1 performs a comparison of the contents of memory to a static value.
 
-If the condition is not met, all instructions until the appropriate conditional block terminator are skipped.
+If the condition is not met, all instructions until the appropriate End or Else conditional block terminator are skipped.
 
 #### Encoding
 `1TMC00AA AAAAAAAA VVVVVVVV (VVVVVVVV)`
 
 + T: Width of memory write (1, 2, 4, or 8 bytes).
-+ M: Memory region to write to (0 = Main NSO, 1 = Heap).
++ M: Memory region to write to (0 = Main NSO, 1 = Heap, 2 = Alias, 3 = Aslr).
 + C: Condition to use, see below.
 + A: Immediate offset to use from memory region base.
 + V: Value to compare to.
@@ -78,16 +80,20 @@ If the condition is not met, all instructions until the appropriate conditional
 
 ---
 
-### Code Type 2: End Conditional Block
+### Code Type 0x2: End Conditional Block
-Code type 2 marks the end of a conditional block (started by Code Type 1 or Code Type 8).
+Code type 0x2 marks the end of a conditional block (started by Code Type 0x1 or Code Type 0x8).
+
+When an Else is executed, all instructions until the appropriate End conditional block terminator are skipped.
 
 #### Encoding
-`20000000`
+`2X000000`
+
++ X: End type (0 = End, 1 = Else).
 
 ---
 
-### Code Type 3: Start/End Loop
+### Code Type 0x3: Start/End Loop
-Code type 3 allows for iterating in a loop a fixed number of times.
+Code type 0x3 allows for iterating in a loop a fixed number of times.
 
 #### Start Loop Encoding
 `300R0000 VVVVVVVV`
@@ -102,8 +108,8 @@ Code type 3 allows for iterating in a loop a fixed number of times.
 
 ---
 
-### Code Type 4: Load Register with Static Value
+### Code Type 0x4: Load Register with Static Value
-Code type 4 allows setting a register to a constant value.
+Code type 0x4 allows setting a register to a constant value.
 
 #### Encoding
 `400R0000 VVVVVVVV VVVVVVVV`
@@ -113,29 +119,28 @@ Code type 4 allows setting a register to a constant value.
 
 ---
 
-### Code Type 5: Load Register with Memory Value
+### Code Type 0x5: Load Register with Memory Value
-Code type 5 allows loading a value from memory into a register, either using a fixed address or by dereferencing the destination register.
+Code type 0x5 allows loading a value from memory into a register, either using a fixed address or by dereferencing the destination register.
 
 #### Load From Fixed Address Encoding
 `5TMR00AA AAAAAAAA`
 
 + T: Width of memory read (1, 2, 4, or 8 bytes).
-+ M: Memory region to write to (0 = Main NSO, 1 = Heap).
++ M: Memory region to write to (0 = Main NSO, 1 = Heap, 2 = Alias, 3 = Aslr).
 + R: Register to load value into.
 + A: Immediate offset to use from memory region base.
 
 #### Load from Register Address Encoding
-`5TMR10AA AAAAAAAA`
+`5T0R10AA AAAAAAAA`
 
 + T: Width of memory read (1, 2, 4, or 8 bytes).
-+ M: Memory region to write to (0 = Main NSO, 1 = Heap).
++ R: Register to load value into. (This register is also used as the base memory address).
-+ R: Register to load value into.
 + A: Immediate offset to use from register R.
 
 ---
 
-### Code Type 6: Store Static Value to Register Memory Address
+### Code Type 0x6: Store Static Value to Register Memory Address
-Code type 6 allows writing a fixed value to a memory address specified by a register.
+Code type 0x6 allows writing a fixed value to a memory address specified by a register.
 
 #### Encoding
 `6T0RIor0 VVVVVVVV VVVVVVVV`
@@ -149,10 +154,10 @@ Code type 6 allows writing a fixed value to a memory address specified by a regi
 
 ---
 
-### Code Type 7: Legacy Arithmetic
+### Code Type 0x7: Legacy Arithmetic
-Code type 7 allows performing arithmetic on registers.
+Code type 0x7 allows performing arithmetic on registers.
 
-However, it has been deprecated by Code type 9, and is only kept for backwards compatibility.
+However, it has been deprecated by Code type 0x9, and is only kept for backwards compatibility.
 
 #### Encoding
 `7T0RC000 VVVVVVVV`
@@ -171,8 +176,8 @@ However, it has been deprecated by Code type 9, and is only kept for backwards c
 
 ---
 
-### Code Type 8: Begin Keypress Conditional Block
+### Code Type 0x8: Begin Keypress Conditional Block
-Code type 8 enters or skips a conditional block based on whether a key combination is pressed.
+Code type 0x8 enters or skips a conditional block based on whether a key combination is pressed.
 
 #### Encoding
 `8kkkkkkk`
@@ -213,8 +218,8 @@ Note: This is the direct output of `hidKeysDown()`.
 
 ---
 
-### Code Type 9: Perform Arithmetic
+### Code Type 0x9: Perform Arithmetic
-Code type 9 allows performing arithmetic on registers.
+Code type 0x9 allows performing arithmetic on registers.
 
 #### Register Arithmetic Encoding
 `9TCRS0s0`
@@ -248,8 +253,8 @@ Code type 9 allows performing arithmetic on registers.
 
 ---
 
-### Code Type 10: Store Register to Memory Address
+### Code Type 0xA: Store Register to Memory Address
-Code type 10 allows writing a register to memory.
+Code type 0xA allows writing a register to memory.
 
 #### Encoding
 `ATSRIOxa (aaaaaaaa)`
@@ -272,13 +277,13 @@ Code type 10 allows writing a register to memory.
 
 ---
 
-### Code Type 11: Reserved
+### Code Type 0xB: Reserved
-Code Type 11 is currently reserved for future use.
+Code Type 0xB is currently reserved for future use.
 
 ---
 
-### Code Type 12-15: Extended-Width Instruction
+### Code Type 0xC-0xF: Extended-Width Instruction
-Code Types 12-15 signal to the VM to treat the upper two nybbles of the first dword as instruction type, instead of just the upper nybble.
+Code Types 0xC-0xF signal to the VM to treat the upper two nybbles of the first dword as instruction type, instead of just the upper nybble.
 
 This reserves an additional 64 opcodes for future use.
 

docs/features/configurations.md

@@ -1,21 +1,10 @@
 # Configurations
 Atmosphère provides a variety of customizable configurations to better adjust to users' needs.
 
-## BCT.ini
+## stratosphere.ini
-This is the configuration file used by fusée.
+This is the configuration file used by fusée for configuring user-space system modules.
 This file is located under the `/atmosphere/config/` folder on your SD card and a default template can be found inside the `/atmosphere/config_templates/` folder.
 
-### Adding a Custom Boot Splashscreen
-Atmosphère provides its own default splashscreen which is displayed at boot time. However, this can be replaced at will.
-
-The boot splashscreen must be a BMP file, it must be 720x1280 (1280x720 rotated 90 degrees left/counterclockwise/anti-clockwise) resolution, and be in 32-bit ARGB format. You can use image editing software such as GIMP or Photoshop to export the image in this format.
-
-Add the following lines to BCT.ini and change the value of `custom_splash` to the actual path and filename of your boot splashscreen:
-```
-[stage2]
-custom_splash = /path/to/your/bootlogo.bmp
-```
-
 ### Configuring "nogc" Protection
 "nogc" is a feature provided by fusée-secondary which disables the Nintendo Switch's Game Card reader. Its purpose is to prevent the reader from being updated when the console has been updated, without burning fuses, from a lower firmware version. More specifically, from firmware versions 4.0.0 or 9.0.0 which introduced updates to the Game Card reader's firmware. By default, Atmosphère will protect the Game Card reader automatically, but you are free to change it.
 
@@ -29,32 +18,15 @@ nogc = X
 0 = force-disable nogc, so Atmosphère will always enable the Game Card reader.
 ```
 
-### NCM opt-out
+## Adding a Custom Boot Splashscreen
-Atmosphère provides a reimplementation of the [ncm](../components/modules/ncm.md) system module. If you wish to disable this reimplementation add the following line to the `stratosphere` section:
+Atmosphère provides its own default splashscreen which is displayed at boot time. However, this can be replaced at will.
-```
-[stratosphere]
-disable_ncm = 1
-```
 
-### Logging
+Boot splash screens must be 1280x720 resolution.
-This is an advanced feature aimed at developers trying to debug boot time issues. It enables logging of the fusée stages to be displayed on screen.
 
-Add the following lines to BCT.ini and change the value of `X` according to the following list:
+A script can be found inside the source tree (`/utilities/insert_splash_screen.py`) for inserting a custom splash screen into a release binary.
-```
-[config]
-log_level = X
-```
-```
-0 = NONE
-1 = ERROR
-2 = WARNING
-3 = MANDATORY
-4 = INFO
-5 = DEBUG
-```
 
-A special level is also provided to prevent prefix creation. To use it, do a bitwise OR with this mask:
+To do so, execute the following command on the script:
-`0x100 = NO_PREFIX`
+`python insert_splash_screen.py <path to your splash screen image> <path to /atmosphere/package3 on your SD card>`
 
 ## emummc.ini
 This is the configuration file used for the [emummc](../components/emummc.md) component.

docs/main.md

@@ -12,7 +12,6 @@ Atmosphère provides six core components, mimicking to some degree the various l
 
 Additionally, Atmosphère also provides the following secondary components:
 + [emummc](components/emummc.md)
-+ [sept](components/sept.md)
 + [libraries](components/libraries.md)
 
 ## Features

emummc/.gitrepo

@@ -6,7 +6,7 @@
 [subrepo]
 	remote = https://github.com/m4xw/emuMMC
 	branch = develop
-	commit = 219c723c3001fbc33d47840ceceb83cf39a1d218
+	commit = cbc294c390ed73bb281bc1028a8899c053427112
-	parent = 7821241356c2f6b159945babf657ffd921957918
+	parent = 38f9a76ba028995ed3274da3a45b0254f09d1f59
 	method = rebase
 	cmdver = 0.4.1

emummc/Makefile

@@ -32,7 +32,7 @@ CFLAGS	+=	$(INCLUDE) -D__SWITCH__
 CXXFLAGS	:= $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++17
 
 ASFLAGS	:=	-g $(ARCH)
-LDFLAGS	=	-specs=$(DEVKITPRO)/libnx/switch.specs -g $(ARCH) -Wl,-Map,$(notdir $*.map)
+LDFLAGS	=	-specs=$(EMUMMCDIR)/emummc.specs -g $(ARCH) -Wl,-Map,$(notdir $*.map)
 
 ifneq ($(BUILD),$(notdir $(CURDIR)))
 
@@ -98,7 +98,10 @@ else
 
 DEPENDS	:=	$(OFILES:.o=.d)
 
-all	:	$(OUTPUT).kip
+all	:	$(OUTPUT)_unpacked.kip
+
+$(OUTPUT)_unpacked.kip	:	$(OUTPUT).kip
+	@hactool -t kip --uncompressed=$(OUTPUT)_unpacked.kip $(OUTPUT).kip
 
 $(OUTPUT).kip	:	$(OUTPUT).elf
 

emummc/emummc.ld

@@ -0,0 +1,201 @@
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+
+PHDRS
+{
+	code   PT_LOAD FLAGS(5) /* Read | Execute */;
+	rodata PT_LOAD FLAGS(4) /* Read */;
+	data   PT_LOAD FLAGS(6) /* Read | Write */;
+	dyn    PT_DYNAMIC;
+}
+
+SECTIONS
+{
+	/* =========== CODE section =========== */
+	PROVIDE(__start__ = 0x0);
+	. = __start__;
+	__code_start = . ;
+
+	.crt0 :
+	{
+		KEEP (*(.crt0))
+		. = ALIGN(8);
+	} :code
+
+	.init :
+	{
+		KEEP( *(.init) )
+		. = ALIGN(8);
+	} :code
+
+	.plt :
+	{
+		*(.plt)
+		*(.iplt)
+		. = ALIGN(8);
+	} :code
+
+	.text :
+	{
+		*(.text.unlikely .text.*_unlikely .text.unlikely.*)
+		*(.text.exit .text.exit.*)
+		*(.text.startup .text.startup.*)
+		*(.text.hot .text.hot.*)
+		*(.text .stub .text.* .gnu.linkonce.t.*)
+		. = ALIGN(8);
+	} :code
+
+	.fini :
+	{
+		KEEP( *(.fini) )
+		. = ALIGN(8);
+	} :code
+
+	/* =========== RODATA section =========== */
+	. = ALIGN(0x1000);
+	__rodata_start = . ;
+
+	.nx-module-name : { KEEP (*(.nx-module-name)) } :rodata
+
+	.rodata :
+	{
+		*(.rodata .rodata.* .gnu.linkonce.r.*)
+		. = ALIGN(8);
+	} :rodata
+
+	.eh_frame_hdr     : { __eh_frame_hdr_start = .; *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) __eh_frame_hdr_end = .; } :rodata
+	.eh_frame         : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } :rodata
+	.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } :rodata
+	.gnu_extab        : ONLY_IF_RO { *(.gnu_extab*) } : rodata
+
+	.dynamic           : { *(.dynamic) } :rodata :dyn
+	.dynsym            : { *(.dynsym) } :rodata
+	.dynstr            : { *(.dynstr) } :rodata
+	.rela.dyn          : { *(.rela.*) } :rodata
+	.interp            : { *(.interp) } :rodata
+	.hash              : { *(.hash) } :rodata
+	.gnu.hash          : { *(.gnu.hash) } :rodata
+	.gnu.version       : { *(.gnu.version) } :rodata
+	.gnu.version_d     : { *(.gnu.version_d) } :rodata
+	.gnu.version_r     : { *(.gnu.version_r) } :rodata
+	.note.gnu.build-id : { *(.note.gnu.build-id) } :rodata
+
+	/* =========== DATA section =========== */
+	. = ALIGN(0x1000);
+	__data_start = . ;
+
+	.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) } :data
+	.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } :data
+	.gnu_extab : ONLY_IF_RW { *(.gnu_extab*) } : data
+	.exception_ranges : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) } :data
+
+	.tdata ALIGN(8) :
+	{
+		__tdata_lma = .;
+		*(.tdata .tdata.* .gnu.linkonce.td.*)
+		. = ALIGN(8);
+		__tdata_lma_end = .;
+	} :data
+
+	.tbss ALIGN(8) :
+	{
+		*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+		. = ALIGN(8);
+	} :data
+
+	.preinit_array ALIGN(8) :
+	{
+		PROVIDE (__preinit_array_start = .);
+		KEEP (*(.preinit_array))
+		PROVIDE (__preinit_array_end = .);
+	} :data
+
+	.init_array ALIGN(8) :
+	{
+		PROVIDE (__init_array_start = .);
+		KEEP( *(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)) )
+		KEEP( *(.init_array .ctors) )
+		PROVIDE (__init_array_end = .);
+	} :data
+
+	.fini_array ALIGN(8) :
+	{
+		PROVIDE (__fini_array_start = .);
+		KEEP( *(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)) )
+		KEEP( *(.fini_array .dtors) )
+		PROVIDE (__fini_array_end = .);
+	} :data
+
+	__got_start__ = .;
+
+	.got            : { *(.got) *(.igot) } :data
+	.got.plt        : { *(.got.plt)  *(.igot.plt) } :data
+
+	__got_end__ = .;
+
+	.data ALIGN(8) :
+	{
+		*(.data .data.* .gnu.linkonce.d.*)
+		SORT(CONSTRUCTORS)
+	} :data
+
+	__bss_start__ = .;
+	.bss ALIGN(8) :
+	{
+		*(.dynbss)
+		*(.bss .bss.* .gnu.linkonce.b.*)
+		*(COMMON)
+		. = ALIGN(8);
+
+		/* Reserve space for the TLS segment of the main thread */
+		__tls_start = .;
+		. += + SIZEOF(.tdata) + SIZEOF(.tbss);
+		__tls_end = .;
+	} : data
+	__bss_end__ = .;
+
+	__end__ = ABSOLUTE(.) ;
+
+	. = ALIGN(0x1000);
+	__argdata__ = ABSOLUTE(.) ;
+
+	/* ==================
+	   ==== Metadata ====
+	   ================== */
+
+	/* Discard sections that difficult post-processing */
+	/DISCARD/ : { *(.group .comment .note) }
+
+	/* Stabs debugging sections. */
+	.stab          0 : { *(.stab) }
+	.stabstr       0 : { *(.stabstr) }
+	.stab.excl     0 : { *(.stab.excl) }
+	.stab.exclstr  0 : { *(.stab.exclstr) }
+	.stab.index    0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+
+	/* DWARF debug sections.
+	   Symbols in the DWARF debugging sections are relative to the beginning
+	   of the section so we begin them at 0. */
+
+	/* DWARF 1 */
+	.debug          0 : { *(.debug) }
+	.line           0 : { *(.line) }
+
+	/* GNU DWARF 1 extensions */
+	.debug_srcinfo  0 : { *(.debug_srcinfo) }
+	.debug_sfnames  0 : { *(.debug_sfnames) }
+
+	/* DWARF 1.1 and DWARF 2 */
+	.debug_aranges  0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+
+	/* DWARF 2 */
+	.debug_info     0 : { *(.debug_info) }
+	.debug_abbrev   0 : { *(.debug_abbrev) }
+	.debug_line     0 : { *(.debug_line) }
+	.debug_frame    0 : { *(.debug_frame) }
+	.debug_str      0 : { *(.debug_str) }
+	.debug_loc      0 : { *(.debug_loc) }
+	.debug_macinfo  0 : { *(.debug_macinfo) }
+}

emummc/emummc.specs

@@ -0,0 +1,8 @@
+%rename link                old_link
+
+*link:
+%(old_link) -T %:getenv(TOPDIR /emummc.ld) -pie --no-dynamic-linker --spare-dynamic-tags=0 --gc-sections -z text -z nodynamic-undefined-weak --build-id=sha1 --nx-module-name
+
+*startfile:
+crti%O%s crtbegin%O%s
+

exosphere/loader_stub/source/secmon_loader_main.cpp

@@ -20,13 +20,13 @@
 
 namespace ams::secmon::loader {
 
-    NORETURN void UncompressAndExecute() {
+    NORETURN void UncompressAndExecute(const void *program, const void *boot_code) {
         /* Uncompress the program image. */
-        Uncompress(secmon::MemoryRegionPhysicalTzramFullProgramImage.GetPointer(), secmon::MemoryRegionPhysicalTzramFullProgramImage.GetSize(), program_lz4, program_lz4_size);
+        Uncompress(secmon::MemoryRegionPhysicalTzramFullProgramImage.GetPointer(), secmon::MemoryRegionPhysicalTzramFullProgramImage.GetSize(), program, program_lz4_size);
 
         /* Copy the boot image to the end of IRAM */
         u8 *relocated_boot_code = secmon::MemoryRegionPhysicalIramBootCodeImage.GetEndPointer<u8>() - boot_code_lz4_size;
-        std::memcpy(relocated_boot_code, boot_code_lz4, boot_code_lz4_size);
+        std::memcpy(relocated_boot_code, boot_code, boot_code_lz4_size);
 
         /* Uncompress the boot image. */
         Uncompress(secmon::MemoryRegionPhysicalIramBootCodeImage.GetPointer(), secmon::MemoryRegionPhysicalIramBootCodeImage.GetSize(), relocated_boot_code, boot_code_lz4_size);

exosphere/loader_stub/source/start.s

@@ -98,8 +98,8 @@ _start:
     ldr x20, =0x7C020000
     mov sp, x20
 
-    /* Call our init array functions. */
+    adr x0, program_lz4
-    bl __libc_init_array
+    adr x1, boot_code_lz4
 
     /* Uncompress the program and iram boot code images. */
-    b _ZN3ams6secmon6loader20UncompressAndExecuteEv
+    b _ZN3ams6secmon6loader20UncompressAndExecuteEPKvS3_

exosphere/mariko_fatal/source/fatal_display.hpp

@@ -23,6 +23,7 @@ namespace ams::secmon::fatal {
     constexpr inline size_t FrameBufferSize   = FrameBufferHeight * FrameBufferWidth * sizeof(u32);
 
     void InitializeDisplay();
+    void ShowDisplay();
     void ShowDisplay(const ams::impl::FatalErrorContext *f_ctx, const Result save_result);
 
 }

exosphere/mariko_fatal/source/fs/fatal_fs_api.cpp

@@ -104,13 +104,13 @@ namespace ams::fs {
 
     bool MountSdCard() {
         AMS_ASSERT(!g_is_sd_mounted);
-        g_is_sd_mounted = f_mount(std::addressof(g_sd_fs), "", 1) == FR_OK;
+        g_is_sd_mounted = f_mount(std::addressof(g_sd_fs), "sdmc", 1) == FR_OK;
         return g_is_sd_mounted;
     }
 
     void UnmountSdCard() {
         AMS_ASSERT(g_is_sd_mounted);
-        f_unmount("");
+        f_unmount("sdmc");
         g_is_sd_mounted = false;
     }
 

exosphere/program/program.ld

@@ -176,13 +176,11 @@ SECTIONS
         KEEP (*(.warmboot.text.start)) /* Should be first */
         KEEP (*(.warmboot.text*))
         KEEP(secmon_setup_warm.o(.text*))
-        KEEP(tsec_*.o(.text*))
+        KEEP(*(.text._ZN3ams4tsec4LockEv))
         KEEP (*(.warmboot.rodata*))
         KEEP(secmon_setup_warm.o(.rodata*))
-        KEEP(tsec_*.o(.rodata*))
         KEEP (*(.warmboot.data*))
         KEEP(secmon_setup_warm.o(.data*))
-        KEEP(tsec_*.o(.data*))
     } >warmboot_text AT>glob
 
 	.text ORIGIN(main) + SIZEOF(.vectors) + SIZEOF(.warmboot) :

exosphere/program/sc7fw/source/sc7fw_main.cpp

@@ -58,8 +58,8 @@ namespace ams::sc7fw {
 
         void EnterSc7() {
             /* Disable read buffering and write buffering in the BPMP cache. */
-            reg::ReadWrite(AVP_CACHE_ADDRESS(AVP_CACHE_CONFIG), AVP_CACHE_REG_BITS_ENUM(DISABLE_WB, TRUE),
+            reg::ReadWrite(AVP_CACHE_ADDR(AVP_CACHE_CONFIG), AVP_CACHE_REG_BITS_ENUM(CONFIG_DISABLE_WB, TRUE),
-                                                                AVP_CACHE_REG_BITS_ENUM(DISABLE_RB, TRUE));
+                                                             AVP_CACHE_REG_BITS_ENUM(CONFIG_DISABLE_RB, TRUE));
 
             /* Ensure the CPU Rail is turned off. */
             DisableCrail();

exosphere/program/source/boot/secmon_boot_key_data.s

@@ -85,10 +85,10 @@ _ZN3ams6secmon4boot15VolatileKeyDataE:
 /* We can get away with only including latest because exosphere supports newer-than-expected master key in engine. */
 /* TODO: Update on next change of keys. */
 /* Mariko Development Master Kek Source. */
-.byte 0xF9, 0x37, 0xCF, 0x9A, 0xBD, 0x86, 0xBB, 0xA9, 0x9C, 0x9E, 0x03, 0xC4, 0xFC, 0xBC, 0x3B, 0xCE
+.byte 0x75, 0x2D, 0x2E, 0xF3, 0x2F, 0x3F, 0xFE, 0x65, 0xF4, 0xA9, 0x83, 0xB4, 0xED, 0x42, 0x63, 0xBA
 
 /* Mariko Production Master Kek Source. */
-.byte 0x0E, 0x44, 0x0C, 0xED, 0xB4, 0x36, 0xC0, 0x3F, 0xAA, 0x1D, 0xAE, 0xBF, 0x62, 0xB1, 0x09, 0x82
+.byte 0xE5, 0x41, 0xAC, 0xEC, 0xD1, 0xA7, 0xD1, 0xAB, 0xED, 0x03, 0x77, 0xF1, 0x27, 0xCA, 0xF8, 0xF1
 
 /* Development Master Key Vectors. */
 .byte 0x46, 0x22, 0xB4, 0x51, 0x9A, 0x7E, 0xA7, 0x7F, 0x62, 0xA1, 0x1F, 0x8F, 0xC5, 0x3A, 0xDB, 0xFE /* Zeroes encrypted with Master Key 00. */
@@ -102,6 +102,7 @@ _ZN3ams6secmon4boot15VolatileKeyDataE:
 .byte 0xEC, 0xE1, 0x46, 0x89, 0x37, 0xFD, 0xD2, 0x15, 0x8C, 0x3F, 0x24, 0x82, 0xEF, 0x49, 0x68, 0x04 /* Master key 07 encrypted with Master key 08. */
 .byte 0x43, 0x3D, 0xC5, 0x3B, 0xEF, 0x91, 0x02, 0x21, 0x61, 0x54, 0x63, 0x8A, 0x35, 0xE7, 0xCA, 0xEE /* Master key 08 encrypted with Master key 09. */
 .byte 0x6C, 0x2E, 0xCD, 0xB3, 0x34, 0x61, 0x77, 0xF5, 0xF9, 0xB1, 0xDD, 0x61, 0x98, 0x19, 0x3E, 0xD4 /* Master key 09 encrypted with Master key 0A. */
+.byte 0x21, 0x88, 0x6B, 0x10, 0x9E, 0x83, 0xD6, 0x52, 0xAB, 0x08, 0xDB, 0x6D, 0x39, 0xFF, 0x1C, 0x9C /* Master key 0A encrypted with Master key 0B. */
 
 /* Production Master Key Vectors. */
 .byte 0x0C, 0xF0, 0x59, 0xAC, 0x85, 0xF6, 0x26, 0x65, 0xE1, 0xE9, 0x19, 0x55, 0xE6, 0xF2, 0x67, 0x3D /* Zeroes encrypted with Master Key 00. */
@@ -115,33 +116,37 @@ _ZN3ams6secmon4boot15VolatileKeyDataE:
 .byte 0xEA, 0x60, 0xB3, 0xEA, 0xCE, 0x8F, 0x24, 0x46, 0x7D, 0x33, 0x9C, 0xD1, 0xBC, 0x24, 0x98, 0x29 /* Master key 07 encrypted with Master key 08. */
 .byte 0x4D, 0xD9, 0x98, 0x42, 0x45, 0x0D, 0xB1, 0x3C, 0x52, 0x0C, 0x9A, 0x44, 0xBB, 0xAD, 0xAF, 0x80 /* Master key 08 encrypted with Master key 09. */
 .byte 0xB8, 0x96, 0x9E, 0x4A, 0x00, 0x0D, 0xD6, 0x28, 0xB3, 0xD1, 0xDB, 0x68, 0x5F, 0xFB, 0xE1, 0x2A /* Master key 09 encrypted with Master key 0A. */
+.byte 0xC1, 0x8D, 0x16, 0xBB, 0x2A, 0xE4, 0x1D, 0xD4, 0xC2, 0xC1, 0xB6, 0x40, 0x94, 0x35, 0x63, 0x98 /* Master key 0A encrypted with Master key 0B. */
 
 /* Device Master Key Source Sources. */
-.byte 0x8B, 0x4E, 0x1C, 0x22, 0x42, 0x07, 0xC8, 0x73, 0x56, 0x94, 0x08, 0x8B, 0xCC, 0x47, 0x0F, 0x5D /* 4.0.0 Device Master Key Source Source. */
+.byte 0x8B, 0x4E, 0x1C, 0x22, 0x42, 0x07, 0xC8, 0x73, 0x56, 0x94, 0x08, 0x8B, 0xCC, 0x47, 0x0F, 0x5D /* 4.0.0  Device Master Key Source Source. */
-.byte 0x6C, 0xEF, 0xC6, 0x27, 0x8B, 0xEC, 0x8A, 0x91, 0x99, 0xAB, 0x24, 0xAC, 0x4F, 0x1C, 0x8F, 0x1C /* 5.0.0 Device Master Key Source Source. */
+.byte 0x6C, 0xEF, 0xC6, 0x27, 0x8B, 0xEC, 0x8A, 0x91, 0x99, 0xAB, 0x24, 0xAC, 0x4F, 0x1C, 0x8F, 0x1C /* 5.0.0  Device Master Key Source Source. */
-.byte 0x70, 0x08, 0x1B, 0x97, 0x44, 0x64, 0xF8, 0x91, 0x54, 0x9D, 0xC6, 0x84, 0x8F, 0x1A, 0xB2, 0xE4 /* 6.0.0 Device Master Key Source Source. */
+.byte 0x70, 0x08, 0x1B, 0x97, 0x44, 0x64, 0xF8, 0x91, 0x54, 0x9D, 0xC6, 0x84, 0x8F, 0x1A, 0xB2, 0xE4 /* 6.0.0  Device Master Key Source Source. */
-.byte 0x8E, 0x09, 0x1F, 0x7A, 0xBB, 0xCA, 0x6A, 0xFB, 0xB8, 0x9B, 0xD5, 0xC1, 0x25, 0x9C, 0xA9, 0x17 /* 6.2.0 Device Master Key Source Source. */
+.byte 0x8E, 0x09, 0x1F, 0x7A, 0xBB, 0xCA, 0x6A, 0xFB, 0xB8, 0x9B, 0xD5, 0xC1, 0x25, 0x9C, 0xA9, 0x17 /* 6.2.0  Device Master Key Source Source. */
-.byte 0x8F, 0x77, 0x5A, 0x96, 0xB0, 0x94, 0xFD, 0x8D, 0x28, 0xE4, 0x19, 0xC8, 0x16, 0x1C, 0xDB, 0x3D /* 7.0.0 Device Master Key Source Source. */
+.byte 0x8F, 0x77, 0x5A, 0x96, 0xB0, 0x94, 0xFD, 0x8D, 0x28, 0xE4, 0x19, 0xC8, 0x16, 0x1C, 0xDB, 0x3D /* 7.0.0  Device Master Key Source Source. */
-.byte 0x67, 0x62, 0xD4, 0x8E, 0x55, 0xCF, 0xFF, 0x41, 0x31, 0x15, 0x3B, 0x24, 0x0C, 0x7C, 0x07, 0xAE /* 8.1.0 Device Master Key Source Source. */
+.byte 0x67, 0x62, 0xD4, 0x8E, 0x55, 0xCF, 0xFF, 0x41, 0x31, 0x15, 0x3B, 0x24, 0x0C, 0x7C, 0x07, 0xAE /* 8.1.0  Device Master Key Source Source. */
-.byte 0x4A, 0xC3, 0x4E, 0x14, 0x8B, 0x96, 0x4A, 0xD5, 0xD4, 0x99, 0x73, 0xC4, 0x45, 0xAB, 0x8B, 0x49 /* 9.0.0 Device Master Key Source Source. */
+.byte 0x4A, 0xC3, 0x4E, 0x14, 0x8B, 0x96, 0x4A, 0xD5, 0xD4, 0x99, 0x73, 0xC4, 0x45, 0xAB, 0x8B, 0x49 /* 9.0.0  Device Master Key Source Source. */
-.byte 0x14, 0xB8, 0x74, 0x12, 0xCB, 0xBD, 0x0B, 0x8F, 0x20, 0xFB, 0x30, 0xDA, 0x27, 0xE4, 0x58, 0x94 /* 9.1.0 Device Master Key Source Source. */
+.byte 0x14, 0xB8, 0x74, 0x12, 0xCB, 0xBD, 0x0B, 0x8F, 0x20, 0xFB, 0x30, 0xDA, 0x27, 0xE4, 0x58, 0x94 /* 9.1.0  Device Master Key Source Source. */
+.byte 0xAA, 0xFD, 0xBC, 0xBB, 0x25, 0xC3, 0xA4, 0xEF, 0xE3, 0xEE, 0x58, 0x53, 0xB7, 0xF8, 0xDD, 0xD6 /* 12.1.0 Device Master Key Source Source. */
 
 /* Development Device Master Kek Sources. */
-.byte 0xD6, 0xBD, 0x9F, 0xC6, 0x18, 0x09, 0xE1, 0x96, 0x20, 0x39, 0x60, 0xD2, 0x89, 0x83, 0x31, 0x34 /* 4.0.0 Device Master Kek Source. */
+.byte 0xD6, 0xBD, 0x9F, 0xC6, 0x18, 0x09, 0xE1, 0x96, 0x20, 0x39, 0x60, 0xD2, 0x89, 0x83, 0x31, 0x34 /* 4.0.0  Device Master Kek Source. */
-.byte 0x59, 0x2D, 0x20, 0x69, 0x33, 0xB5, 0x17, 0xBA, 0xCF, 0xB1, 0x4E, 0xFD, 0xE4, 0xC2, 0x7B, 0xA8 /* 5.0.0 Device Master Kek Source. */
+.byte 0x59, 0x2D, 0x20, 0x69, 0x33, 0xB5, 0x17, 0xBA, 0xCF, 0xB1, 0x4E, 0xFD, 0xE4, 0xC2, 0x7B, 0xA8 /* 5.0.0  Device Master Kek Source. */
-.byte 0xF6, 0xD8, 0x59, 0x63, 0x8F, 0x47, 0xCB, 0x4A, 0xD8, 0x74, 0x05, 0x7F, 0x88, 0x92, 0x33, 0xA5 /* 6.0.0 Device Master Kek Source. */
+.byte 0xF6, 0xD8, 0x59, 0x63, 0x8F, 0x47, 0xCB, 0x4A, 0xD8, 0x74, 0x05, 0x7F, 0x88, 0x92, 0x33, 0xA5 /* 6.0.0  Device Master Kek Source. */
-.byte 0x20, 0xAB, 0xF2, 0x0F, 0x05, 0xE3, 0xDE, 0x2E, 0xA1, 0xFB, 0x37, 0x5E, 0x8B, 0x22, 0x1A, 0x38 /* 6.2.0 Device Master Kek Source. */
+.byte 0x20, 0xAB, 0xF2, 0x0F, 0x05, 0xE3, 0xDE, 0x2E, 0xA1, 0xFB, 0x37, 0x5E, 0x8B, 0x22, 0x1A, 0x38 /* 6.2.0  Device Master Kek Source. */
-.byte 0x60, 0xAE, 0x56, 0x68, 0x11, 0xE2, 0x0C, 0x99, 0xDE, 0x05, 0xAE, 0x68, 0x78, 0x85, 0x04, 0xAE /* 7.0.0 Device Master Kek Source. */
+.byte 0x60, 0xAE, 0x56, 0x68, 0x11, 0xE2, 0x0C, 0x99, 0xDE, 0x05, 0xAE, 0x68, 0x78, 0x85, 0x04, 0xAE /* 7.0.0  Device Master Kek Source. */
-.byte 0x94, 0xD6, 0xA8, 0xC0, 0x95, 0xAF, 0xD0, 0xA6, 0x27, 0x53, 0x5E, 0xE5, 0x8E, 0x70, 0x1F, 0x87 /* 8.1.0 Device Master Kek Source. */
+.byte 0x94, 0xD6, 0xA8, 0xC0, 0x95, 0xAF, 0xD0, 0xA6, 0x27, 0x53, 0x5E, 0xE5, 0x8E, 0x70, 0x1F, 0x87 /* 8.1.0  Device Master Kek Source. */
-.byte 0x61, 0x6A, 0x88, 0x21, 0xA3, 0x52, 0xB0, 0x19, 0x16, 0x25, 0xA4, 0xE3, 0x4C, 0x54, 0x02, 0x0F /* 9.0.0 Device Master Kek Source. */
+.byte 0x61, 0x6A, 0x88, 0x21, 0xA3, 0x52, 0xB0, 0x19, 0x16, 0x25, 0xA4, 0xE3, 0x4C, 0x54, 0x02, 0x0F /* 9.0.0  Device Master Kek Source. */
-.byte 0x9D, 0xB1, 0xAE, 0xCB, 0xF6, 0xF6, 0xE3, 0xFE, 0xAB, 0x6F, 0xCB, 0xAF, 0x38, 0x03, 0xFC, 0x7B /* 9.1.0 Device Master Kek Source. */
+.byte 0x9D, 0xB1, 0xAE, 0xCB, 0xF6, 0xF6, 0xE3, 0xFE, 0xAB, 0x6F, 0xCB, 0xAF, 0x38, 0x03, 0xFC, 0x7B /* 9.1.0  Device Master Kek Source. */
+.byte 0xC4, 0xBB, 0xF3, 0x9F, 0xA3, 0xAA, 0x00, 0x99, 0x7C, 0x97, 0xAD, 0x91, 0x8F, 0xE8, 0x45, 0xCB /* 12.1.0 Device Master Kek Source. */
 
 /* Production Device Master Kek Sources. */
-.byte 0x88, 0x62, 0x34, 0x6E, 0xFA, 0xF7, 0xD8, 0x3F, 0xE1, 0x30, 0x39, 0x50, 0xF0, 0xB7, 0x5D, 0x5D /* 4.0.0 Device Master Kek Source. */
+.byte 0x88, 0x62, 0x34, 0x6E, 0xFA, 0xF7, 0xD8, 0x3F, 0xE1, 0x30, 0x39, 0x50, 0xF0, 0xB7, 0x5D, 0x5D /* 4.0.0  Device Master Kek Source. */
-.byte 0x06, 0x1E, 0x7B, 0xE9, 0x6D, 0x47, 0x8C, 0x77, 0xC5, 0xC8, 0xE7, 0x94, 0x9A, 0xA8, 0x5F, 0x2E /* 5.0.0 Device Master Kek Source. */
+.byte 0x06, 0x1E, 0x7B, 0xE9, 0x6D, 0x47, 0x8C, 0x77, 0xC5, 0xC8, 0xE7, 0x94, 0x9A, 0xA8, 0x5F, 0x2E /* 5.0.0  Device Master Kek Source. */
-.byte 0x99, 0xFA, 0x98, 0xBD, 0x15, 0x1C, 0x72, 0xFD, 0x7D, 0x9A, 0xD5, 0x41, 0x00, 0xFD, 0xB2, 0xEF /* 6.0.0 Device Master Kek Source. */
+.byte 0x99, 0xFA, 0x98, 0xBD, 0x15, 0x1C, 0x72, 0xFD, 0x7D, 0x9A, 0xD5, 0x41, 0x00, 0xFD, 0xB2, 0xEF /* 6.0.0  Device Master Kek Source. */
-.byte 0x81, 0x3C, 0x6C, 0xBF, 0x5D, 0x21, 0xDE, 0x77, 0x20, 0xD9, 0x6C, 0xE3, 0x22, 0x06, 0xAE, 0xBB /* 6.2.0 Device Master Kek Source. */
+.byte 0x81, 0x3C, 0x6C, 0xBF, 0x5D, 0x21, 0xDE, 0x77, 0x20, 0xD9, 0x6C, 0xE3, 0x22, 0x06, 0xAE, 0xBB /* 6.2.0  Device Master Kek Source. */
-.byte 0x86, 0x61, 0xB0, 0x16, 0xFA, 0x7A, 0x9A, 0xEA, 0xF6, 0xF5, 0xBE, 0x1A, 0x13, 0x5B, 0x6D, 0x9E /* 7.0.0 Device Master Kek Source. */
+.byte 0x86, 0x61, 0xB0, 0x16, 0xFA, 0x7A, 0x9A, 0xEA, 0xF6, 0xF5, 0xBE, 0x1A, 0x13, 0x5B, 0x6D, 0x9E /* 7.0.0  Device Master Kek Source. */
-.byte 0xA6, 0x81, 0x71, 0xE7, 0xB5, 0x23, 0x74, 0xB0, 0x39, 0x8C, 0xB7, 0xFF, 0xA0, 0x62, 0x9F, 0x8D /* 8.1.0 Device Master Kek Source. */
+.byte 0xA6, 0x81, 0x71, 0xE7, 0xB5, 0x23, 0x74, 0xB0, 0x39, 0x8C, 0xB7, 0xFF, 0xA0, 0x62, 0x9F, 0x8D /* 8.1.0  Device Master Kek Source. */
-.byte 0x03, 0xE7, 0xEB, 0x43, 0x1B, 0xCF, 0x5F, 0xB5, 0xED, 0xDC, 0x97, 0xAE, 0x21, 0x8D, 0x19, 0xED /* 9.0.0 Device Master Kek Source. */
+.byte 0x03, 0xE7, 0xEB, 0x43, 0x1B, 0xCF, 0x5F, 0xB5, 0xED, 0xDC, 0x97, 0xAE, 0x21, 0x8D, 0x19, 0xED /* 9.0.0  Device Master Kek Source. */
-.byte 0xCE, 0xFE, 0x41, 0x0F, 0x46, 0x9A, 0x30, 0xD6, 0xF2, 0xE9, 0x0C, 0x6B, 0xB7, 0x15, 0x91, 0x36 /* 9.1.0 Device Master Kek Source. */
+.byte 0xCE, 0xFE, 0x41, 0x0F, 0x46, 0x9A, 0x30, 0xD6, 0xF2, 0xE9, 0x0C, 0x6B, 0xB7, 0x15, 0x91, 0x36 /* 9.1.0  Device Master Kek Source. */
+.byte 0xC2, 0x65, 0x34, 0x6E, 0xC7, 0xC6, 0x5D, 0x97, 0x3E, 0x34, 0x5C, 0x6B, 0xB3, 0x7E, 0xC6, 0xE3 /* 12.1.0 Device Master Kek Source. */

exosphere/program/source/boot/secmon_main.cpp

@@ -80,6 +80,8 @@ namespace ams::secmon {
 
             /* Alert the bootloader that we're initialized. */
             secmon_params.secmon_state = pkg1::SecureMonitorState_Initialized;
+            hw::FlushDataCache(std::addressof(secmon_params.secmon_state), sizeof(secmon_params.secmon_state));
+            hw::DataSynchronizationBarrierInnerShareable();
         }
 
         /* Wait for NX Bootloader to finish loading the BootConfig. */

exosphere/program/source/boot/secmon_package2.cpp

@@ -94,7 +94,7 @@ namespace ams::secmon::boot {
         }
 
         /* Check that the key generation is one that we can use. */
-        static_assert(pkg1::KeyGeneration_Count == 11);
+        static_assert(pkg1::KeyGeneration_Count == 12);
         if (key_generation >= pkg1::KeyGeneration_Count) {
             return false;
         }
@@ -154,8 +154,11 @@ namespace ams::secmon::boot {
     bool VerifyPackage2Payloads(const pkg2::Package2Meta &meta, uintptr_t payload_address) {
         /* Verify hashes match for all payloads. */
         for (int i = 0; i < pkg2::PayloadCount; ++i) {
-            if (!VerifyHash(meta.payload_hashes[i], payload_address, meta.payload_sizes[i])) {
+            /* Allow all-zero bytes to match any payload. */
-                return false;
+            if (!(meta.payload_hashes[i][0] == 0 && std::memcmp(meta.payload_hashes[i] + 0, meta.payload_hashes[i] + 1, sizeof(meta.payload_hashes[i]) - 1) == 0)) {
+                if (!VerifyHash(meta.payload_hashes[i], payload_address, meta.payload_sizes[i])) {
+                    return false;
+                }
             }
 
             payload_address += meta.payload_sizes[i];

exosphere/program/source/secmon_setup.cpp

@@ -475,8 +475,8 @@ namespace ams::secmon {
 
             /* Lock cluster switching, to prevent usage of the A53 cores. */
             reg::Write(FLOW_CTLR + FLOW_CTLR_BPMP_CLUSTER_CONTROL, FLOW_REG_BITS_ENUM(BPMP_CLUSTER_CONTROL_ACTIVE_CLUSTER_LOCK,    ENABLE),
-                                                                FLOW_REG_BITS_ENUM(BPMP_CLUSTER_CONTROL_CLUSTER_SWITCH_ENABLE, DISABLE),
+                                                                   FLOW_REG_BITS_ENUM(BPMP_CLUSTER_CONTROL_CLUSTER_SWITCH_ENABLE, DISABLE),
-                                                                FLOW_REG_BITS_ENUM(BPMP_CLUSTER_CONTROL_ACTIVE_CLUSTER,           FAST));
+                                                                   FLOW_REG_BITS_ENUM(BPMP_CLUSTER_CONTROL_ACTIVE_CLUSTER,           FAST));
 
             /* Enable flow controller debug qualifier for legacy FIQs. */
             reg::Write(FLOW_CTLR + FLOW_CTLR_FLOW_DBG_QUAL, FLOW_REG_BITS_ENUM(FLOW_DBG_QUAL_FIQ2CCPLEX_ENABLE, ENABLE));
@@ -600,8 +600,8 @@ namespace ams::secmon {
                 g_kernel_carveouts[0].size = 200 * 128_KB;
             }
 
-            /* Configure the two kernel carveouts. */
+            /* NOTE: Here Nintendo configures the two kernel carveouts; we will do this later, to allow fusee to continue using AVP_CACHE. */
-            SetupKernelCarveouts();
+            /* SetupKernelCarveouts(); */
 
             /* Configure slave register security. */
             ConfigureSlaveSecurity();
@@ -833,7 +833,7 @@ namespace ams::secmon {
             #define MC_ENABLE_CLIENT_ACCESS(INDEX, WHICH) MC_REG_BITS_ENUM(CLIENT_ACCESS##INDEX##_##WHICH, ENABLE)
 
             constexpr u32 WarmbootCarveoutClientAccess0     = reg::Encode(MC_ENABLE_CLIENT_ACCESS(0, AVPCARM7R),
-                                                          MC_ENABLE_CLIENT_ACCESS(0, PPCSAHBSLVR));
+                                                                          MC_ENABLE_CLIENT_ACCESS(0, PPCSAHBSLVR));
 
             constexpr u32 WarmbootCarveoutClientAccess1     = reg::Encode(MC_ENABLE_CLIENT_ACCESS(1, AVPCARM7W));
 
@@ -1164,6 +1164,9 @@ namespace ams::secmon {
         /* Setup the GPU carveout. */
         SetupGpuCarveout();
 
+        /* Configure the two kernel carveouts. */
+        SetupKernelCarveouts();
+
         /* Disable the ARC. */
         DisableArc();
 

exosphere/program/source/smc/secmon_smc_aes.cpp

@@ -272,7 +272,19 @@ namespace ams::secmon::smc {
 
         void GetSecureDataImpl(u8 *dst, SecureData which, bool tweak) {
             /* Compute the appropriate AES-CTR. */
-            se::ComputeAes128Ctr(dst, AesKeySize, pkg1::AesKeySlot_Device, SecureDataSource, AesKeySize, GetSecureDataCounter(which), AesKeySize);
+            {
+                /* Ensure that the SE sees consistent data. */
+                hw::FlushDataCache(dst, AesKeySize);
+                hw::DataSynchronizationBarrierInnerShareable();
+
+                /* Perform the appropriate AES operation. */
+                se::ComputeAes128Ctr(dst, AesKeySize, pkg1::AesKeySlot_Device, SecureDataSource, AesKeySize, GetSecureDataCounter(which), AesKeySize);
+                hw::DataSynchronizationBarrierInnerShareable();
+
+                /* Ensure the CPU sees consistent data. */
+                hw::FlushDataCache(dst, AesKeySize);
+                hw::DataSynchronizationBarrierInnerShareable();
+            }
 
             /* Tweak, if we should. */
             if (tweak) {

exosphere/program/source/smc/secmon_smc_info.cpp

@@ -243,7 +243,7 @@ namespace ams::secmon::smc {
                                 (static_cast<u64>(ATMOSPHERE_RELEASE_VERSION_MINOR & 0xFF) << 48) |
                                 (static_cast<u64>(ATMOSPHERE_RELEASE_VERSION_MICRO & 0xFF) << 40) |
                                 (static_cast<u64>(GetKeyGeneration())                      << 32) |
-                                (static_cast<u64>(GetTargetFirmware())                     << 00);
+                                (static_cast<u64>(GetTargetFirmware())                     <<  0);
                     break;
                 case ConfigItem::ExosphereNeedsReboot:
                     /* We are executing, so we aren't in the process of rebooting. */
@@ -290,6 +290,12 @@ namespace ams::secmon::smc {
                     /* Get whether usb 3.0 should be force-enabled. */
                     args.r[1] = GetSecmonConfiguration().IsUsb30ForceEnabled();
                     break;
+                case ConfigItem::ExosphereSupportedHosVersion:
+                    /* Get information about the supported hos version. */
+                    args.r[1] = (static_cast<u64>(ATMOSPHERE_SUPPORTED_HOS_VERSION_MAJOR & 0xFF) << 24) |
+                                (static_cast<u64>(ATMOSPHERE_SUPPORTED_HOS_VERSION_MINOR & 0xFF) << 16) |
+                                (static_cast<u64>(ATMOSPHERE_SUPPORTED_HOS_VERSION_MICRO & 0xFF) <<  8);
+                    break;
                 default:
                     return SmcResult::InvalidArgument;
             }

exosphere/program/source/smc/secmon_smc_info.hpp

@@ -40,17 +40,18 @@ namespace ams::secmon::smc {
         Package2Hash                  = 17,
 
         /* Extension config items for exosphere. */
-        ExosphereApiVersion       = 65000,
+        ExosphereApiVersion          = 65000,
-        ExosphereNeedsReboot      = 65001,
+        ExosphereNeedsReboot         = 65001,
-        ExosphereNeedsShutdown    = 65002,
+        ExosphereNeedsShutdown       = 65002,
-        ExosphereGitCommitHash    = 65003,
+        ExosphereGitCommitHash       = 65003,
-        ExosphereHasRcmBugPatch   = 65004,
+        ExosphereHasRcmBugPatch      = 65004,
-        ExosphereBlankProdInfo    = 65005,
+        ExosphereBlankProdInfo       = 65005,
-        ExosphereAllowCalWrites   = 65006,
+        ExosphereAllowCalWrites      = 65006,
-        ExosphereEmummcType       = 65007,
+        ExosphereEmummcType          = 65007,
-        ExospherePayloadAddress   = 65008,
+        ExospherePayloadAddress      = 65008,
-        ExosphereLogConfiguration = 65009,
+        ExosphereLogConfiguration    = 65009,
-        ExosphereForceEnableUsb30 = 65010,
+        ExosphereForceEnableUsb30    = 65010,
+        ExosphereSupportedHosVersion = 65011,
     };
 
     SmcResult SmcGetConfigUser(SmcArguments &args);

fusee/Makefile

@@ -1,10 +1,44 @@
-SUBFOLDERS := fusee-primary fusee-mtc fusee-secondary
+ATMOSPHERE_BUILD_CONFIGS :=
+all: release
 
-TOPTARGETS := all clean
+define ATMOSPHERE_ADD_TARGET
 
-$(TOPTARGETS): $(SUBFOLDERS)
+ATMOSPHERE_BUILD_CONFIGS += $(strip $1)
 
-$(SUBFOLDERS):
+$(strip $1): fusee$(strip $2).bin
-	$(MAKE) -C $@ $(MAKECMDGOALS)
 
-.PHONY: $(TOPTARGETS) $(SUBFOLDERS)
+fusee$(strip $2).bin: loader_stub/loader_stub$(strip $2).bin
+	@cp loader_stub/loader_stub$(strip $2).bin fusee$(strip $2).bin
+	@echo "Built fusee$(strip $2).bin..."
+
+check_program_$(strip $1):
+	@$$(MAKE) -C program $(strip $1)
+
+loader_stub/loader_stub$(strip $2).bin: check_program_$(strip $1)
+	@$$(MAKE) -C loader_stub $(strip $1)
+
+clean-$(strip $1): clean-program-$(strip $1) clean-loader_stub-$(strip $1)
+	@rm -rf fusee$(strip $2).bin
+
+clean-program-$(strip $1):
+	@$$(MAKE) -C program clean-$(strip $1)
+
+clean-loader_stub-$(strip $1):
+	@$$(MAKE) -C loader_stub clean-$(strip $1)
+
+endef
+
+$(eval $(call ATMOSPHERE_ADD_TARGET, release, ))
+$(eval $(call ATMOSPHERE_ADD_TARGET, debug, _debug))
+$(eval $(call ATMOSPHERE_ADD_TARGET, audit, _audit))
+
+clean: clean-program clean-loader_stub
+	@rm -rf fusee*.bin package3*
+
+clean-program:
+	@$(MAKE) -C program clean
+
+clean-loader_stub:
+	@$(MAKE) -C loader_stub clean
+
+.PHONY: all clean clean-program clean-loader_stub $(foreach config,$(ATMOSPHERE_BUILD_CONFIGS),check_program_$(config) check_warmboot_$(strip $1) clean-$(config) clean-program-$(config) clean-loader_stub-$(config) clean-warmboot-$(config))

fusee/build_package3.py

@@ -0,0 +1,201 @@
+#!/usr/bin/env python
+import sys, lz4, hashlib, os
+from struct import unpack as up, pack as pk
+
+def lz4_compress(data):
+    try:
+        import lz4.block as block
+    except ImportError:
+        block = lz4.LZ4_compress
+    return block.compress(data, 'high_compression', store_size=False)
+
+def read_file(fn):
+    with open(fn, 'rb') as f:
+        return f.read()
+
+def pad(data, size):
+    assert len(data) <= size
+    return (data + '\x00' * size)[:size]
+
+def get_overlay(program, i):
+    return program[0x2B000 + 0x14000 * i:0x2B000 + 0x14000 * (i+1)]
+
+KIP_NAMES = ['Loader', 'NCM', 'ProcessManager', 'sm', 'boot', 'spl', 'ams_mitm']
+
+def get_kips(ams_dir):
+    emummc   = read_file(os.path.join(ams_dir, 'emummc/emummc_unpacked.kip'))
+    loader   = read_file(os.path.join(ams_dir, 'stratosphere/loader/loader.kip'))
+    ncm      = read_file(os.path.join(ams_dir, 'stratosphere/ncm/ncm.kip'))
+    pm       = read_file(os.path.join(ams_dir, 'stratosphere/pm/pm.kip'))
+    sm       = read_file(os.path.join(ams_dir, 'stratosphere/sm/sm.kip'))
+    boot     = read_file(os.path.join(ams_dir, 'stratosphere/boot/boot.kip'))
+    spl      = read_file(os.path.join(ams_dir, 'stratosphere/spl/spl.kip'))
+    ams_mitm = read_file(os.path.join(ams_dir, 'stratosphere/ams_mitm/ams_mitm.kip'))
+    return (emummc, {
+        'Loader' : loader,
+        'NCM' : ncm,
+        'ProcessManager' : pm,
+        'sm' : sm,
+        'boot' : boot,
+        'spl' : spl,
+        'ams_mitm' : ams_mitm,
+    })
+
+def write_kip_meta(f, kip, ofs):
+    # Write program id
+    f.write(kip[0x10:0x18])
+    # Write offset, size
+    f.write(pk('<II', ofs - 0x100000, len(kip)))
+    # Write hash
+    f.write(hashlib.sha256(kip).digest())
+
+def write_header(f, all_kips, wb_size, tk_size, xf_size, ex_size, ms_size, fs_size, rb_size, git_revision, major, minor, micro, relstep, s_major, s_minor, s_micro, s_relstep):
+    # Unpack kips
+    emummc, kips = all_kips
+    # Write magic as PK31 magic.
+    f.write(b'PK31')
+    # Write metadata offset = 0x10
+    f.write(pk('<I', 0x20))
+    # Write flags
+    f.write(pk('<I', 0x00000000))
+    # Write meso_size
+    f.write(pk('<I', ms_size))
+    # Write num_kips
+    f.write(pk('<I', len(KIP_NAMES)))
+    # Write reserved1
+    f.write(b'\xCC' * 0xC)
+    # Write legacy magic
+    f.write(b'FSS0')
+    # Write total size
+    f.write(pk('<I', 0x800000))
+    # Write reserved2
+    f.write(pk('<I', 0xCCCCCCCC))
+    # Write content_header_offset
+    f.write(pk('<I', 0x40))
+    # Write num_content_headers;
+    f.write(pk('<I', 8 + len(KIP_NAMES)))
+    # Write supported_hos_version;
+    f.write(pk('<BBBB', s_relstep, s_micro, s_minor, s_major))
+    # Write release_version;
+    f.write(pk('<BBBB', relstep, micro, minor, major))
+    # Write git_revision;
+    f.write(pk('<I', git_revision))
+    # Write content metas
+    f.write(pk('<IIBBBBI16s', 0x000800, wb_size,  2, 0, 0, 0, 0xCCCCCCCC, 'warmboot'))
+    f.write(pk('<IIBBBBI16s', 0x002000, tk_size, 12, 0, 0, 0, 0xCCCCCCCC, 'tsec_keygen'))
+    f.write(pk('<IIBBBBI16s', 0x004000, xf_size, 11, 0, 0, 0, 0xCCCCCCCC, 'exosphere_fatal'))
+    f.write(pk('<IIBBBBI16s', 0x048000, ex_size,  1, 0, 0, 0, 0xCCCCCCCC, 'exosphere'))
+    f.write(pk('<IIBBBBI16s', 0x056000, ms_size, 10, 0, 0, 0, 0xCCCCCCCC, 'mesosphere'))
+    f.write(pk('<IIBBBBI16s', 0x7C0000, fs_size,  0, 0, 0, 0, 0xCCCCCCCC, 'fusee'))
+    f.write(pk('<IIBBBBI16s', 0x7E0000, rb_size,  3, 0, 0, 0, 0xCCCCCCCC, 'rebootstub'))
+    f.write(pk('<IIBBBBI16s', 0x100000, len(emummc),  8, 0, 0, 0, 0xCCCCCCCC, 'emummc'))
+    ofs = (0x100000 + len(emummc) + 0xF) & ~0xF
+    for kip_name in KIP_NAMES:
+        kip_data = kips[kip_name]
+        f.write(pk('<IIBBBBI16s', ofs, len(kip_data), 6, 0, 0, 0, 0xCCCCCCCC, kip_name))
+        ofs += len(kip_data)
+        ofs += 0xF
+        ofs &= ~0xF
+    # Pad to kip metas.
+    f.write(b'\xCC' * (0x400 - 0x40 - (0x20 * (8 + len(KIP_NAMES)))))
+    # Write emummc_meta. */
+    write_kip_meta(f, emummc, 0x100000)
+    # Write kip metas
+    ofs = (0x100000 + len(emummc) + 0xF) & ~0xF
+    for kip_name in KIP_NAMES:
+        kip_data = kips[kip_name]
+        write_kip_meta(f, kip_data, ofs)
+        ofs += len(kip_data)
+        ofs += 0xF
+        ofs &= ~0xF
+    # Pad to end of header
+    f.write(b'\xCC' * (0x800 - (0x400 + (1 + len(KIP_NAMES)) * 0x30)))
+
+def write_kips(f, all_kips):
+    # Unpack kips
+    emummc, kips = all_kips
+    # Write emummc
+    f.write(emummc)
+    # Write kips
+    tot = len(emummc)
+    if (tot & 0xF):
+        f.write('\xCC' * (0x10 - (tot & 0xF)))
+        tot += 0xF
+        tot &= ~0xF
+    for kip_name in KIP_NAMES:
+        kip_data = kips[kip_name]
+        f.write(kip_data)
+        tot += len(kip_data)
+        if (tot & 0xF):
+            f.write('\xCC' * (0x10 - (tot & 0xF)))
+            tot += 0xF
+            tot &= ~0xF
+    # Pad to 3 MB
+    f.write(b'\xCC' * (0x300000 - tot))
+
+def main(argc, argv):
+    if argc != 12:
+        print('Usage: %s ams_dir target revision major minor micro relstep s_major s_minor s_micro s_relstep' % argv[0])
+        return 1
+    # Parse arguments
+    ams_dir   = argv[1]
+    target    = '' if argv[2] == 'release' else ('_%s' % argv[2])
+    revision  = int(argv[3], 16)
+    major     = int(argv[4])
+    minor     = int(argv[5])
+    micro     = int(argv[6])
+    relstep   = int(argv[7])
+    s_major   = int(argv[8])
+    s_minor   = int(argv[9])
+    s_micro   = int(argv[10])
+    s_relstep = int(argv[11])
+    # Read/parse fusee
+    fusee_program = read_file(os.path.join(ams_dir, 'fusee/program/program%s.bin' % target))
+    fusee_bin     = read_file(os.path.join(ams_dir, 'fusee/fusee%s.bin' % target))
+    erista_mtc = get_overlay(fusee_program, 1)
+    mariko_mtc = get_overlay(fusee_program, 2)
+    erista_hsh = hashlib.sha256(erista_mtc[:-4]).digest()[:4]
+    mariko_hsh = hashlib.sha256(mariko_mtc[:-4]).digest()[:4]
+    # Read other files
+    exosphere    = read_file(os.path.join(ams_dir, 'exosphere/exosphere%s.bin' % target))
+    warmboot     = read_file(os.path.join(ams_dir, 'exosphere/warmboot%s.bin' % target))
+    mariko_fatal = read_file(os.path.join(ams_dir, 'exosphere/mariko_fatal%s.bin' % target))
+    rebootstub   = read_file(os.path.join(ams_dir, 'exosphere/program/rebootstub/rebootstub%s.bin' % target))
+    mesosphere   = read_file(os.path.join(ams_dir, 'mesosphere/mesosphere%s.bin' % target))
+    all_kips     = get_kips(ams_dir)
+    tsec_keygen  = read_file(os.path.join(ams_dir, 'fusee/program/tsec_keygen/tsec_keygen.bin'))
+    splash_bin   = read_file(os.path.join(ams_dir, 'img/splash.bin'))
+    assert len(splash_bin) == 0x3C0000
+    with open(os.path.join(ams_dir, 'fusee/package3%s' % target), 'wb') as f:
+        # Write header
+        write_header(f, all_kips, len(warmboot), len(tsec_keygen), len(mariko_fatal), len(exosphere), len(mesosphere), len(fusee_bin), len(rebootstub), revision, major, minor, micro, relstep, s_major, s_minor, s_micro, s_relstep)
+        # Write warmboot
+        f.write(pad(warmboot, 0x1800))
+        # Write TSEC Keygen
+        f.write(pad(tsec_keygen, 0x2000))
+        # Write Mariko Fatal
+        f.write(pad(mariko_fatal, 0x1C000))
+        # Write Erista MTC
+        f.write(erista_mtc[:-4] + erista_hsh)
+        # Write Mariko MTC
+        f.write(mariko_mtc[:-4] + mariko_hsh)
+        # Write exosphere
+        f.write(pad(exosphere, 0xE000))
+        # Write mesosphere
+        f.write(pad(mesosphere, 0xAA000))
+        # Write kips
+        write_kips(f, all_kips)
+        # Write Splash Screen
+        f.write(splash_bin)
+        # Write fusee
+        f.write(pad(fusee_bin, 0x20000))
+        # Write rebootstub
+        f.write(pad(rebootstub, 0x1000))
+        # Pad to 8 MB
+        f.write(b'\xCC' * (0x800000 - 0x7E1000))
+
+
+    return 0
+
+if __name__ == '__main__':
+    sys.exit(main(len(sys.argv), sys.argv))

fusee/common/display/video_fb.h

@@ -1,58 +0,0 @@
-/*
- * (C) Copyright 1997-2002 ELTEC Elektronik AG
- * Frank Gottschling <fgottschling@eltec.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _VIDEO_FB_H_
-#define _VIDEO_FB_H_
-
-#define CONSOLE_BG_COL            0x00
-#define CONSOLE_FG_COL            0xa0
-
-/* Try using the small font */
-#define CONFIG_VIDEO_FONT_SMALL
-
-/*
- * Graphic Data Format (GDF) bits for VIDEO_DATA_FORMAT
- */
-#define GDF__8BIT_INDEX         0
-#define GDF_15BIT_555RGB        1
-#define GDF_16BIT_565RGB        2
-#define GDF_32BIT_X888RGB       3
-#define GDF_24BIT_888RGB        4
-#define GDF__8BIT_332RGB        5
-
-#define CONFIG_VIDEO_FB_LITTLE_ENDIAN
-#define CONFIG_VIDEO_VISIBLE_COLS 720
-#define CONFIG_VIDEO_VISIBLE_ROWS 1280
-#define CONFIG_VIDEO_COLS         768
-#define CONFIG_VIDEO_PIXEL_SIZE   4
-#define CONFIG_VIDEO_DATA_FORMAT  GDF_32BIT_X888RGB /* BGR actually, but w/e */
-
-int video_get_col(void);
-int video_get_row(void);
-
-int video_init(void *fb);
-int video_resume(void *fb, int row, int col);
-void video_putc(char c);
-void video_puts(const char *s);
-
-#endif /*_VIDEO_FB_H_ */

fusee/common/fatfs/00history.txt

@@ -1,340 +0,0 @@
-----------------------------------------------------------------------------
-  Revision history of FatFs module
-----------------------------------------------------------------------------
-
-R0.00 (February 26, 2006)
-
-  Prototype.
-
-
-
-R0.01 (April 29, 2006)
-
-  The first release.
-
-
-
-R0.02 (June 01, 2006)
-
-  Added FAT12 support.
-  Removed unbuffered mode.
-  Fixed a problem on small (<32M) partition.
-
-
-
-R0.02a (June 10, 2006)
-
-  Added a configuration option (_FS_MINIMUM).
-
-
-
-R0.03 (September 22, 2006)
-
-  Added f_rename().
-  Changed option _FS_MINIMUM to _FS_MINIMIZE.
-
-
-
-R0.03a (December 11, 2006)
-
-  Improved cluster scan algorithm to write files fast.
-  Fixed f_mkdir() creates incorrect directory on FAT32.
-
-
-
-R0.04 (February 04, 2007)
-
-  Added f_mkfs().
-  Supported multiple drive system.
-  Changed some interfaces for multiple drive system.
-  Changed f_mountdrv() to f_mount().
-
-
-
-R0.04a (April 01, 2007)
-
-  Supported multiple partitions on a physical drive.
-  Added a capability of extending file size to f_lseek().
-  Added minimization level 3.
-  Fixed an endian sensitive code in f_mkfs().
-
-
-
-R0.04b (May 05, 2007)
-
-  Added a configuration option _USE_NTFLAG.
-  Added FSINFO support.
-  Fixed DBCS name can result FR_INVALID_NAME.
-  Fixed short seek (<= csize) collapses the file object.
-
-
-
-R0.05 (August 25, 2007)
-
-  Changed arguments of f_read(), f_write() and f_mkfs().
-  Fixed f_mkfs() on FAT32 creates incorrect FSINFO.
-  Fixed f_mkdir() on FAT32 creates incorrect directory.
-
-
-
-R0.05a (February 03, 2008)
-
-  Added f_truncate() and f_utime().
-  Fixed off by one error at FAT sub-type determination.
-  Fixed btr in f_read() can be mistruncated.
-  Fixed cached sector is not flushed when create and close without write.
-
-
-
-R0.06 (April 01, 2008)
-
-  Added fputc(), fputs(), fprintf() and fgets().
-  Improved performance of f_lseek() on moving to the same or following cluster.
-
-
-
-R0.07 (April 01, 2009)
-
-  Merged Tiny-FatFs as a configuration option. (_FS_TINY)
-  Added long file name feature. (_USE_LFN)
-  Added multiple code page feature. (_CODE_PAGE)
-  Added re-entrancy for multitask operation. (_FS_REENTRANT)
-  Added auto cluster size selection to f_mkfs().
-  Added rewind option to f_readdir().
-  Changed result code of critical errors.
-  Renamed string functions to avoid name collision.
-
-
-
-R0.07a (April 14, 2009)
-
-  Septemberarated out OS dependent code on reentrant cfg.
-  Added multiple sector size feature.
-
-
-
-R0.07c (June 21, 2009)
-
-  Fixed f_unlink() can return FR_OK on error.
-  Fixed wrong cache control in f_lseek().
-  Added relative path feature.
-  Added f_chdir() and f_chdrive().
-  Added proper case conversion to extended character.
-
-
-
-R0.07e (November 03, 2009)
-
-  Septemberarated out configuration options from ff.h to ffconf.h.
-  Fixed f_unlink() fails to remove a sub-directory on _FS_RPATH.
-  Fixed name matching error on the 13 character boundary.
-  Added a configuration option, _LFN_UNICODE.
-  Changed f_readdir() to return the SFN with always upper case on non-LFN cfg.
-
-
-
-R0.08 (May 15, 2010)
-
-  Added a memory configuration option. (_USE_LFN = 3)
-  Added file lock feature. (_FS_SHARE)
-  Added fast seek feature. (_USE_FASTSEEK)
-  Changed some types on the API, XCHAR->TCHAR.
-  Changed .fname in the FILINFO structure on Unicode cfg.
-  String functions support UTF-8 encoding files on Unicode cfg.
-
-
-
-R0.08a (August 16, 2010)
-
-  Added f_getcwd(). (_FS_RPATH = 2)
-  Added sector erase feature. (_USE_ERASE)
-  Moved file lock semaphore table from fs object to the bss.
-  Fixed f_mkfs() creates wrong FAT32 volume.
-
-
-
-R0.08b (January 15, 2011)
-
-  Fast seek feature is also applied to f_read() and f_write().
-  f_lseek() reports required table size on creating CLMP.
-  Extended format syntax of f_printf().
-  Ignores duplicated directory separators in given path name.
-
-
-
-R0.09 (September 06, 2011)
-
-  f_mkfs() supports multiple partition to complete the multiple partition feature.
-  Added f_fdisk().
-
-
-
-R0.09a (August 27, 2012)
-
-  Changed f_open() and f_opendir() reject null object pointer to avoid crash.
-  Changed option name _FS_SHARE to _FS_LOCK.
-  Fixed assertion failure due to OS/2 EA on FAT12/16 volume.
-
-
-
-R0.09b (January 24, 2013)
-
-  Added f_setlabel() and f_getlabel().
-
-
-
-R0.10 (October 02, 2013)
-
-  Added selection of character encoding on the file. (_STRF_ENCODE)
-  Added f_closedir().
-  Added forced full FAT scan for f_getfree(). (_FS_NOFSINFO)
-  Added forced mount feature with changes of f_mount().
-  Improved behavior of volume auto detection.
-  Improved write throughput of f_puts() and f_printf().
-  Changed argument of f_chdrive(), f_mkfs(), disk_read() and disk_write().
-  Fixed f_write() can be truncated when the file size is close to 4GB.
-  Fixed f_open(), f_mkdir() and f_setlabel() can return incorrect value on error.
-
-
-
-R0.10a (January 15, 2014)
-
-  Added arbitrary strings as drive number in the path name. (_STR_VOLUME_ID)
-  Added a configuration option of minimum sector size. (_MIN_SS)
-  2nd argument of f_rename() can have a drive number and it will be ignored.
-  Fixed f_mount() with forced mount fails when drive number is >= 1. (appeared at R0.10)
-  Fixed f_close() invalidates the file object without volume lock.
-  Fixed f_closedir() returns but the volume lock is left acquired. (appeared at R0.10)
-  Fixed creation of an entry with LFN fails on too many SFN collisions. (appeared at R0.07)
-
-
-
-R0.10b (May 19, 2014)
-
-  Fixed a hard error in the disk I/O layer can collapse the directory entry.
-  Fixed LFN entry is not deleted when delete/rename an object with lossy converted SFN. (appeared at R0.07)
-
-
-
-R0.10c (November 09, 2014)
-
-  Added a configuration option for the platforms without RTC. (_FS_NORTC)
-  Changed option name _USE_ERASE to _USE_TRIM.
-  Fixed volume label created by Mac OS X cannot be retrieved with f_getlabel(). (appeared at R0.09b)
-  Fixed a potential problem of FAT access that can appear on disk error.
-  Fixed null pointer dereference on attempting to delete the root direcotry. (appeared at R0.08)
-
-
-
-R0.11 (February 09, 2015)
-
-  Added f_findfirst(), f_findnext() and f_findclose(). (_USE_FIND)
-  Fixed f_unlink() does not remove cluster chain of the file. (appeared at R0.10c)
-  Fixed _FS_NORTC option does not work properly. (appeared at R0.10c)
-
-
-
-R0.11a (September 05, 2015)
-
-  Fixed wrong media change can lead a deadlock at thread-safe configuration.
-  Added code page 771, 860, 861, 863, 864, 865 and 869. (_CODE_PAGE)
-  Removed some code pages actually not exist on the standard systems. (_CODE_PAGE)
-  Fixed errors in the case conversion teble of code page 437 and 850 (ff.c).
-  Fixed errors in the case conversion teble of Unicode (cc*.c).
-
-
-
-R0.12 (April 12, 2016)
-
-  Added support for exFAT file system. (_FS_EXFAT)
-  Added f_expand(). (_USE_EXPAND)
-  Changed some members in FINFO structure and behavior of f_readdir().
-  Added an option _USE_CHMOD.
-  Removed an option _WORD_ACCESS.
-  Fixed errors in the case conversion table of Unicode (cc*.c).
-
-
-
-R0.12a (July 10, 2016)
-
-  Added support for creating exFAT volume with some changes of f_mkfs().
-  Added a file open method FA_OPEN_APPEND. An f_lseek() following f_open() is no longer needed.
-  f_forward() is available regardless of _FS_TINY.
-  Fixed f_mkfs() creates wrong volume. (appeared at R0.12)
-  Fixed wrong memory read in create_name(). (appeared at R0.12)
-  Fixed compilation fails at some configurations, _USE_FASTSEEK and _USE_FORWARD.
-
-
-
-R0.12b (September 04, 2016)
-
-  Made f_rename() be able to rename objects with the same name but case.
-  Fixed an error in the case conversion teble of code page 866. (ff.c)
-  Fixed writing data is truncated at the file offset 4GiB on the exFAT volume. (appeared at R0.12)
-  Fixed creating a file in the root directory of exFAT volume can fail. (appeared at R0.12)
-  Fixed f_mkfs() creating exFAT volume with too small cluster size can collapse unallocated memory. (appeared at R0.12)
-  Fixed wrong object name can be returned when read directory at Unicode cfg. (appeared at R0.12)
-  Fixed large file allocation/removing on the exFAT volume collapses allocation bitmap. (appeared at R0.12)
-  Fixed some internal errors in f_expand() and f_lseek(). (appeared at R0.12)
-
-
-
-R0.12c (March 04, 2017)
-
-  Improved write throughput at the fragmented file on the exFAT volume.
-  Made memory usage for exFAT be able to be reduced as decreasing _MAX_LFN.
-  Fixed successive f_getfree() can return wrong count on the FAT12/16 volume. (appeared at R0.12)
-  Fixed configuration option _VOLUMES cannot be set 10. (appeared at R0.10c)
-
-
-
-R0.13 (May 21, 2017)
-
-  Changed heading character of configuration keywords "_" to "FF_".
-  Removed ASCII-only configuration, FF_CODE_PAGE = 1. Use FF_CODE_PAGE = 437 instead.
-  Added f_setcp(), run-time code page configuration. (FF_CODE_PAGE = 0)
-  Improved cluster allocation time on stretch a deep buried cluster chain.
-  Improved processing time of f_mkdir() with large cluster size by using FF_USE_LFN = 3.
-  Improved NoFatChain flag of the fragmented file to be set after it is truncated and got contiguous.
-  Fixed archive attribute is left not set when a file on the exFAT volume is renamed. (appeared at R0.12)
-  Fixed exFAT FAT entry can be collapsed when write or lseek operation to the existing file is done. (appeared at R0.12c)
-  Fixed creating a file can fail when a new cluster allocation to the exFAT directory occures. (appeared at R0.12c)
-
-
-
-R0.13a (October 14, 2017)
-
-  Added support for UTF-8 encoding on the API. (FF_LFN_UNICODE = 2)
-  Added options for file name output buffer. (FF_LFN_BUF, FF_SFN_BUF).
-  Added dynamic memory allocation option for working buffer of f_mkfs() and f_fdisk().
-  Fixed f_fdisk() and f_mkfs() create the partition table with wrong CHS parameters. (appeared at R0.09)
-  Fixed f_unlink() can cause lost clusters at fragmented file on the exFAT volume. (appeared at R0.12c)
-  Fixed f_setlabel() rejects some valid characters for exFAT volume. (appeared at R0.12)
-
-
-
-R0.13b (April 07, 2018)
-
-  Added support for UTF-32 encoding on the API. (FF_LFN_UNICODE = 3)
-  Added support for Unix style volume ID. (FF_STR_VOLUME_ID = 2)
-  Fixed accesing any object on the exFAT root directory beyond the cluster boundary can fail. (appeared at R0.12c)
-  Fixed f_setlabel() does not reject some invalid characters. (appeared at R0.09b)
-
-
-
-R0.13c (October 14, 2018)
-  Supported stdint.h for C99 and later. (integer.h was included in ff.h)
-  Fixed reading a directory gets infinite loop when the last directory entry is not empty. (appeared at R0.12)
-  Fixed creating a sub-directory in the fragmented sub-directory on the exFAT volume collapses FAT chain of the parent directory. (appeared at R0.12)
-  Fixed f_getcwd() cause output buffer overrun when the buffer has a valid drive number. (appeared at R0.13b)
-
-
-
-R0.14 (October 14, 2019)
-  Added support for 64-bit LBA and GUID partition table (FF_LBA64 = 1)
-  Changed some API functions, f_mkfs() and f_fdisk().
-  Fixed f_open() function cannot find the file with file name in length of FF_MAX_LFN characters.
-  Fixed f_readdir() function cannot retrieve long file names in length of FF_MAX_LFN - 1 characters.
-  Fixed f_readdir() function returns file names with wrong case conversion. (appeared at R0.12)
-  Fixed f_mkfs() function can fail to create exFAT volume in the second partition. (appeared at R0.12)
-

fusee/common/fatfs/00readme.txt

@@ -1,21 +0,0 @@
-FatFs Module Source Files R0.14
-
-
-FILES
-
-  00readme.txt   This file.
-  00history.txt  Revision history.
-  ff.c           FatFs module.
-  ffconf.h       Configuration file of FatFs module.
-  ff.h           Common include file for FatFs and application module.
-  diskio.h       Common include file for FatFs and disk I/O module.
-  diskio.c       An example of glue function to attach existing disk I/O module to FatFs.
-  ffunicode.c    Optional Unicode utility functions.
-  ffsystem.c     An example of optional O/S related functions.
-
-
-  Low level disk I/O module is not included in this archive because the FatFs
-  module is only a generic file system layer and it does not depend on any specific
-  storage device. You need to provide a low level disk I/O module written to
-  control the storage device that attached to the target system.
-

fusee/common/ini.c

@@ -1,272 +0,0 @@
-/* inih -- simple .INI file parser
-
-inih is released under the New BSD license (see LICENSE.txt). Go to the project
-home page for more info:
-
-https://github.com/benhoyt/inih
-
-*/
-
-#if defined(_MSC_VER) && !defined(_CRT_SECURE_NO_WARNINGS)
-#define _CRT_SECURE_NO_WARNINGS
-#endif
-
-#include <stdio.h>
-#include <ctype.h>
-#include <string.h>
-
-#include "ini.h"
-
-#if !INI_USE_STACK
-#include <stdlib.h>
-#endif
-
-#define MAX_SECTION 50
-#define MAX_NAME 50
-
-/* Used by ini_parse_string() to keep track of string parsing state. */
-typedef struct {
-    const char* ptr;
-    size_t num_left;
-} ini_parse_string_ctx;
-
-/* Strip whitespace chars off end of given string, in place. Return s. */
-static char* rstrip(char* s)
-{
-    char* p = s + strlen(s);
-    while (p > s && isspace((unsigned char)(*--p)))
-        *p = '\0';
-    return s;
-}
-
-/* Return pointer to first non-whitespace char in given string. */
-static char* lskip(const char* s)
-{
-    while (*s && isspace((unsigned char)(*s)))
-        s++;
-    return (char*)s;
-}
-
-/* Return pointer to first char (of chars) or inline comment in given string,
-   or pointer to null at end of string if neither found. Inline comment must
-   be prefixed by a whitespace character to register as a comment. */
-static char* find_chars_or_comment(const char* s, const char* chars)
-{
-#if INI_ALLOW_INLINE_COMMENTS
-    int was_space = 0;
-    while (*s && (!chars || !strchr(chars, *s)) &&
-           !(was_space && strchr(INI_INLINE_COMMENT_PREFIXES, *s))) {
-        was_space = isspace((unsigned char)(*s));
-        s++;
-    }
-#else
-    while (*s && (!chars || !strchr(chars, *s))) {
-        s++;
-    }
-#endif
-    return (char*)s;
-}
-
-/* Version of strncpy that ensures dest (size bytes) is null-terminated. */
-static char* strncpy0(char* dest, const char* src, size_t size)
-{
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wstringop-truncation"
-    strncpy(dest, src, size - 1);
-#pragma GCC diagnostic pop
-    dest[size - 1] = '\0';
-    return dest;
-}
-
-/* See documentation in header file. */
-int ini_parse_stream(ini_reader reader, void* stream, ini_handler handler,
-                     void* user)
-{
-    /* Uses a fair bit of stack (use heap instead if you need to) */
-#if INI_USE_STACK
-    char line[INI_MAX_LINE];
-    int max_line = INI_MAX_LINE;
-#else
-    char* line;
-    int max_line = INI_INITIAL_ALLOC;
-#endif
-#if INI_ALLOW_REALLOC
-    char* new_line;
-    int offset;
-#endif
-    char section[MAX_SECTION] = "";
-    char prev_name[MAX_NAME] = "";
-
-    char* start;
-    char* end;
-    char* name;
-    char* value;
-    int lineno = 0;
-    int error = 0;
-
-#if !INI_USE_STACK
-    line = (char*)malloc(INI_INITIAL_ALLOC);
-    if (!line) {
-        return -2;
-    }
-#endif
-
-#if INI_HANDLER_LINENO
-#define HANDLER(u, s, n, v) handler(u, s, n, v, lineno)
-#else
-#define HANDLER(u, s, n, v) handler(u, s, n, v)
-#endif
-
-    /* Scan through stream line by line */
-    while (reader(line, max_line, stream) != NULL) {
-#if INI_ALLOW_REALLOC
-        offset = strlen(line);
-        while (offset == max_line - 1 && line[offset - 1] != '\n') {
-            max_line *= 2;
-            if (max_line > INI_MAX_LINE)
-                max_line = INI_MAX_LINE;
-            new_line = realloc(line, max_line);
-            if (!new_line) {
-                free(line);
-                return -2;
-            }
-            line = new_line;
-            if (reader(line + offset, max_line - offset, stream) == NULL)
-                break;
-            if (max_line >= INI_MAX_LINE)
-                break;
-            offset += strlen(line + offset);
-        }
-#endif
-
-        lineno++;
-
-        start = line;
-#if INI_ALLOW_BOM
-        if (lineno == 1 && (unsigned char)start[0] == 0xEF &&
-                           (unsigned char)start[1] == 0xBB &&
-                           (unsigned char)start[2] == 0xBF) {
-            start += 3;
-        }
-#endif
-        start = lskip(rstrip(start));
-
-        if (strchr(INI_START_COMMENT_PREFIXES, *start)) {
-            /* Start-of-line comment */
-        }
-#if INI_ALLOW_MULTILINE
-        else if (*prev_name && *start && start > line) {
-            /* Non-blank line with leading whitespace, treat as continuation
-               of previous name's value (as per Python configparser). */
-            if (!HANDLER(user, section, prev_name, start) && !error)
-                error = lineno;
-        }
-#endif
-        else if (*start == '[') {
-            /* A "[section]" line */
-            end = find_chars_or_comment(start + 1, "]");
-            if (*end == ']') {
-                *end = '\0';
-                strncpy0(section, start + 1, sizeof(section));
-                *prev_name = '\0';
-            }
-            else if (!error) {
-                /* No ']' found on section line */
-                error = lineno;
-            }
-        }
-        else if (*start) {
-            /* Not a comment, must be a name[=:]value pair */
-            end = find_chars_or_comment(start, "=:");
-            if (*end == '=' || *end == ':') {
-                *end = '\0';
-                name = rstrip(start);
-                value = end + 1;
-#if INI_ALLOW_INLINE_COMMENTS
-                end = find_chars_or_comment(value, NULL);
-                if (*end)
-                    *end = '\0';
-#endif
-                value = lskip(value);
-                rstrip(value);
-
-                /* Valid name[=:]value pair found, call handler */
-                strncpy0(prev_name, name, sizeof(prev_name));
-                if (!HANDLER(user, section, name, value) && !error)
-                    error = lineno;
-            }
-            else if (!error) {
-                /* No '=' or ':' found on name[=:]value line */
-                error = lineno;
-            }
-        }
-
-#if INI_STOP_ON_FIRST_ERROR
-        if (error)
-            break;
-#endif
-    }
-
-#if !INI_USE_STACK
-    free(line);
-#endif
-
-    return error;
-}
-
-/* See documentation in header file. */
-int ini_parse_file(FILE* file, ini_handler handler, void* user)
-{
-    return ini_parse_stream((ini_reader)fgets, file, handler, user);
-}
-
-/* See documentation in header file. */
-int ini_parse(const char* filename, ini_handler handler, void* user)
-{
-    FILE* file;
-    int error;
-
-    file = fopen(filename, "r");
-    if (!file)
-        return -1;
-    error = ini_parse_file(file, handler, user);
-    fclose(file);
-    return error;
-}
-
-/* An ini_reader function to read the next line from a string buffer. This
-   is the fgets() equivalent used by ini_parse_string(). */
-static char* ini_reader_string(char* str, int num, void* stream) {
-    ini_parse_string_ctx* ctx = (ini_parse_string_ctx*)stream;
-    const char* ctx_ptr = ctx->ptr;
-    size_t ctx_num_left = ctx->num_left;
-    char* strp = str;
-    char c;
-
-    if (ctx_num_left == 0 || num < 2)
-        return NULL;
-
-    while (num > 1 && ctx_num_left != 0) {
-        c = *ctx_ptr++;
-        ctx_num_left--;
-        *strp++ = c;
-        if (c == '\n')
-            break;
-        num--;
-    }
-
-    *strp = '\0';
-    ctx->ptr = ctx_ptr;
-    ctx->num_left = ctx_num_left;
-    return str;
-}
-
-/* See documentation in header file. */
-int ini_parse_string(const char* string, ini_handler handler, void* user) {
-    ini_parse_string_ctx ctx;
-
-    ctx.ptr = string;
-    ctx.num_left = strlen(string);
-    return ini_parse_stream((ini_reader)ini_reader_string, &ctx, handler,
-                            user);
-}

fusee/common/ini.h

@@ -1,130 +0,0 @@
-/* inih -- simple .INI file parser
-
-inih is released under the New BSD license (see LICENSE.txt). Go to the project
-home page for more info:
-
-https://github.com/benhoyt/inih
-
-*/
-
-#ifndef __INI_H__
-#define __INI_H__
-
-/* Make this header file easier to include in C++ code */
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdio.h>
-
-/* Nonzero if ini_handler callback should accept lineno parameter. */
-#ifndef INI_HANDLER_LINENO
-#define INI_HANDLER_LINENO 0
-#endif
-
-/* Typedef for prototype of handler function. */
-#if INI_HANDLER_LINENO
-typedef int (*ini_handler)(void* user, const char* section,
-                           const char* name, const char* value,
-                           int lineno);
-#else
-typedef int (*ini_handler)(void* user, const char* section,
-                           const char* name, const char* value);
-#endif
-
-/* Typedef for prototype of fgets-style reader function. */
-typedef char* (*ini_reader)(char* str, int num, void* stream);
-
-/* Parse given INI-style file. May have [section]s, name=value pairs
-   (whitespace stripped), and comments starting with ';' (semicolon). Section
-   is "" if name=value pair parsed before any section heading. name:value
-   pairs are also supported as a concession to Python's configparser.
-
-   For each name=value pair parsed, call handler function with given user
-   pointer as well as section, name, and value (data only valid for duration
-   of handler call). Handler should return nonzero on success, zero on error.
-
-   Returns 0 on success, line number of first error on parse error (doesn't
-   stop on first error), -1 on file open error, or -2 on memory allocation
-   error (only when INI_USE_STACK is zero).
-*/
-int ini_parse(const char* filename, ini_handler handler, void* user);
-
-/* Same as ini_parse(), but takes a FILE* instead of filename. This doesn't
-   close the file when it's finished -- the caller must do that. */
-int ini_parse_file(FILE* file, ini_handler handler, void* user);
-
-/* Same as ini_parse(), but takes an ini_reader function pointer instead of
-   filename. Used for implementing custom or string-based I/O (see also
-   ini_parse_string). */
-int ini_parse_stream(ini_reader reader, void* stream, ini_handler handler,
-                     void* user);
-
-/* Same as ini_parse(), but takes a zero-terminated string with the INI data
-instead of a file. Useful for parsing INI data from a network socket or
-already in memory. */
-int ini_parse_string(const char* string, ini_handler handler, void* user);
-
-/* Nonzero to allow multi-line value parsing, in the style of Python's
-   configparser. If allowed, ini_parse() will call the handler with the same
-   name for each subsequent line parsed. */
-#ifndef INI_ALLOW_MULTILINE
-#define INI_ALLOW_MULTILINE 1
-#endif
-
-/* Nonzero to allow a UTF-8 BOM sequence (0xEF 0xBB 0xBF) at the start of
-   the file. See http://code.google.com/p/inih/issues/detail?id=21 */
-#ifndef INI_ALLOW_BOM
-#define INI_ALLOW_BOM 1
-#endif
-
-/* Chars that begin a start-of-line comment. Per Python configparser, allow
-   both ; and # comments at the start of a line by default. */
-#ifndef INI_START_COMMENT_PREFIXES
-#define INI_START_COMMENT_PREFIXES ";#"
-#endif
-
-/* Nonzero to allow inline comments (with valid inline comment characters
-   specified by INI_INLINE_COMMENT_PREFIXES). Set to 0 to turn off and match
-   Python 3.2+ configparser behaviour. */
-#ifndef INI_ALLOW_INLINE_COMMENTS
-#define INI_ALLOW_INLINE_COMMENTS 1
-#endif
-#ifndef INI_INLINE_COMMENT_PREFIXES
-#define INI_INLINE_COMMENT_PREFIXES ";"
-#endif
-
-/* Nonzero to use stack for line buffer, zero to use heap (malloc/free). */
-#ifndef INI_USE_STACK
-#define INI_USE_STACK 1
-#endif
-
-/* Maximum line length for any line in INI file (stack or heap). Note that
-   this must be 3 more than the longest line (due to '\r', '\n', and '\0'). */
-#ifndef INI_MAX_LINE
-#define INI_MAX_LINE 200
-#endif
-
-/* Nonzero to allow heap line buffer to grow via realloc(), zero for a
-   fixed-size buffer of INI_MAX_LINE bytes. Only applies if INI_USE_STACK is
-   zero. */
-#ifndef INI_ALLOW_REALLOC
-#define INI_ALLOW_REALLOC 0
-#endif
-
-/* Initial size in bytes for heap line buffer. Only applies if INI_USE_STACK
-   is zero. */
-#ifndef INI_INITIAL_ALLOC
-#define INI_INITIAL_ALLOC 200
-#endif
-
-/* Stop parsing on first error (default is to keep parsing). */
-#ifndef INI_STOP_ON_FIRST_ERROR
-#define INI_STOP_ON_FIRST_ERROR 0
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __INI_H__ */

fusee/common/log.c

@@ -1,141 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "log.h"
-
-#ifdef FUSEE_STAGE2_SRC
-#include "../../../fusee/fusee-secondary/src/console.h"
-#include <stdio.h>
-#else
-#include "display/video_fb.h"
-#include "vsprintf.h"
-#endif
-
-/* Default log level for screen output. */
-ScreenLogLevel g_screen_log_level = SCREEN_LOG_LEVEL_NONE;
-
-void log_set_log_level(ScreenLogLevel log_level) {
-    g_screen_log_level = log_level;
-}
-
-ScreenLogLevel log_get_log_level() {
-    return g_screen_log_level;
-}
-
-void log_to_uart(const char *message) {
-    /* TODO: Add UART logging. */
-}
-
-static void print_to_screen(ScreenLogLevel screen_log_level, char *message) {
-    /* Don't print to screen if below log level */
-    if(screen_log_level > g_screen_log_level) return;
-    
-    #ifdef FUSEE_STAGE2_SRC
-    printf(message);
-    #else
-    video_puts(message);
-    #endif
-}
-
-/**
- * vprintk - logs a message and prints it to screen based on its screen_log_level
- *
- * If the level is below g_screen_log_level it will not be shown but logged to UART
- * This text will not be colored or prefixed
- * UART is TODO
- */
-void vprint(ScreenLogLevel screen_log_level, const char *fmt, va_list args)
-{
-    char buf[PRINT_MESSAGE_MAX_LENGTH];
-    vsnprintf(buf, PRINT_MESSAGE_MAX_LENGTH, fmt, args);
-
-    /* We don't need that flag here, but if it gets used, strip it so we print correctly. */
-    screen_log_level &= ~SCREEN_LOG_LEVEL_NO_PREFIX;
-
-    /* Log to UART. */
-    log_to_uart(buf);
-
-    print_to_screen(screen_log_level, buf);
-}
-
-static void add_prefix(ScreenLogLevel screen_log_level, const char *fmt, char *buf) {
-    char typebuf[] = "[%s] %s";
-
-    /* Apply prefix and append message format. */
-    /* TODO: Add coloring to the output. */
-    switch(screen_log_level)
-    {
-        case SCREEN_LOG_LEVEL_ERROR:
-            snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, typebuf, "ERROR", fmt);
-            break;
-        case SCREEN_LOG_LEVEL_WARNING:
-            snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, typebuf, "WARNING", fmt);
-            break;
-        case SCREEN_LOG_LEVEL_MANDATORY:
-            snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, "%s", fmt);
-            break;
-        case SCREEN_LOG_LEVEL_INFO:
-            snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, typebuf, "INFO", fmt);
-            break;
-        case SCREEN_LOG_LEVEL_DEBUG:
-            snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, typebuf, "DEBUG", fmt);
-            break;
-        default:
-            break;
-    }
-}
-
-/**
- * print - logs a message and prints it to screen based on its screen_log_level
- * 
- * If the level is below g_screen_log_level it will not be shown but logged to UART
- * Use SCREEN_LOG_LEVEL_NO_PREFIX if you don't want a prefix to be added
- * UART is TODO
- */
-void print(ScreenLogLevel screen_log_level, const char * fmt, ...)
-{
-    char buf[PRINT_MESSAGE_MAX_LENGTH] = {};
-    char message[PRINT_MESSAGE_MAX_LENGTH] = {};
-
-    /* Make splash disappear if level is ERROR or WARNING. */
-    #ifdef FUSEE_STAGE2_SRC
-    if (screen_log_level < SCREEN_LOG_LEVEL_MANDATORY) {
-        console_resume();
-    }
-    #endif
-
-    /* Make prefix free messages with log_level possible. */
-    if(screen_log_level & SCREEN_LOG_LEVEL_NO_PREFIX) {
-        /* Remove the NO_PREFIX flag so the enum can be recognized later on. */
-        screen_log_level &= ~SCREEN_LOG_LEVEL_NO_PREFIX;
-
-        snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, "%s", fmt);
-    }
-    else {
-        add_prefix(screen_log_level, fmt, buf);
-    }
-
-    /* Input arguments. */
-    va_list args;
-    va_start(args, fmt);
-    vsnprintf(message, PRINT_MESSAGE_MAX_LENGTH, buf, args);
-    va_end(args);
-
-    /* Log to UART. */
-    log_to_uart(message);
-
-    print_to_screen(screen_log_level, message);
-}

fusee/common/log.h

@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef FUSEE_LOG_H
-#define FUSEE_LOG_H
-
-#define PRINT_MESSAGE_MAX_LENGTH 1024
-
-#include <stdarg.h>
-
-typedef enum {
-    SCREEN_LOG_LEVEL_NONE       = 0,
-    SCREEN_LOG_LEVEL_ERROR      = 1,
-    SCREEN_LOG_LEVEL_WARNING    = 2,
-    SCREEN_LOG_LEVEL_MANDATORY  = 3,    /* No log prefix. */
-    SCREEN_LOG_LEVEL_INFO       = 4,
-    SCREEN_LOG_LEVEL_DEBUG      = 5,
-    SCREEN_LOG_LEVEL_SD_DEBUG   = 6,
-
-    SCREEN_LOG_LEVEL_NO_PREFIX  = 0x100 /* OR this to your LOG_LEVEL to prevent prefix creation. */
-} ScreenLogLevel;
-
-extern ScreenLogLevel g_screen_log_level;
-
-void log_set_log_level(ScreenLogLevel screen_log_level);
-ScreenLogLevel log_get_log_level();
-void log_to_uart(const char *message);
-void vprint(ScreenLogLevel screen_log_level, const char *fmt, va_list args);
-void print(ScreenLogLevel screen_log_level, const char* fmt, ...);
-
-#endif

fusee/common/lz.c

@@ -1,377 +0,0 @@
-/*************************************************************************
-* Name:        lz.c
-* Author:      Marcus Geelnard
-* Description: LZ77 coder/decoder implementation.
-* Reentrant:   Yes
-*
-* The LZ77 compression scheme is a substitutional compression scheme
-* proposed by Abraham Lempel and Jakob Ziv in 1977. It is very simple in
-* its design, and uses no fancy bit level compression.
-*
-* This is my first attempt at an implementation of a LZ77 code/decoder.
-*
-* The principle of the LZ77 compression algorithm is to store repeated
-* occurrences of strings as references to previous occurrences of the same
-* string. The point is that the reference consumes less space than the
-* string itself, provided that the string is long enough (in this
-* implementation, the string has to be at least 4 bytes long, since the
-* minimum coded reference is 3 bytes long). Also note that the term
-* "string" refers to any kind of byte sequence (it does not have to be
-* an ASCII string, for instance).
-*
-* The coder uses a brute force approach to finding string matches in the
-* history buffer (or "sliding window", if you wish), which is very, very
-* slow. I recon the complexity is somewhere between O(n^2) and O(n^3),
-* depending on the input data.
-*
-* There is also a faster implementation that uses a large working buffer
-* in which a "jump table" is stored, which is used to quickly find
-* possible string matches (see the source code for LZ_CompressFast() for
-* more information). The faster method is an order of magnitude faster,
-* but still quite slow compared to other compression methods.
-*
-* The upside is that decompression is very fast, and the compression ratio
-* is often very good.
-*
-* The reference to a string is coded as a (length,offset) pair, where the
-* length indicates the length of the string, and the offset gives the
-* offset from the current data position. To distinguish between string
-* references and literal strings (uncompressed bytes), a string reference
-* is preceded by a marker byte, which is chosen as the least common byte
-* symbol in the input data stream (this marker byte is stored in the
-* output stream as the first byte).
-*
-* Occurrences of the marker byte in the stream are encoded as the marker
-* byte followed by a zero byte, which means that occurrences of the marker
-* byte have to be coded with two bytes.
-*
-* The lengths and offsets are coded in a variable length fashion, allowing
-* values of any magnitude (up to 4294967295 in this implementation).
-*
-* With this compression scheme, the worst case compression result is
-* (257/256)*insize + 1.
-*
-*-------------------------------------------------------------------------
-* Copyright (c) 2003-2006 Marcus Geelnard
-*
-* This software is provided 'as-is', without any express or implied
-* warranty. In no event will the authors be held liable for any damages
-* arising from the use of this software.
-*
-* Permission is granted to anyone to use this software for any purpose,
-* including commercial applications, and to alter it and redistribute it
-* freely, subject to the following restrictions:
-*
-* 1. The origin of this software must not be misrepresented; you must not
-*    claim that you wrote the original software. If you use this software
-*    in a product, an acknowledgment in the product documentation would
-*    be appreciated but is not required.
-*
-* 2. Altered source versions must be plainly marked as such, and must not
-*    be misrepresented as being the original software.
-*
-* 3. This notice may not be removed or altered from any source
-*    distribution.
-*
-* Marcus Geelnard
-* marcus.geelnard at home.se
-*************************************************************************/
-
-
-/*************************************************************************
-* Constants used for LZ77 coding
-*************************************************************************/
-
-/* Maximum offset (can be any size < 2^31). Lower values give faster
-   compression, while higher values gives better compression. The default
-   value of 100000 is quite high. Experiment to see what works best for
-   you. */
-#define LZ_MAX_OFFSET 100000
-
-
-
-/*************************************************************************
-*                           INTERNAL FUNCTIONS                           *
-*************************************************************************/
-
-
-/*************************************************************************
-* _LZ_StringCompare() - Return maximum length string match.
-*************************************************************************/
-
-static unsigned int _LZ_StringCompare( const unsigned char * str1,
-  const unsigned char * str2, unsigned int minlen, unsigned int maxlen )
-{
-    unsigned int len;
-
-    for( len = minlen; (len < maxlen) && (str1[len] == str2[len]); ++ len );
-
-    return len;
-}
-
-
-/*************************************************************************
-* _LZ_WriteVarSize() - Write unsigned integer with variable number of
-* bytes depending on value.
-*************************************************************************/
-
-static int _LZ_WriteVarSize( unsigned int x, unsigned char * buf )
-{
-    unsigned int y;
-    int num_bytes, i, b;
-
-    /* Determine number of bytes needed to store the number x */
-    y = x >> 3;
-    for( num_bytes = 5; num_bytes >= 2; -- num_bytes )
-    {
-        if( y & 0xfe000000 ) break;
-        y <<= 7;
-    }
-
-    /* Write all bytes, seven bits in each, with 8:th bit set for all */
-    /* but the last byte. */
-    for( i = num_bytes-1; i >= 0; -- i )
-    {
-        b = (x >> (i*7)) & 0x0000007f;
-        if( i > 0 )
-        {
-            b |= 0x00000080;
-        }
-        *buf ++ = (unsigned char) b;
-    }
-
-    /* Return number of bytes written */
-    return num_bytes;
-}
-
-
-/*************************************************************************
-* _LZ_ReadVarSize() - Read unsigned integer with variable number of
-* bytes depending on value.
-*************************************************************************/
-
-static int _LZ_ReadVarSize( unsigned int * x, const unsigned char * buf )
-{
-    unsigned int y, b, num_bytes;
-
-    /* Read complete value (stop when byte contains zero in 8:th bit) */
-    y = 0;
-    num_bytes = 0;
-    do
-    {
-        b = (unsigned int) (*buf ++);
-        y = (y << 7) | (b & 0x0000007f);
-        ++ num_bytes;
-    }
-    while( b & 0x00000080 );
-
-    /* Store value in x */
-    *x = y;
-
-    /* Return number of bytes read */
-    return num_bytes;
-}
-
-
-
-/*************************************************************************
-*                            PUBLIC FUNCTIONS                            *
-*************************************************************************/
-
-
-/*************************************************************************
-* LZ_Compress() - Compress a block of data using an LZ77 coder.
-*  in     - Input (uncompressed) buffer.
-*  out    - Output (compressed) buffer. This buffer must be 0.4% larger
-*           than the input buffer, plus one byte.
-*  insize - Number of input bytes.
-* The function returns the size of the compressed data.
-*************************************************************************/
-
-int LZ_Compress( const unsigned char *in, unsigned char *out, unsigned int insize )
-{
-    unsigned char marker, symbol;
-    unsigned int  inpos, outpos, bytesleft, i;
-    unsigned int  maxoffset, offset, bestoffset;
-    unsigned int  maxlength, length, bestlength;
-    unsigned int  histogram[ 256 ];
-    const unsigned char *ptr1, *ptr2;
-
-    /* Do we have anything to compress? */
-    if( insize < 1 )
-    {
-        return 0;
-    }
-
-    /* Create histogram */
-    for( i = 0; i < 256; ++ i )
-    {
-        histogram[ i ] = 0;
-    }
-    for( i = 0; i < insize; ++ i )
-    {
-        ++ histogram[ in[ i ] ];
-    }
-
-    /* Find the least common byte, and use it as the marker symbol */
-    marker = 0;
-    for( i = 1; i < 256; ++ i )
-    {
-        if( histogram[ i ] < histogram[ marker ] )
-        {
-            marker = (unsigned char) i;
-        }
-    }
-
-    /* Remember the marker symbol for the decoder */
-    out[ 0 ] = marker;
-
-    /* Start of compression */
-    inpos = 0;
-    outpos = 1;
-
-    /* Main compression loop */
-    bytesleft = insize;
-    do
-    {
-        /* Determine most distant position */
-        if( inpos > LZ_MAX_OFFSET ) maxoffset = LZ_MAX_OFFSET;
-        else                        maxoffset = inpos;
-
-        /* Get pointer to current position */
-        ptr1 = &in[ inpos ];
-
-        /* Search history window for maximum length string match */
-        bestlength = 3;
-        bestoffset = 0;
-        for( offset = 3; offset <= maxoffset; ++ offset )
-        {
-            /* Get pointer to candidate string */
-            ptr2 = &ptr1[ -(int)offset ];
-
-            /* Quickly determine if this is a candidate (for speed) */
-            if( (ptr1[ 0 ] == ptr2[ 0 ]) &&
-                (ptr1[ bestlength ] == ptr2[ bestlength ]) )
-            {
-                /* Determine maximum length for this offset */
-                maxlength = (bytesleft < offset ? bytesleft : offset);
-
-                /* Count maximum length match at this offset */
-                length = _LZ_StringCompare( ptr1, ptr2, 0, maxlength );
-
-                /* Better match than any previous match? */
-                if( length > bestlength )
-                {
-                    bestlength = length;
-                    bestoffset = offset;
-                }
-            }
-        }
-
-        /* Was there a good enough match? */
-        if( (bestlength >= 8) ||
-            ((bestlength == 4) && (bestoffset <= 0x0000007f)) ||
-            ((bestlength == 5) && (bestoffset <= 0x00003fff)) ||
-            ((bestlength == 6) && (bestoffset <= 0x001fffff)) ||
-            ((bestlength == 7) && (bestoffset <= 0x0fffffff)) )
-        {
-            out[ outpos ++ ] = (unsigned char) marker;
-            outpos += _LZ_WriteVarSize( bestlength, &out[ outpos ] );
-            outpos += _LZ_WriteVarSize( bestoffset, &out[ outpos ] );
-            inpos += bestlength;
-            bytesleft -= bestlength;
-        }
-        else
-        {
-            /* Output single byte (or two bytes if marker byte) */
-            symbol = in[ inpos ++ ];
-            out[ outpos ++ ] = symbol;
-            if( symbol == marker )
-            {
-                out[ outpos ++ ] = 0;
-            }
-            -- bytesleft;
-        }
-    }
-    while( bytesleft > 3 );
-
-    /* Dump remaining bytes, if any */
-    while( inpos < insize )
-    {
-        if( in[ inpos ] == marker )
-        {
-            out[ outpos ++ ] = marker;
-            out[ outpos ++ ] = 0;
-        }
-        else
-        {
-            out[ outpos ++ ] = in[ inpos ];
-        }
-        ++ inpos;
-    }
-
-    return outpos;
-}
-
-
-/*************************************************************************
-* LZ_Uncompress() - Uncompress a block of data using an LZ77 decoder.
-*  in      - Input (compressed) buffer.
-*  out     - Output (uncompressed) buffer. This buffer must be large
-*            enough to hold the uncompressed data.
-*  insize  - Number of input bytes.
-*************************************************************************/
-
-int LZ_Uncompress( const unsigned char *in, unsigned char *out, unsigned int insize )
-{
-    unsigned char marker, symbol;
-    unsigned int  i, inpos, outpos, length, offset;
-
-    /* Do we have anything to uncompress? */
-    if( insize < 1 )
-    {
-        return 0;
-    }
-
-    /* Get marker symbol from input stream */
-    marker = in[ 0 ];
-    inpos = 1;
-
-    /* Main decompression loop */
-    outpos = 0;
-    do
-    {
-        symbol = in[ inpos ++ ];
-        if( symbol == marker )
-        {
-            /* We had a marker byte */
-            if( in[ inpos ] == 0 )
-            {
-                /* It was a single occurrence of the marker byte */
-                out[ outpos ++ ] = marker;
-                ++ inpos;
-            }
-            else
-            {
-                /* Extract true length and offset */
-                inpos += _LZ_ReadVarSize( &length, &in[ inpos ] );
-                inpos += _LZ_ReadVarSize( &offset, &in[ inpos ] );
-
-                /* Copy corresponding data from history window */
-                for( i = 0; i < length; ++ i )
-                {
-                    out[ outpos ] = out[ outpos - offset ];
-                    ++ outpos;
-                }
-            }
-        }
-        else
-        {
-            /* No marker, plain copy */
-            out[ outpos ++ ] = symbol;
-        }
-    }
-    while( inpos < insize );
-
-    return outpos;
-}

fusee/common/lz.h

@@ -1,51 +0,0 @@
-/*************************************************************************
-* Name:        lz.h
-* Author:      Marcus Geelnard
-* Description: LZ77 coder/decoder interface.
-* Reentrant:   Yes
-*-------------------------------------------------------------------------
-* Copyright (c) 2003-2006 Marcus Geelnard
-*
-* This software is provided 'as-is', without any express or implied
-* warranty. In no event will the authors be held liable for any damages
-* arising from the use of this software.
-*
-* Permission is granted to anyone to use this software for any purpose,
-* including commercial applications, and to alter it and redistribute it
-* freely, subject to the following restrictions:
-*
-* 1. The origin of this software must not be misrepresented; you must not
-*    claim that you wrote the original software. If you use this software
-*    in a product, an acknowledgment in the product documentation would
-*    be appreciated but is not required.
-*
-* 2. Altered source versions must be plainly marked as such, and must not
-*    be misrepresented as being the original software.
-*
-* 3. This notice may not be removed or altered from any source
-*    distribution.
-*
-* Marcus Geelnard
-* marcus.geelnard at home.se
-*************************************************************************/
-
-#ifndef _lz_h_
-#define _lz_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/*************************************************************************
-* Function prototypes
-*************************************************************************/
-
-int LZ_Compress(const unsigned char *in, unsigned char *out, unsigned int insize);
-int LZ_Uncompress(const unsigned char *in, unsigned char *out, unsigned int insize);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _lz_h_ */

fusee/common/sdmmc/mmc.h

@@ -1,449 +0,0 @@
-/*
- * Header for MultiMediaCard (MMC)
- *
- * Copyright 2002 Hewlett-Packard Company
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * Use consistent with the GNU GPL is permitted,
- * provided that this copyright notice is
- * preserved in its entirety in all copies and derived works.
- *
- * HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
- * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
- * FITNESS FOR ANY PARTICULAR PURPOSE.
- *
- * Many thanks to Alessandro Rubini and Jonathan Corbet!
- *
- * Based strongly on code by:
- *
- * Author: Yong-iL Joh <tolkien@mizi.com>
- *
- * Author:  Andrew Christian
- *          15 May 2002
- */
-
-#ifndef LINUX_MMC_MMC_H
-#define LINUX_MMC_MMC_H
-
-/* Standard MMC commands (4.1)           type  argument     response */
-   /* class 1 */
-#define MMC_GO_IDLE_STATE         0   /* bc                          */
-#define MMC_SEND_OP_COND          1   /* bcr  [31:0] OCR         R3  */
-#define MMC_ALL_SEND_CID          2   /* bcr                     R2  */
-#define MMC_SET_RELATIVE_ADDR     3   /* ac   [31:16] RCA        R1  */
-#define MMC_SET_DSR               4   /* bc   [31:16] RCA            */
-#define MMC_SLEEP_AWAKE           5   /* ac   [31:16] RCA 15:flg R1b */
-#define MMC_SWITCH                6   /* ac   [31:0] See below   R1b */
-#define MMC_SELECT_CARD           7   /* ac   [31:16] RCA        R1  */
-#define MMC_SEND_EXT_CSD          8   /* adtc                    R1  */
-#define MMC_SEND_CSD              9   /* ac   [31:16] RCA        R2  */
-#define MMC_SEND_CID             10   /* ac   [31:16] RCA        R2  */
-#define MMC_READ_DAT_UNTIL_STOP  11   /* adtc [31:0] dadr        R1  */
-#define MMC_STOP_TRANSMISSION    12   /* ac                      R1b */
-#define MMC_SEND_STATUS          13   /* ac   [31:16] RCA        R1  */
-#define MMC_BUS_TEST_R           14   /* adtc                    R1  */
-#define MMC_GO_INACTIVE_STATE    15   /* ac   [31:16] RCA            */
-#define MMC_BUS_TEST_W           19   /* adtc                    R1  */
-#define MMC_SPI_READ_OCR         58   /* spi                  spi_R3 */
-#define MMC_SPI_CRC_ON_OFF       59   /* spi  [0:0] flag      spi_R1 */
-
-  /* class 2 */
-#define MMC_SET_BLOCKLEN            16   /* ac   [31:0] block len   R1  */
-#define MMC_READ_SINGLE_BLOCK       17   /* adtc [31:0] data addr   R1  */
-#define MMC_READ_MULTIPLE_BLOCK     18   /* adtc [31:0] data addr   R1  */
-#define MMC_SEND_TUNING_BLOCK       19   /* adtc                    R1  */
-#define MMC_SEND_TUNING_BLOCK_HS200 21   /* adtc R1  */
-
-  /* class 3 */
-#define MMC_WRITE_DAT_UNTIL_STOP 20   /* adtc [31:0] data addr   R1  */
-
-  /* class 4 */
-#define MMC_SET_BLOCK_COUNT      23   /* adtc [31:0] data addr   R1  */
-#define MMC_WRITE_BLOCK          24   /* adtc [31:0] data addr   R1  */
-#define MMC_WRITE_MULTIPLE_BLOCK 25   /* adtc                    R1  */
-#define MMC_PROGRAM_CID          26   /* adtc                    R1  */
-#define MMC_PROGRAM_CSD          27   /* adtc                    R1  */
-
-  /* class 6 */
-#define MMC_SET_WRITE_PROT       28   /* ac   [31:0] data addr   R1b */
-#define MMC_CLR_WRITE_PROT       29   /* ac   [31:0] data addr   R1b */
-#define MMC_SEND_WRITE_PROT      30   /* adtc [31:0] wpdata addr R1  */
-
-  /* class 5 */
-#define MMC_ERASE_GROUP_START    35   /* ac   [31:0] data addr   R1  */
-#define MMC_ERASE_GROUP_END      36   /* ac   [31:0] data addr   R1  */
-#define MMC_ERASE                38   /* ac                      R1b */
-
-  /* class 9 */
-#define MMC_FAST_IO              39   /* ac   <Complex>          R4  */
-#define MMC_GO_IRQ_STATE         40   /* bcr                     R5  */
-
-  /* class 7 */
-#define MMC_LOCK_UNLOCK          42   /* adtc                    R1b */
-
-  /* class 8 */
-#define MMC_APP_CMD              55   /* ac   [31:16] RCA        R1  */
-#define MMC_GEN_CMD              56   /* adtc [0] RD/WR          R1  */
-
-  /* class 11 */
-#define MMC_QUE_TASK_PARAMS      44   /* ac   [20:16] task id    R1  */
-#define MMC_QUE_TASK_ADDR        45   /* ac   [31:0] data addr   R1  */
-#define MMC_EXECUTE_READ_TASK    46   /* adtc [20:16] task id    R1  */
-#define MMC_EXECUTE_WRITE_TASK   47   /* adtc [20:16] task id    R1  */
-#define MMC_CMDQ_TASK_MGMT       48   /* ac   [20:16] task id    R1b */
-
-/*
- * MMC_SWITCH argument format:
- *
- *  [31:26] Always 0
- *  [25:24] Access Mode
- *  [23:16] Location of target Byte in EXT_CSD
- *  [15:08] Value Byte
- *  [07:03] Always 0
- *  [02:00] Command Set
- */
-
-/*
-  MMC status in R1, for native mode (SPI bits are different)
-  Type
-    e : error bit
-    s : status bit
-    r : detected and set for the actual command response
-    x : detected and set during command execution. the host must poll
-            the card by sending status command in order to read these bits.
-  Clear condition
-    a : according to the card state
-    b : always related to the previous command. Reception of
-            a valid command will clear it (with a delay of one command)
-    c : clear by read
- */
-
-#define R1_OUT_OF_RANGE     (1 << 31)   /* er, c */
-#define R1_ADDRESS_ERROR    (1 << 30)   /* erx, c */
-#define R1_BLOCK_LEN_ERROR  (1 << 29)   /* er, c */
-#define R1_ERASE_SEQ_ERROR      (1 << 28)   /* er, c */
-#define R1_ERASE_PARAM      (1 << 27)   /* ex, c */
-#define R1_WP_VIOLATION     (1 << 26)   /* erx, c */
-#define R1_CARD_IS_LOCKED   (1 << 25)   /* sx, a */
-#define R1_LOCK_UNLOCK_FAILED   (1 << 24)   /* erx, c */
-#define R1_COM_CRC_ERROR    (1 << 23)   /* er, b */
-#define R1_ILLEGAL_COMMAND  (1 << 22)   /* er, b */
-#define R1_CARD_ECC_FAILED  (1 << 21)   /* ex, c */
-#define R1_CC_ERROR     (1 << 20)   /* erx, c */
-#define R1_ERROR        (1 << 19)   /* erx, c */
-#define R1_UNDERRUN     (1 << 18)   /* ex, c */
-#define R1_OVERRUN      (1 << 17)   /* ex, c */
-#define R1_CID_CSD_OVERWRITE    (1 << 16)   /* erx, c, CID/CSD overwrite */
-#define R1_WP_ERASE_SKIP    (1 << 15)   /* sx, c */
-#define R1_CARD_ECC_DISABLED    (1 << 14)   /* sx, a */
-#define R1_ERASE_RESET      (1 << 13)   /* sr, c */
-#define R1_STATUS(x)            (x & 0xFFFFE000)
-#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
-#define R1_READY_FOR_DATA   (1 << 8)    /* sx, a */
-#define R1_SWITCH_ERROR     (1 << 7)    /* sx, c */
-#define R1_EXCEPTION_EVENT  (1 << 6)    /* sr, a */
-#define R1_APP_CMD      (1 << 5)    /* sr, c */
-
-#define R1_STATE_IDLE   0
-#define R1_STATE_READY  1
-#define R1_STATE_IDENT  2
-#define R1_STATE_STBY   3
-#define R1_STATE_TRAN   4
-#define R1_STATE_DATA   5
-#define R1_STATE_RCV    6
-#define R1_STATE_PRG    7
-#define R1_STATE_DIS    8
-
-/*
- * MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS
- * R1 is the low order byte; R2 is the next highest byte, when present.
- */
-#define R1_SPI_IDLE     (1 << 0)
-#define R1_SPI_ERASE_RESET  (1 << 1)
-#define R1_SPI_ILLEGAL_COMMAND  (1 << 2)
-#define R1_SPI_COM_CRC      (1 << 3)
-#define R1_SPI_ERASE_SEQ    (1 << 4)
-#define R1_SPI_ADDRESS      (1 << 5)
-#define R1_SPI_PARAMETER    (1 << 6)
-/* R1 bit 7 is always zero */
-#define R2_SPI_CARD_LOCKED  (1 << 8)
-#define R2_SPI_WP_ERASE_SKIP    (1 << 9)    /* or lock/unlock fail */
-#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
-#define R2_SPI_ERROR        (1 << 10)
-#define R2_SPI_CC_ERROR     (1 << 11)
-#define R2_SPI_CARD_ECC_ERROR   (1 << 12)
-#define R2_SPI_WP_VIOLATION (1 << 13)
-#define R2_SPI_ERASE_PARAM  (1 << 14)
-#define R2_SPI_OUT_OF_RANGE (1 << 15)   /* or CSD overwrite */
-#define R2_SPI_CSD_OVERWRITE    R2_SPI_OUT_OF_RANGE
-
-/*
- * OCR bits are mostly in host.h
- */
-#define MMC_CARD_BUSY       0x80000000  /* Card Power up status bit */
-#define MMC_VDD_165_195     0x00000080  /* VDD voltage 1.65 - 1.95 */
-#define MMC_VDD_20_21       0x00000100  /* VDD voltage 2.0 ~ 2.1 */
-#define MMC_VDD_21_22       0x00000200  /* VDD voltage 2.1 ~ 2.2 */
-#define MMC_VDD_22_23       0x00000400  /* VDD voltage 2.2 ~ 2.3 */
-#define MMC_VDD_23_24       0x00000800  /* VDD voltage 2.3 ~ 2.4 */
-#define MMC_VDD_24_25       0x00001000  /* VDD voltage 2.4 ~ 2.5 */
-#define MMC_VDD_25_26       0x00002000  /* VDD voltage 2.5 ~ 2.6 */
-#define MMC_VDD_26_27       0x00004000  /* VDD voltage 2.6 ~ 2.7 */
-#define MMC_VDD_27_28       0x00008000  /* VDD voltage 2.7 ~ 2.8 */
-#define MMC_VDD_28_29       0x00010000  /* VDD voltage 2.8 ~ 2.9 */
-#define MMC_VDD_29_30       0x00020000  /* VDD voltage 2.9 ~ 3.0 */
-#define MMC_VDD_30_31       0x00040000  /* VDD voltage 3.0 ~ 3.1 */
-#define MMC_VDD_31_32       0x00080000  /* VDD voltage 3.1 ~ 3.2 */
-#define MMC_VDD_32_33       0x00100000  /* VDD voltage 3.2 ~ 3.3 */
-#define MMC_VDD_33_34       0x00200000  /* VDD voltage 3.3 ~ 3.4 */
-#define MMC_VDD_34_35       0x00400000  /* VDD voltage 3.4 ~ 3.5 */
-#define MMC_VDD_35_36       0x00800000  /* VDD voltage 3.5 ~ 3.6 */
-
-/*
- * Card Command Classes (CCC)
- */
-#define CCC_BASIC       (1<<0)  /* (0) Basic protocol functions */
-                    /* (CMD0,1,2,3,4,7,9,10,12,13,15) */
-                    /* (and for SPI, CMD58,59) */
-#define CCC_STREAM_READ     (1<<1)  /* (1) Stream read commands */
-                    /* (CMD11) */
-#define CCC_BLOCK_READ      (1<<2)  /* (2) Block read commands */
-                    /* (CMD16,17,18) */
-#define CCC_STREAM_WRITE    (1<<3)  /* (3) Stream write commands */
-                    /* (CMD20) */
-#define CCC_BLOCK_WRITE     (1<<4)  /* (4) Block write commands */
-                    /* (CMD16,24,25,26,27) */
-#define CCC_ERASE       (1<<5)  /* (5) Ability to erase blocks */
-                    /* (CMD32,33,34,35,36,37,38,39) */
-#define CCC_WRITE_PROT      (1<<6)  /* (6) Able to write protect blocks */
-                    /* (CMD28,29,30) */
-#define CCC_LOCK_CARD       (1<<7)  /* (7) Able to lock down card */
-                    /* (CMD16,CMD42) */
-#define CCC_APP_SPEC        (1<<8)  /* (8) Application specific */
-                    /* (CMD55,56,57,ACMD*) */
-#define CCC_IO_MODE     (1<<9)  /* (9) I/O mode */
-                    /* (CMD5,39,40,52,53) */
-#define CCC_SWITCH      (1<<10) /* (10) High speed switch */
-                    /* (CMD6,34,35,36,37,50) */
-                    /* (11) Reserved */
-                    /* (CMD?) */
-
-/*
- * CSD field definitions
- */
-
-#define CSD_STRUCT_VER_1_0  0           /* Valid for system specification 1.0 - 1.2 */
-#define CSD_STRUCT_VER_1_1  1           /* Valid for system specification 1.4 - 2.2 */
-#define CSD_STRUCT_VER_1_2  2           /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */
-#define CSD_STRUCT_EXT_CSD  3           /* Version is coded in CSD_STRUCTURE in EXT_CSD */
-
-#define CSD_SPEC_VER_0      0           /* Implements system specification 1.0 - 1.2 */
-#define CSD_SPEC_VER_1      1           /* Implements system specification 1.4 */
-#define CSD_SPEC_VER_2      2           /* Implements system specification 2.0 - 2.2 */
-#define CSD_SPEC_VER_3      3           /* Implements system specification 3.1 - 3.2 - 3.31 */
-#define CSD_SPEC_VER_4      4           /* Implements system specification 4.0 - 4.1 */
-
-/*
- * EXT_CSD fields
- */
-
-#define EXT_CSD_CMDQ_MODE_EN        15  /* R/W */
-#define EXT_CSD_FLUSH_CACHE     32      /* W */
-#define EXT_CSD_CACHE_CTRL      33      /* R/W */
-#define EXT_CSD_POWER_OFF_NOTIFICATION  34  /* R/W */
-#define EXT_CSD_PACKED_FAILURE_INDEX    35  /* RO */
-#define EXT_CSD_PACKED_CMD_STATUS   36  /* RO */
-#define EXT_CSD_EXP_EVENTS_STATUS   54  /* RO, 2 bytes */
-#define EXT_CSD_EXP_EVENTS_CTRL     56  /* R/W, 2 bytes */
-#define EXT_CSD_DATA_SECTOR_SIZE    61  /* R */
-#define EXT_CSD_GP_SIZE_MULT        143 /* R/W */
-#define EXT_CSD_PARTITION_SETTING_COMPLETED 155 /* R/W */
-#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
-#define EXT_CSD_PARTITION_SUPPORT   160 /* RO */
-#define EXT_CSD_HPI_MGMT        161 /* R/W */
-#define EXT_CSD_RST_N_FUNCTION      162 /* R/W */
-#define EXT_CSD_BKOPS_EN        163 /* R/W */
-#define EXT_CSD_BKOPS_START     164 /* W */
-#define EXT_CSD_SANITIZE_START      165     /* W */
-#define EXT_CSD_WR_REL_PARAM        166 /* RO */
-#define EXT_CSD_RPMB_MULT       168 /* RO */
-#define EXT_CSD_FW_CONFIG       169 /* R/W */
-#define EXT_CSD_BOOT_WP         173 /* R/W */
-#define EXT_CSD_ERASE_GROUP_DEF     175 /* R/W */
-#define EXT_CSD_PART_CONFIG     179 /* R/W */
-#define EXT_CSD_ERASED_MEM_CONT     181 /* RO */
-#define EXT_CSD_BUS_WIDTH       183 /* R/W */
-#define EXT_CSD_STROBE_SUPPORT      184 /* RO */
-#define EXT_CSD_HS_TIMING       185 /* R/W */
-#define EXT_CSD_POWER_CLASS     187 /* R/W */
-#define EXT_CSD_REV         192 /* RO */
-#define EXT_CSD_STRUCTURE       194 /* RO */
-#define EXT_CSD_CARD_TYPE       196 /* RO */
-#define EXT_CSD_DRIVER_STRENGTH     197 /* RO */
-#define EXT_CSD_OUT_OF_INTERRUPT_TIME   198 /* RO */
-#define EXT_CSD_PART_SWITCH_TIME        199     /* RO */
-#define EXT_CSD_PWR_CL_52_195       200 /* RO */
-#define EXT_CSD_PWR_CL_26_195       201 /* RO */
-#define EXT_CSD_PWR_CL_52_360       202 /* RO */
-#define EXT_CSD_PWR_CL_26_360       203 /* RO */
-#define EXT_CSD_SEC_CNT         212 /* RO, 4 bytes */
-#define EXT_CSD_S_A_TIMEOUT     217 /* RO */
-#define EXT_CSD_REL_WR_SEC_C        222 /* RO */
-#define EXT_CSD_HC_WP_GRP_SIZE      221 /* RO */
-#define EXT_CSD_ERASE_TIMEOUT_MULT  223 /* RO */
-#define EXT_CSD_HC_ERASE_GRP_SIZE   224 /* RO */
-#define EXT_CSD_BOOT_MULT       226 /* RO */
-#define EXT_CSD_SEC_TRIM_MULT       229 /* RO */
-#define EXT_CSD_SEC_ERASE_MULT      230 /* RO */
-#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
-#define EXT_CSD_TRIM_MULT       232 /* RO */
-#define EXT_CSD_PWR_CL_200_195      236 /* RO */
-#define EXT_CSD_PWR_CL_200_360      237 /* RO */
-#define EXT_CSD_PWR_CL_DDR_52_195   238 /* RO */
-#define EXT_CSD_PWR_CL_DDR_52_360   239 /* RO */
-#define EXT_CSD_BKOPS_STATUS        246 /* RO */
-#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */
-#define EXT_CSD_GENERIC_CMD6_TIME   248 /* RO */
-#define EXT_CSD_CACHE_SIZE      249 /* RO, 4 bytes */
-#define EXT_CSD_PWR_CL_DDR_200_360  253 /* RO */
-#define EXT_CSD_FIRMWARE_VERSION    254 /* RO, 8 bytes */
-#define EXT_CSD_PRE_EOL_INFO        267 /* RO */
-#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A  268 /* RO */
-#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B  269 /* RO */
-#define EXT_CSD_CMDQ_DEPTH      307 /* RO */
-#define EXT_CSD_CMDQ_SUPPORT        308 /* RO */
-#define EXT_CSD_SUPPORTED_MODE      493 /* RO */
-#define EXT_CSD_TAG_UNIT_SIZE       498 /* RO */
-#define EXT_CSD_DATA_TAG_SUPPORT    499 /* RO */
-#define EXT_CSD_MAX_PACKED_WRITES   500 /* RO */
-#define EXT_CSD_MAX_PACKED_READS    501 /* RO */
-#define EXT_CSD_BKOPS_SUPPORT       502 /* RO */
-#define EXT_CSD_HPI_FEATURES        503 /* RO */
-
-/*
- * EXT_CSD field definitions
- */
-
-#define EXT_CSD_WR_REL_PARAM_EN     (1<<2)
-
-#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS    (0x40)
-#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS   (0x10)
-#define EXT_CSD_BOOT_WP_B_PERM_WP_EN    (0x04)
-#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01)
-
-#define EXT_CSD_PART_CONFIG_ACC_MASK    (0x7)
-#define EXT_CSD_PART_CONFIG_ACC_BOOT0   (0x1)
-#define EXT_CSD_PART_CONFIG_ACC_RPMB    (0x3)
-#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4)
-
-#define EXT_CSD_PART_SETTING_COMPLETED  (0x1)
-#define EXT_CSD_PART_SUPPORT_PART_EN    (0x1)
-
-#define EXT_CSD_CMD_SET_NORMAL      (1<<0)
-#define EXT_CSD_CMD_SET_SECURE      (1<<1)
-#define EXT_CSD_CMD_SET_CPSECURE    (1<<2)
-
-#define EXT_CSD_CARD_TYPE_HS_26 (1<<0)  /* Card can run at 26MHz */
-#define EXT_CSD_CARD_TYPE_HS_52 (1<<1)  /* Card can run at 52MHz */
-#define EXT_CSD_CARD_TYPE_HS    (EXT_CSD_CARD_TYPE_HS_26 | \
-                 EXT_CSD_CARD_TYPE_HS_52)
-#define EXT_CSD_CARD_TYPE_DDR_1_8V  (1<<2)   /* Card can run at 52MHz */
-                         /* DDR mode @1.8V or 3V I/O */
-#define EXT_CSD_CARD_TYPE_DDR_1_2V  (1<<3)   /* Card can run at 52MHz */
-                         /* DDR mode @1.2V I/O */
-#define EXT_CSD_CARD_TYPE_DDR_52       (EXT_CSD_CARD_TYPE_DDR_1_8V  \
-                    | EXT_CSD_CARD_TYPE_DDR_1_2V)
-#define EXT_CSD_CARD_TYPE_HS200_1_8V    (1<<4)  /* Card can run at 200MHz */
-#define EXT_CSD_CARD_TYPE_HS200_1_2V    (1<<5)  /* Card can run at 200MHz */
-                        /* SDR mode @1.2V I/O */
-#define EXT_CSD_CARD_TYPE_HS200     (EXT_CSD_CARD_TYPE_HS200_1_8V | \
-                     EXT_CSD_CARD_TYPE_HS200_1_2V)
-#define EXT_CSD_CARD_TYPE_HS400_1_8V    (1<<6)  /* Card can run at 200MHz DDR, 1.8V */
-#define EXT_CSD_CARD_TYPE_HS400_1_2V    (1<<7)  /* Card can run at 200MHz DDR, 1.2V */
-#define EXT_CSD_CARD_TYPE_HS400     (EXT_CSD_CARD_TYPE_HS400_1_8V | \
-                     EXT_CSD_CARD_TYPE_HS400_1_2V)
-#define EXT_CSD_CARD_TYPE_HS400ES   (1<<8)  /* Card can run at HS400ES */
-
-#define EXT_CSD_BUS_WIDTH_1 0   /* Card is in 1 bit mode */
-#define EXT_CSD_BUS_WIDTH_4 1   /* Card is in 4 bit mode */
-#define EXT_CSD_BUS_WIDTH_8 2   /* Card is in 8 bit mode */
-#define EXT_CSD_DDR_BUS_WIDTH_4 5   /* Card is in 4 bit DDR mode */
-#define EXT_CSD_DDR_BUS_WIDTH_8 6   /* Card is in 8 bit DDR mode */
-#define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */
-
-#define EXT_CSD_TIMING_BC   0   /* Backwards compatility */
-#define EXT_CSD_TIMING_HS   1   /* High speed */
-#define EXT_CSD_TIMING_HS200    2   /* HS200 */
-#define EXT_CSD_TIMING_HS400    3   /* HS400 */
-#define EXT_CSD_DRV_STR_SHIFT   4   /* Driver Strength shift */
-
-#define EXT_CSD_SEC_ER_EN   BIT(0)
-#define EXT_CSD_SEC_BD_BLK_EN   BIT(2)
-#define EXT_CSD_SEC_GB_CL_EN    BIT(4)
-#define EXT_CSD_SEC_SANITIZE    BIT(6)  /* v4.5 only */
-
-#define EXT_CSD_RST_N_EN_MASK   0x3
-#define EXT_CSD_RST_N_ENABLED   1   /* RST_n is enabled on card */
-
-#define EXT_CSD_NO_POWER_NOTIFICATION   0
-#define EXT_CSD_POWER_ON        1
-#define EXT_CSD_POWER_OFF_SHORT     2
-#define EXT_CSD_POWER_OFF_LONG      3
-
-#define EXT_CSD_PWR_CL_8BIT_MASK    0xF0    /* 8 bit PWR CLS */
-#define EXT_CSD_PWR_CL_4BIT_MASK    0x0F    /* 8 bit PWR CLS */
-#define EXT_CSD_PWR_CL_8BIT_SHIFT   4
-#define EXT_CSD_PWR_CL_4BIT_SHIFT   0
-
-#define EXT_CSD_PACKED_EVENT_EN BIT(3)
-
-/*
- * EXCEPTION_EVENT_STATUS field
- */
-#define EXT_CSD_URGENT_BKOPS        BIT(0)
-#define EXT_CSD_DYNCAP_NEEDED       BIT(1)
-#define EXT_CSD_SYSPOOL_EXHAUSTED   BIT(2)
-#define EXT_CSD_PACKED_FAILURE      BIT(3)
-
-#define EXT_CSD_PACKED_GENERIC_ERROR    BIT(0)
-#define EXT_CSD_PACKED_INDEXED_ERROR    BIT(1)
-
-/*
- * BKOPS status level
- */
-#define EXT_CSD_BKOPS_LEVEL_2       0x2
-
-/*
- * BKOPS modes
- */
-#define EXT_CSD_MANUAL_BKOPS_MASK   0x01
-#define EXT_CSD_AUTO_BKOPS_MASK     0x02
-
-/*
- * Command Queue
- */
-#define EXT_CSD_CMDQ_MODE_ENABLED   BIT(0)
-#define EXT_CSD_CMDQ_DEPTH_MASK     GENMASK(4, 0)
-#define EXT_CSD_CMDQ_SUPPORTED      BIT(0)
-
-/*
- * MMC_SWITCH access modes
- */
-#define MMC_SWITCH_MODE_CMD_SET     0x00    /* Change the command set */
-#define MMC_SWITCH_MODE_SET_BITS    0x01    /* Set bits which are 1 in value */
-#define MMC_SWITCH_MODE_CLEAR_BITS  0x02    /* Clear bits which are 1 in value */
-#define MMC_SWITCH_MODE_WRITE_BYTE  0x03    /* Set target to value */
-
-/*
- * Erase/trim/discard
- */
-#define MMC_ERASE_ARG           0x00000000
-#define MMC_SECURE_ERASE_ARG        0x80000000
-#define MMC_TRIM_ARG            0x00000001
-#define MMC_DISCARD_ARG         0x00000003
-#define MMC_SECURE_TRIM1_ARG        0x80000001
-#define MMC_SECURE_TRIM2_ARG        0x80008000
-#define MMC_SECURE_ARGS         0x80000000
-#define MMC_TRIM_ARGS           0x00008001
-
-#endif /* LINUX_MMC_MMC_H */

fusee/common/sdmmc/sd.h

@@ -1,155 +0,0 @@
-/*
- *  include/linux/mmc/sd.h
- *
- *  Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
- *  Copyright (C) 2018 CTCaer
- *  Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- */
-
-#ifndef LINUX_MMC_SD_H
-#define LINUX_MMC_SD_H
-
-/* SD commands                           type  argument     response */
-/* class 0 */
-/* This is basically the same command as for MMC with some quirks. */
-#define SD_SEND_RELATIVE_ADDR     3   /* bcr                     R6  */
-#define SD_SEND_IF_COND           8   /* bcr  [11:0] See below   R7  */
-#define SD_SWITCH_VOLTAGE         11  /* ac                      R1  */
-
-/* class 10 */
-#define SD_SWITCH                 6   /* adtc [31:0] See below   R1  */
-
-/* class 5 */
-#define SD_ERASE_WR_BLK_START    32   /* ac   [31:0] data addr   R1  */
-#define SD_ERASE_WR_BLK_END      33   /* ac   [31:0] data addr   R1  */
-
-/* Application commands */
-#define SD_APP_SET_BUS_WIDTH        6   /* ac   [1:0] bus width    R1  */
-#define SD_APP_SD_STATUS            13  /* adtc                    R1  */
-#define SD_APP_SEND_NUM_WR_BLKS     22  /* adtc                    R1  */
-#define SD_APP_OP_COND              41  /* bcr  [31:0] OCR         R3  */
-#define SD_APP_SET_CLR_CARD_DETECT  42  /* ac   [0] set cd         R1  */
-#define SD_APP_SEND_SCR             51  /* adtc                    R1  */
-
-/* OCR bit definitions */
-#define SD_OCR_S18R             (1 << 24)                   /* 1.8V switching request */
-#define SD_ROCR_S18A            SD_OCR_S18R                 /* 1.8V switching accepted by card */
-#define SD_OCR_XPC              (1 << 28)                   /* SDXC power control */
-#define SD_OCR_CCS              (1 << 30)                   /* Card Capacity Status */
-#define SD_OCR_VDD_LOW          (1 << 7)                    /* SD: Reserved for Low Voltage Range */
-#define SD_OCR_VDD_20_21        (1 << 8)
-#define SD_OCR_VDD_21_22        (1 << 9)
-#define SD_OCR_VDD_22_23        (1 << 10)
-#define SD_OCR_VDD_23_24        (1 << 11)
-#define SD_OCR_VDD_24_25        (1 << 12)
-#define SD_OCR_VDD_25_26        (1 << 13)
-#define SD_OCR_VDD_26_27        (1 << 14)
-#define SD_OCR_VDD_27_28        (1 << 15)
-#define SD_OCR_VDD_28_29        (1 << 16)
-#define SD_OCR_VDD_29_30        (1 << 17)
-#define SD_OCR_VDD_30_31        (1 << 18)
-#define SD_OCR_VDD_31_32        (1 << 19)
-#define SD_OCR_VDD_32_33        (1 << 20)
-#define SD_OCR_VDD_33_34        (1 << 21)
-#define SD_OCR_VDD_34_35        (1 << 22)
-#define SD_OCR_VDD_35_36        (1 << 23)
-
-/*
- * SD_SWITCH argument format:
- *
- *      [31] Check (0) or switch (1)
- *      [30:24] Reserved (0)
- *      [23:20] Function group 6
- *      [19:16] Function group 5
- *      [15:12] Function group 4
- *      [11:8] Function group 3
- *      [7:4] Function group 2
- *      [3:0] Function group 1
- */
-
-/*
- * SD_SEND_IF_COND argument format:
- *
- *  [31:12] Reserved (0)
- *  [11:8] Host Voltage Supply Flags
- *  [7:0] Check Pattern (0xAA)
- */
-
-/*
- * SCR field definitions
- */
-
-#define SD_SCR_SPEC_VER_0       0   /* Implements system specification 1.0 - 1.01 */
-#define SD_SCR_SPEC_VER_1       1   /* Implements system specification 1.10 */
-#define SD_SCR_SPEC_VER_2       2   /* Implements system specification 2.00-3.0X */
-#define SD_SCR_BUS_WIDTH_1      1
-#define SD_SCR_BUS_WIDTH_4      4
-#define SD_SCR_CMD20_SUPPORT    1
-#define SD_SCR_CMD23_SUPPORT    2
-
-/*
- * SD bus widths
- */
-#define SD_BUS_WIDTH_1      0
-#define SD_BUS_WIDTH_4      2
-
-/*
- * SD bus speed modes
- */
-#define UHS_SDR12_BUS_SPEED     0
-#define HIGH_SPEED_BUS_SPEED    1
-#define UHS_SDR25_BUS_SPEED     1
-#define UHS_SDR50_BUS_SPEED     2
-#define UHS_SDR104_BUS_SPEED    3
-#define UHS_DDR50_BUS_SPEED     4
-#define SD_MODE_HIGH_SPEED      (1 << HIGH_SPEED_BUS_SPEED)
-#define SD_MODE_UHS_SDR12       (1 << UHS_SDR12_BUS_SPEED)
-#define SD_MODE_UHS_SDR25       (1 << UHS_SDR25_BUS_SPEED)
-#define SD_MODE_UHS_SDR50       (1 << UHS_SDR50_BUS_SPEED)
-#define SD_MODE_UHS_SDR104      (1 << UHS_SDR104_BUS_SPEED)
-#define SD_MODE_UHS_DDR50       (1 << UHS_DDR50_BUS_SPEED)
-
-/*
- * SD bus driver types
- */
-#define SD_DRIVER_TYPE_B    0x01
-#define SD_DRIVER_TYPE_A    0x02
-#define SD_DRIVER_TYPE_C    0x04
-#define SD_DRIVER_TYPE_D    0x08
-
-/*
- * SD bus current limits
- */
-#define SD_SET_CURRENT_LIMIT_200    0
-#define SD_SET_CURRENT_LIMIT_400    1
-#define SD_SET_CURRENT_LIMIT_600    2
-#define SD_SET_CURRENT_LIMIT_800    3
-#define SD_SET_CURRENT_NO_CHANGE    (-1)
-#define SD_MAX_CURRENT_200          (1 << SD_SET_CURRENT_LIMIT_200)
-#define SD_MAX_CURRENT_400          (1 << SD_SET_CURRENT_LIMIT_400)
-#define SD_MAX_CURRENT_600          (1 << SD_SET_CURRENT_LIMIT_600)
-#define SD_MAX_CURRENT_800          (1 << SD_SET_CURRENT_LIMIT_800)
-
-/*
- * SD_SWITCH mode
- */
-#define SD_SWITCH_CHECK     0
-#define SD_SWITCH_SET       1
-
-/*
- * SD_SWITCH function groups
- */
-#define SD_SWITCH_GRP_ACCESS    0
-
-/*
- * SD_SWITCH access modes
- */
-#define SD_SWITCH_ACCESS_DEF    0
-#define SD_SWITCH_ACCESS_HS     1
-
-#endif /* LINUX_MMC_SD_H */

fusee/common/sdmmc/sdmmc.h

@@ -1,179 +0,0 @@
-/*
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018 CTCaer
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_SDMMC_H
-#define FUSEE_SDMMC_H
-
-#include "sdmmc_core.h"
-
-/* Structure for storing the MMC CID (adapted from Linux headers) */
-typedef struct {
-    uint32_t    manfid;
-    uint8_t     prod_name[8];
-    uint8_t     prv;
-    uint32_t    serial;
-    uint16_t    oemid;
-    uint16_t    year;
-    uint8_t     hwrev;
-    uint8_t     fwrev;
-    uint8_t     month;
-} mmc_cid_t;
-
-/* Structure for storing the MMC CSD (adapted from Linux headers) */
-typedef struct {
-    uint8_t     structure;
-    uint8_t     mmca_vsn;
-    uint16_t    cmdclass;
-    uint16_t    taac_clks;
-    uint32_t    taac_ns;
-    uint32_t    c_size;
-    uint32_t    r2w_factor;
-    uint32_t    max_dtr;
-    uint32_t    erase_size;     /* In sectors */
-    uint32_t    read_blkbits;
-    uint32_t    write_blkbits;
-    uint32_t    capacity;
-    uint32_t    read_partial:1,
-                read_misalign:1,
-                write_partial:1,
-                write_misalign:1,
-                dsr_imp:1;
-} mmc_csd_t;
-
-/* Structure for storing the MMC extended CSD (adapted from Linux headers) */
-typedef struct {
-    uint8_t     rev;
-    uint8_t     erase_group_def;
-    uint8_t     sec_feature_support;
-    uint8_t     rel_sectors;
-    uint8_t     rel_param;
-    uint8_t     part_config;
-    uint8_t     cache_ctrl;
-    uint8_t     rst_n_function;
-    uint8_t     max_packed_writes;
-    uint8_t     max_packed_reads;
-    uint8_t     packed_event_en;
-    uint32_t    part_time;                      /* Units: ms */
-    uint32_t    sa_timeout;                     /* Units: 100ns */
-    uint32_t    generic_cmd6_time;              /* Units: 10ms */
-    uint32_t    power_off_longtime;             /* Units: ms */
-    uint8_t     power_off_notification;         /* state */
-    uint32_t    hs_max_dtr;
-    uint32_t    hs200_max_dtr;
-    uint32_t    sectors;
-    uint32_t    hc_erase_size;                  /* In sectors */
-    uint32_t    hc_erase_timeout;               /* In milliseconds */
-    uint32_t    sec_trim_mult;                  /* Secure trim multiplier  */
-    uint32_t    sec_erase_mult;                 /* Secure erase multiplier */
-    uint32_t    trim_timeout;                   /* In milliseconds */
-    uint32_t    partition_setting_completed;    /* enable bit */
-    uint64_t    enhanced_area_offset;           /* Units: Byte */
-    uint32_t    enhanced_area_size;             /* Units: KB */
-    uint32_t    cache_size;                     /* Units: KB */
-    uint32_t    hpi_en;                         /* HPI enablebit */
-    uint32_t    hpi;                            /* HPI support bit */
-    uint32_t    hpi_cmd;                        /* cmd used as HPI */
-    uint32_t    bkops;                          /* background support bit */
-    uint32_t    man_bkops_en;                   /* manual bkops enable bit */
-    uint32_t    auto_bkops_en;                  /* auto bkops enable bit */
-    uint32_t    data_sector_size;               /* 512 bytes or 4KB */
-    uint32_t    data_tag_unit_size;             /* DATA TAG UNIT size */
-    uint32_t    boot_ro_lock;                   /* ro lock support */
-    uint32_t    boot_ro_lockable;
-    uint32_t    ffu_capable;                    /* Firmware upgrade support */
-    uint32_t    cmdq_en;                        /* Command Queue enabled */
-    uint32_t    cmdq_support;                   /* Command Queue supported */
-    uint32_t    cmdq_depth;                     /* Command Queue depth */
-    uint8_t     fwrev[8];                       /* FW version */
-    uint8_t     raw_exception_status;           /* 54 */
-    uint8_t     raw_partition_support;          /* 160 */
-    uint8_t     raw_rpmb_size_mult;             /* 168 */
-    uint8_t     raw_erased_mem_count;           /* 181 */
-    uint8_t     strobe_support;                 /* 184 */
-    uint8_t     raw_ext_csd_structure;          /* 194 */
-    uint8_t     raw_card_type;                  /* 196 */
-    uint8_t     raw_driver_strength;            /* 197 */
-    uint8_t     out_of_int_time;                /* 198 */
-    uint8_t     raw_pwr_cl_52_195;              /* 200 */
-    uint8_t     raw_pwr_cl_26_195;              /* 201 */
-    uint8_t     raw_pwr_cl_52_360;              /* 202 */
-    uint8_t     raw_pwr_cl_26_360;              /* 203 */
-    uint8_t     raw_s_a_timeout;                /* 217 */
-    uint8_t     raw_hc_erase_gap_size;          /* 221 */
-    uint8_t     raw_erase_timeout_mult;         /* 223 */
-    uint8_t     raw_hc_erase_grp_size;          /* 224 */
-    uint8_t     raw_sec_trim_mult;              /* 229 */
-    uint8_t     raw_sec_erase_mult;             /* 230 */
-    uint8_t     raw_sec_feature_support;        /* 231 */
-    uint8_t     raw_trim_mult;                  /* 232 */
-    uint8_t     raw_pwr_cl_200_195;             /* 236 */
-    uint8_t     raw_pwr_cl_200_360;             /* 237 */
-    uint8_t     raw_pwr_cl_ddr_52_195;          /* 238 */
-    uint8_t     raw_pwr_cl_ddr_52_360;          /* 239 */
-    uint8_t     raw_pwr_cl_ddr_200_360;         /* 253 */
-    uint8_t     raw_bkops_status;               /* 246 */
-    uint8_t     raw_sectors[4];                 /* 212 - 4 bytes */
-    uint8_t     pre_eol_info;                   /* 267 */
-    uint8_t     device_life_time_est_typ_a;     /* 268 */
-    uint8_t     device_life_time_est_typ_b;     /* 269 */
-    uint32_t    feature_support;
-} mmc_ext_csd_t;
-
-/* Structure for storing the SD SCR (adapted from Linux headers) */
-typedef struct  {
-    uint8_t     sda_vsn;
-    uint8_t     sda_spec3;
-    uint8_t     bus_widths;
-    uint8_t     cmds;
-} sd_scr_t;
-
-/* Structure for storing the SD SSR (adapted from Linux headers) */
-typedef struct  {
-    uint8_t     dat_bus_width;
-    uint8_t     secured_mode;
-    uint16_t    sd_card_type;
-    uint8_t     speed_class;
-    uint8_t     uhs_speed_grade;
-    uint8_t     uhs_au_size;
-    uint8_t     video_speed_class;
-    uint8_t     app_perf_class;
-} sd_ssr_t;
-
-/* Structure describing a SDMMC device's context. */
-typedef struct {
-    /* Underlying driver context. */
-    sdmmc_t *sdmmc;
-    
-    bool is_180v;
-    bool is_block_sdhc;
-    uint32_t rca;
-    mmc_cid_t cid;
-    mmc_csd_t csd;
-    mmc_ext_csd_t ext_csd;
-    sd_scr_t scr;
-    sd_ssr_t ssr;
-} sdmmc_device_t;
-
-int sdmmc_device_sd_init(sdmmc_device_t *device, sdmmc_t *sdmmc, SdmmcBusWidth bus_width, SdmmcBusSpeed bus_speed);
-int sdmmc_device_mmc_init(sdmmc_device_t *device, sdmmc_t *sdmmc, SdmmcBusWidth bus_width, SdmmcBusSpeed bus_speed);
-int sdmmc_device_read(sdmmc_device_t *device, uint32_t sector, uint32_t num_sectors, void *data);
-int sdmmc_device_write(sdmmc_device_t *device, uint32_t sector, uint32_t num_sectors, void *data);
-int sdmmc_device_finish(sdmmc_device_t *device);
-int sdmmc_mmc_select_partition(sdmmc_device_t *device, SdmmcPartitionNum partition);
-
-#endif

fusee/common/sdmmc/sdmmc_core.h

@@ -1,312 +0,0 @@
-/*
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018 CTCaer
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_SDMMC_CORE_H
-#define FUSEE_SDMMC_CORE_H
-
-#include "sdmmc_tegra.h"
-
-/* Bounce buffer */
-#define SDMMC_BOUNCE_BUFFER_ADDRESS     0x90000000
-
-/* Present state */
-#define SDHCI_CMD_INHIBIT       0x00000001
-#define SDHCI_DATA_INHIBIT      0x00000002
-#define SDHCI_DOING_WRITE       0x00000100
-#define SDHCI_DOING_READ        0x00000200
-#define SDHCI_SPACE_AVAILABLE   0x00000400
-#define SDHCI_DATA_AVAILABLE    0x00000800
-#define SDHCI_CARD_PRESENT      0x00010000
-#define SDHCI_WRITE_PROTECT     0x00080000
-#define SDHCI_DATA_LVL_MASK     0x00F00000
-#define SDHCI_DATA_LVL_SHIFT    20
-#define SDHCI_DATA_0_LVL_MASK   0x00100000
-#define SDHCI_CMD_LVL           0x01000000
-
-/* SDHCI clock control */
-#define SDHCI_DIVIDER_SHIFT     8
-#define SDHCI_DIVIDER_HI_SHIFT  6
-#define SDHCI_DIV_MASK          0xFF
-#define SDHCI_DIV_MASK_LEN      8
-#define SDHCI_DIV_HI_MASK       0x300
-#define SDHCI_PROG_CLOCK_MODE   0x0020
-#define SDHCI_CLOCK_CARD_EN     0x0004
-#define SDHCI_CLOCK_INT_STABLE  0x0002
-#define SDHCI_CLOCK_INT_EN      0x0001
-
-/* SDHCI host control */
-#define SDHCI_CTRL_LED          0x01
-#define SDHCI_CTRL_4BITBUS      0x02
-#define SDHCI_CTRL_HISPD        0x04
-#define SDHCI_CTRL_DMA_MASK     0x18
-#define SDHCI_CTRL_SDMA         0x00
-#define SDHCI_CTRL_ADMA1        0x08
-#define SDHCI_CTRL_ADMA32       0x10
-#define SDHCI_CTRL_ADMA64       0x18
-#define SDHCI_CTRL_8BITBUS      0x20
-#define SDHCI_CTRL_CDTEST_INS   0x40
-#define SDHCI_CTRL_CDTEST_EN    0x80
-
-/* SDHCI host control 2 */
-#define SDHCI_CTRL_UHS_MASK             0x0007
-#define SDHCI_CTRL_UHS_SDR12            0x0000
-#define SDHCI_CTRL_UHS_SDR25            0x0001
-#define SDHCI_CTRL_UHS_SDR50            0x0002
-#define SDHCI_CTRL_UHS_SDR104           0x0003
-#define SDHCI_CTRL_UHS_DDR50            0x0004
-#define SDHCI_CTRL_HS400                0x0005
-#define SDHCI_CTRL_VDD_180              0x0008
-#define SDHCI_CTRL_DRV_TYPE_MASK        0x0030
-#define SDHCI_CTRL_DRV_TYPE_B           0x0000
-#define SDHCI_CTRL_DRV_TYPE_A           0x0010
-#define SDHCI_CTRL_DRV_TYPE_C           0x0020
-#define SDHCI_CTRL_DRV_TYPE_D           0x0030
-#define SDHCI_CTRL_EXEC_TUNING          0x0040
-#define SDHCI_CTRL_TUNED_CLK            0x0080
-#define SDHCI_UHS2_IF_EN                0x0100
-#define SDHCI_HOST_VERSION_4_EN         0x1000
-#define SDHCI_ADDRESSING_64BIT_EN       0x2000
-#define SDHCI_ASYNC_INTR_EN             0x4000
-#define SDHCI_CTRL_PRESET_VAL_ENABLE    0x8000
-
-/* SDHCI capabilities */
-#define SDHCI_CAN_DO_8BIT   0x00040000
-#define SDHCI_CAN_DO_ADMA2  0x00080000
-#define SDHCI_CAN_DO_ADMA1  0x00100000
-#define SDHCI_CAN_DO_HISPD  0x00200000
-#define SDHCI_CAN_DO_SDMA   0x00400000
-#define SDHCI_CAN_VDD_330   0x01000000
-#define SDHCI_CAN_VDD_300   0x02000000
-#define SDHCI_CAN_VDD_180   0x04000000
-#define SDHCI_CAN_64BIT     0x10000000
-#define SDHCI_ASYNC_INTR    0x20000000
-
-/* Vendor clock control */
-#define SDMMC_CLOCK_TAP_MASK                    (0xFF << 16)
-#define SDMMC_CLOCK_TAP_SDMMC1                  (0x04 << 16)
-#define SDMMC_CLOCK_TAP_SDMMC2                  (0x00 << 16)
-#define SDMMC_CLOCK_TAP_SDMMC3                  (0x03 << 16)
-#define SDMMC_CLOCK_TAP_SDMMC4                  (0x00 << 16)
-#define SDMMC_CLOCK_TRIM_MASK                   (0xFF << 24)
-#define SDMMC_CLOCK_TRIM_SDMMC1_ERISTA          (0x02 << 24)
-#define SDMMC_CLOCK_TRIM_SDMMC1_MARIKO          (0x0E << 24)
-#define SDMMC_CLOCK_TRIM_SDMMC2_ERISTA          (0x08 << 24)
-#define SDMMC_CLOCK_TRIM_SDMMC2_MARIKO          (0x0D << 24)
-#define SDMMC_CLOCK_TRIM_SDMMC3                 (0x03 << 24)
-#define SDMMC_CLOCK_TRIM_SDMMC4_ERISTA          (0x08 << 24)
-#define SDMMC_CLOCK_TRIM_SDMMC4_MARIKO          (0x0D << 24)
-#define SDMMC_CLOCK_SPI_MODE_CLKEN_OVERRIDE     (1 << 2)
-#define SDMMC_CLOCK_PADPIPE_CLKEN_OVERRIDE      (1 << 3)
-
-/* Autocal configuration */
-#define SDMMC_AUTOCAL_PDPU_CONFIG_MASK          0x7F7F
-#define SDMMC_AUTOCAL_PDPU_SDMMC1_1V8_ERISTA    0x7B7B
-#define SDMMC_AUTOCAL_PDPU_SDMMC1_1V8_MARIKO    0x0606
-#define SDMMC_AUTOCAL_PDPU_SDMMC1_3V3_ERISTA    0x7D00
-#define SDMMC_AUTOCAL_PDPU_SDMMC1_3V3_MARIKO    0x0000
-#define SDMMC_AUTOCAL_PDPU_SDMMC4_1V8           0x0505
-#define SDMMC_AUTOCAL_START                     (1 << 31)
-#define SDMMC_AUTOCAL_ENABLE                    (1 << 29)
-
-/* Autocal status */
-#define SDMMC_AUTOCAL_ACTIVE                    (1 << 31)
-
-/* Vendor tuning control 0*/
-#define SDMMC_VENDOR_TUNING_TRIES_MASK          (0x7 << 13)
-#define SDMMC_VENDOR_TUNING_TRIES_SHIFT          13
-#define SDMMC_VENDOR_TUNING_MULTIPLIER_MASK     (0x7F << 6)
-#define SDMMC_VENDOR_TUNING_MULTIPLIER_UNITY    (1 << 6)
-#define SDMMC_VENDOR_TUNING_DIVIDER_MASK        (0x7 << 3)
-#define SDMMC_VENDOR_TUNING_SET_BY_HW           (1 << 17)
-
-/* Vendor tuning control 1*/
-#define SDMMC_VENDOR_TUNING_STEP_SIZE_SDR50_DEFAULT     (0 << 0)
-#define SDMMC_VENDOR_TUNING_STEP_SIZE_SDR104_DEFAULT    (0 << 4)
-
-/* Vendor capability overrides */
-#define SDMMC_VENDOR_CAPABILITY_DQS_TRIM_MASK           (0x3F << 8)
-#define SDMMC_VENDOR_CAPABILITY_DQS_TRIM_HS400          (0x11 << 8)
-
-/* Timeouts */
-#define SDMMC_AUTOCAL_TIMEOUT                           (10 * 1000)
-#define SDMMC_TUNING_TIMEOUT                            (150 * 1000)
-
-/* Command response flags */
-#define SDMMC_RSP_PRESENT                               (1 << 0)
-#define SDMMC_RSP_136                                   (1 << 1)
-#define SDMMC_RSP_CRC                                   (1 << 2)
-#define SDMMC_RSP_BUSY                                  (1 << 3)
-#define SDMMC_RSP_OPCODE                                (1 << 4)
-
-/* Command types */
-#define SDMMC_CMD_MASK                                  (3 << 5)
-#define SDMMC_CMD_AC                                    (0 << 5)
-#define SDMMC_CMD_ADTC                                  (1 << 5)
-#define SDMMC_CMD_BC                                    (2 << 5)
-#define SDMMC_CMD_BCR                                   (3 << 5)
-
-/* SPI command response flags */
-#define SDMMC_RSP_SPI_S1                                (1 << 7)
-#define SDMMC_RSP_SPI_S2                                (1 << 8)
-#define SDMMC_RSP_SPI_B4                                (1 << 9)
-#define SDMMC_RSP_SPI_BUSY                              (1 << 10)
-
-/* Native response types for commands */
-#define SDMMC_RSP_NONE          (0)
-#define SDMMC_RSP_R1            (SDMMC_RSP_PRESENT|SDMMC_RSP_CRC|SDMMC_RSP_OPCODE)
-#define SDMMC_RSP_R1B           (SDMMC_RSP_PRESENT|SDMMC_RSP_CRC|SDMMC_RSP_OPCODE|SDMMC_RSP_BUSY)
-#define SDMMC_RSP_R2            (SDMMC_RSP_PRESENT|SDMMC_RSP_136|SDMMC_RSP_CRC)
-#define SDMMC_RSP_R3            (SDMMC_RSP_PRESENT)
-#define SDMMC_RSP_R4            (SDMMC_RSP_PRESENT)
-#define SDMMC_RSP_R5            (SDMMC_RSP_PRESENT|SDMMC_RSP_CRC|SDMMC_RSP_OPCODE)
-#define SDMMC_RSP_R6            (SDMMC_RSP_PRESENT|SDMMC_RSP_CRC|SDMMC_RSP_OPCODE)
-#define SDMMC_RSP_R7            (SDMMC_RSP_PRESENT|SDMMC_RSP_CRC|SDMMC_RSP_OPCODE)
-#define SDMMC_RSP_R1_NO_CRC     (SDMMC_RSP_PRESENT|SDMMC_RSP_OPCODE)
-
-/* SPI response types for commands */
-#define SDMMC_RSP_SPI_R1        (SDMMC_RSP_SPI_S1)
-#define SDMMC_RSP_SPI_R1B       (SDMMC_RSP_SPI_S1|SDMMC_RSP_SPI_BUSY)
-#define SDMMC_RSP_SPI_R2        (SDMMC_RSP_SPI_S1|SDMMC_RSP_SPI_S2)
-#define SDMMC_RSP_SPI_R3        (SDMMC_RSP_SPI_S1|SDMMC_RSP_SPI_B4)
-#define SDMMC_RSP_SPI_R4        (SDMMC_RSP_SPI_S1|SDMMC_RSP_SPI_B4)
-#define SDMMC_RSP_SPI_R5        (SDMMC_RSP_SPI_S1|SDMMC_RSP_SPI_S2)
-#define SDMMC_RSP_SPI_R7        (SDMMC_RSP_SPI_S1|SDMMC_RSP_SPI_B4)
-
-/* SDMMC controllers */
-typedef enum {
-    SDMMC_1 = 0,
-    SDMMC_2 = 1,
-    SDMMC_3 = 2,
-    SDMMC_4 = 3
-} SdmmcControllerNum;
-
-typedef enum {
-    SDMMC_PARTITION_INVALID = -1,
-    SDMMC_PARTITION_USER    = 0,
-    SDMMC_PARTITION_BOOT0   = 1,
-    SDMMC_PARTITION_BOOT1   = 2,
-    SDMMC_PARTITION_RPMB    = 3
-} SdmmcPartitionNum;
-
-typedef enum {
-    SDMMC_VOLTAGE_NONE  = 0,
-    SDMMC_VOLTAGE_1V8   = 1,
-    SDMMC_VOLTAGE_3V3   = 2
-} SdmmcBusVoltage;
-
-typedef enum {
-    SDMMC_BUS_WIDTH_1BIT  = 0,
-    SDMMC_BUS_WIDTH_4BIT  = 1,
-    SDMMC_BUS_WIDTH_8BIT  = 2
-} SdmmcBusWidth;
-
-typedef enum {
-    SDMMC_SPEED_MMC_IDENT       = 0,
-    SDMMC_SPEED_MMC_LEGACY      = 1,
-    SDMMC_SPEED_MMC_HS          = 2,
-    SDMMC_SPEED_MMC_HS200       = 3,
-    SDMMC_SPEED_MMC_HS400       = 4,
-    SDMMC_SPEED_SD_IDENT        = 5,
-    SDMMC_SPEED_SD_DS           = 6,
-    SDMMC_SPEED_SD_HS           = 7,
-    SDMMC_SPEED_SD_SDR12        = 8,
-    SDMMC_SPEED_SD_SDR25        = 9,
-    SDMMC_SPEED_SD_SDR50        = 10,
-    SDMMC_SPEED_SD_SDR104       = 11,
-    SDMMC_SPEED_SD_DDR50        = 12,
-    SDMMC_SPEED_GC_ASIC_FPGA    = 13,
-    SDMMC_SPEED_GC_ASIC         = 14,
-    SDMMC_SPEED_EMU_SDR104      = 255, /* Custom speed mode. Prevents low voltage switch in MMC emulation. */
-} SdmmcBusSpeed;
-
-typedef enum {
-    SDMMC_CAR_DIVIDER_MMC_LEGACY        = 30, /* (16 * 2) - 2 */
-    SDMMC_CAR_DIVIDER_MMC_HS            = 14, /* (8 * 2) - 2 */
-    SDMMC_CAR_DIVIDER_MMC_HS200         = 3,  /* (2.5 * 2) - 2 (for PLLP_OUT0, same as HS400) */
-    SDMMC_CAR_DIVIDER_SD_SDR12          = 31, /* (16.5 * 2) - 2 */
-    SDMMC_CAR_DIVIDER_SD_SDR25          = 15, /* (8.5 * 2) - 2 */
-    SDMMC_CAR_DIVIDER_SD_SDR50          = 7,  /* (4.5 * 2) - 2 */
-    SDMMC_CAR_DIVIDER_SD_SDR104         = 2,  /* (2 * 2) - 2 */
-    SDMMC_CAR_DIVIDER_GC_ASIC_FPGA      = 18, /* (5 * 2 * 2) - 2 */
-} SdmmcCarDivider;
-
-/* Structure for describing a SDMMC device. */
-typedef struct {
-    /* Controller number */
-    SdmmcControllerNum controller;
-    
-    /* Backing register space */
-    volatile tegra_sdmmc_t *regs;
-    
-    /* Controller properties */
-    const char *name;
-    bool has_sd;
-    bool is_clk_running;
-    bool is_sd_clk_enabled;
-    bool is_tuning_tap_val_set;
-    bool use_adma;
-    uint32_t tap_val;
-    uint32_t internal_divider;
-    uint32_t resp[4];
-    uint32_t resp_auto_cmd12;
-    uint32_t next_dma_addr;
-    uint8_t* dma_bounce_buf;
-    SdmmcBusVoltage bus_voltage;
-    SdmmcBusWidth bus_width;
-    
-    /* Per-controller operations. */
-    int (*sdmmc_config)();
-} sdmmc_t;
-
-/* Structure for describing a SDMMC command. */
-typedef struct {
-    uint32_t    opcode;
-    uint32_t    arg;
-    uint32_t    resp[4];
-    uint32_t    flags;      /* Expected response type. */
-} sdmmc_command_t;
-
-/* Structure for describing a SDMMC request. */
-typedef struct {
-    void*       data;
-    uint32_t    blksz;
-    uint32_t    num_blocks;
-    bool        is_multi_block;
-    bool        is_read;
-    bool        is_auto_cmd12;
-} sdmmc_request_t;
-
-int sdmmc_init(sdmmc_t *sdmmc, SdmmcControllerNum controller, SdmmcBusVoltage bus_voltage, SdmmcBusWidth bus_width, SdmmcBusSpeed bus_speed);
-void sdmmc_finish(sdmmc_t *sdmmc);
-int sdmmc_select_speed(sdmmc_t *sdmmc, SdmmcBusSpeed bus_speed);
-void sdmmc_select_bus_width(sdmmc_t *sdmmc, SdmmcBusWidth width);
-void sdmmc_select_voltage(sdmmc_t *sdmmc, SdmmcBusVoltage voltage);
-void sdmmc_adjust_sd_clock(sdmmc_t *sdmmc);
-int sdmmc_switch_voltage(sdmmc_t *sdmmc);
-void sdmmc_set_tuning_tap_val(sdmmc_t *sdmmc);
-int sdmmc_execute_tuning(sdmmc_t *sdmmc, SdmmcBusSpeed bus_speed, uint32_t opcode);
-int sdmmc_send_cmd(sdmmc_t *sdmmc, sdmmc_command_t *cmd, sdmmc_request_t *req, uint32_t *num_blocks_out);
-int sdmmc_load_response(sdmmc_t *sdmmc, uint32_t flags, uint32_t *resp);
-int sdmmc_abort(sdmmc_t *sdmmc, uint32_t opcode);
-void sdmmc_error(sdmmc_t *sdmmc, char *fmt, ...);
-void sdmmc_warn(sdmmc_t *sdmmc, char *fmt, ...);
-void sdmmc_info(sdmmc_t *sdmmc, char *fmt, ...);
-void sdmmc_debug(sdmmc_t *sdmmc, char *fmt, ...);
-void sdmmc_dump_regs(sdmmc_t *sdmmc);
-
-#endif

fusee/common/sdmmc/sdmmc_tegra.h

@@ -1,172 +0,0 @@
-/*
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018 CTCaer
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_SDMMC_TEGRA_H
-#define FUSEE_SDMMC_TEGRA_H
-
-#include <stdbool.h>
-#include <stdint.h>
-
-#define TEGRA_MMC_PWRCTL_SD_BUS_POWER                           (1 << 0)
-#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8                    (5 << 1)
-#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0                    (6 << 1)
-#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3                    (7 << 1)
-
-#define TEGRA_MMC_HOSTCTL_DMASEL_MASK                           (3 << 3)
-#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA                           (0 << 3)
-#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT                    (2 << 3)
-#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT                    (3 << 3)
-
-#define TEGRA_MMC_TRNMOD_DMA_ENABLE                             (1 << 0)
-#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE                     (1 << 1)
-#define TEGRA_MMC_TRNMOD_AUTO_CMD12                             (1 << 2)
-#define TEGRA_MMC_TRNMOD_AUTO_CMD23                             (1 << 3)
-#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE                (0 << 4)
-#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ                 (1 << 4)
-#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT                     (1 << 5)
-
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK                  (3 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE           (0 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136            (1 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48             (2 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY        (3 << 0)
-
-#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK                          (1 << 3)
-#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK                        (1 << 4)
-#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER      (1 << 5)
-
-#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD                        (1 << 0)
-#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT                        (1 << 1)
-
-#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE                  (1 << 0)
-#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE                  (1 << 1)
-#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE                        (1 << 2)
-#define TEGRA_MMC_CLKCON_PROG_CLOCK_MODE                        (1 << 5)
-
-#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT                   8
-#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK                    (0xff << 8)
-
-#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL                        (1 << 0)
-#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE                   (1 << 1)
-#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE                   (1 << 2)
-
-#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE                        (1 << 0)
-#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE                       (1 << 1)
-#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT                       (1 << 3)
-#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT                       (1 << 15)
-#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT                         (1 << 16)
-
-#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE                      (1 << 0)
-#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE                     (1 << 1)
-#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT                     (1 << 3)
-#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY                (1 << 4)
-#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY                 (1 << 5)
-
-#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE                     (1 << 1)
-
-typedef struct {
-    /* SDHCI standard registers */
-    uint32_t dma_address;
-    uint16_t block_size;
-    uint16_t block_count;
-    uint32_t argument;
-    uint16_t transfer_mode;
-    uint16_t command;
-    uint32_t response[0x4];
-    uint32_t buffer;
-    uint32_t present_state;
-    uint8_t host_control;
-    uint8_t power_control;
-    uint8_t block_gap_control;
-    uint8_t wake_up_control;
-    uint16_t clock_control;
-    uint8_t timeout_control;
-    uint8_t software_reset;
-    uint32_t int_status;
-    uint32_t int_enable;
-    uint32_t signal_enable;
-    uint16_t acmd12_err;
-    uint16_t host_control2;
-    uint32_t capabilities;
-    uint32_t capabilities_1;
-    uint32_t max_current;
-    uint32_t _0x4c;
-    uint16_t set_acmd12_error;
-    uint16_t set_int_error;
-    uint8_t adma_error;
-    uint8_t _0x56[0x3];
-    uint32_t adma_address;
-    uint32_t upper_adma_address;
-    uint16_t preset_for_init;
-    uint16_t preset_for_default;
-    uint16_t preset_for_high;
-    uint16_t preset_for_sdr12;
-    uint16_t preset_for_sdr25;
-    uint16_t preset_for_sdr50;
-    uint16_t preset_for_sdr104;
-    uint16_t preset_for_ddr50;
-    uint32_t _0x70[0x23];
-    uint16_t slot_int_status;
-    uint16_t host_version;
-
-    /* Vendor specific registers */
-    uint32_t vendor_clock_cntrl;
-    uint32_t vendor_sys_sw_cntrl;
-    uint32_t vendor_err_intr_status;
-    uint32_t vendor_cap_overrides;
-    uint32_t vendor_boot_cntrl;
-    uint32_t vendor_boot_ack_timeout;
-    uint32_t vendor_boot_dat_timeout;
-    uint32_t vendor_debounce_count;
-    uint32_t vendor_misc_cntrl;
-    uint32_t max_current_override;
-    uint32_t max_current_override_hi;
-    uint32_t _0x12c[0x20];
-    uint32_t vendor_io_trim_cntrl;
-
-    /* Start of sdmmc2/sdmmc4 only */
-    uint32_t vendor_dllcal_cfg;
-    uint32_t vendor_dll_ctrl0;
-    uint32_t vendor_dll_ctrl1;
-    uint32_t vendor_dllcal_cfg_sta;
-    /* End of sdmmc2/sdmmc4 only */
-
-    uint32_t vendor_tuning_cntrl0;
-    uint32_t vendor_tuning_cntrl1;
-    uint32_t vendor_tuning_status0;
-    uint32_t vendor_tuning_status1;
-    uint32_t vendor_clk_gate_hysteresis_count;
-    uint32_t vendor_preset_val0;
-    uint32_t vendor_preset_val1;
-    uint32_t vendor_preset_val2;
-    uint32_t sdmemcomppadctrl;
-    uint32_t auto_cal_config;
-    uint32_t auto_cal_interval;
-    uint32_t auto_cal_status;
-    uint32_t io_spare;
-    uint32_t sdmmca_mccif_fifoctrl;
-    uint32_t timeout_wcoal_sdmmca;
-    uint32_t _0x1fc;
-} tegra_sdmmc_t;
-
-static inline volatile tegra_sdmmc_t *sdmmc_get_regs(uint32_t idx)
-{
-    return (volatile tegra_sdmmc_t *)(0x700B0000 + (idx * 0x200));
-}
-
-#endif

fusee/common/vsprintf.h

@@ -1,28 +0,0 @@
-/*
- *  Copyright (C) 2011 Andrei Warkentin <andrey.warkentin@gmail.com>
- *
- * This program is free software ; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <stdarg.h>
-#include <stdlib.h>
-
-#ifndef VSPRINTF_H
-#define VSPRINTF_H
-
-struct va_format {
-        const char *fmt;
-        va_list *va;
-};
-
-unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int base);
-
-int sprintf(char *buf, const char *fmt, ...);
-int scnprintf(char *buf, size_t size, const char *fmt, ...);
-int snprintf(char *buf, size_t size, const char *fmt, ...);
-int vsnprintf(char *buf, size_t size, const char *fmt, va_list args);
-int sscanf(const char *buf, const char *fmt, ...);
-
-#endif /* VSPRINTF_H */

fusee/fusee-mtc/Makefile

@@ -1,166 +0,0 @@
-#---------------------------------------------------------------------------------
-.SUFFIXES:
-#---------------------------------------------------------------------------------
-
-ifeq ($(strip $(DEVKITARM)),)
-$(error "Please set DEVKITARM in your environment. export DEVKITARM=<path to>devkitARM")
-endif
-
-TOPDIR ?= $(CURDIR)
-
-AMS		:= $(TOPDIR)/../../
-include $(DEVKITARM)/base_rules
-
-AMSBRANCH := $(shell git symbolic-ref --short HEAD)
-AMSREV := $(AMSBRANCH)-$(shell git rev-parse --short HEAD)
-
-ifneq (, $(strip $(shell git status --porcelain 2>/dev/null)))
-    AMSREV := $(AMSREV)-dirty
-endif
-
-#---------------------------------------------------------------------------------
-# TARGET is the name of the output
-# BUILD is the directory where object files & intermediate files will be placed
-# SOURCES is a list of directories containing source code
-# DATA is a list of directories containing data files
-# INCLUDES is a list of directories containing header files
-#---------------------------------------------------------------------------------
-TARGET		:=	$(notdir $(CURDIR))
-BUILD		:=	build
-SOURCES		:=	src ../../fusee/common ../../fusee/common/display
-DATA		:=	data
-INCLUDES	:=	include ../../libraries/libvapours/include
-
-#---------------------------------------------------------------------------------
-# options for code generation
-#---------------------------------------------------------------------------------
-ARCH	:=	-march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork
-DEFINES :=	-D__BPMP__ -DFUSEE_MTC_SRC -DATMOSPHERE_GIT_BRANCH=\"$(AMSBRANCH)\" -DATMOSPHERE_GIT_REV=\"$(AMSREV)\"
-
-CFLAGS	:= \
-	-g \
-	-O2 \
-	-fomit-frame-pointer \
-	-ffunction-sections \
-	-fdata-sections \
-	-std=gnu11 \
-	-Werror \
-	-Wall \
-	-Wno-array-bounds \
-	-Wno-stringop-overflow \
-	-Wno-stringop-overread \
-	-fstrict-volatile-bitfields \
-	$(ARCH) $(DEFINES)
-
-CFLAGS	+=	$(INCLUDE)
-
-CXXFLAGS	:= $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11
-
-ASFLAGS	:=	-g $(ARCH)
-LDFLAGS	=	-specs=$(TOPDIR)/linker.specs -g $(ARCH) -Wl,-Map,$(notdir $*.map)
-
-LIBS	:=
-
-#---------------------------------------------------------------------------------
-# list of directories containing libraries, this must be the top level containing
-# include and lib
-#---------------------------------------------------------------------------------
-LIBDIRS	:=
-
-
-#---------------------------------------------------------------------------------
-# no real need to edit anything past this point unless you need to add additional
-# rules for different file extensions
-#---------------------------------------------------------------------------------
-ifneq ($(BUILD),$(notdir $(CURDIR)))
-#---------------------------------------------------------------------------------
-
-export OUTPUT	:=	$(CURDIR)/$(TARGET)
-export TOPDIR	:=	$(CURDIR)
-
-export VPATH	:=	$(foreach dir,$(SOURCES),$(CURDIR)/$(dir)) \
-			$(foreach dir,$(DATA),$(CURDIR)/$(dir))
-
-export DEPSDIR	:=	$(CURDIR)/$(BUILD)
-
-CFILES		:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.c)))
-CPPFILES	:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.cpp)))
-SFILES		:=	$(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.s)))
-BINFILES	:=	$(foreach dir,$(DATA),$(notdir $(wildcard $(dir)/*.*)))
-
-#---------------------------------------------------------------------------------
-# use CXX for linking C++ projects, CC for standard C
-#---------------------------------------------------------------------------------
-ifeq ($(strip $(CPPFILES)),)
-#---------------------------------------------------------------------------------
-	export LD	:=	$(CC)
-#---------------------------------------------------------------------------------
-else
-#---------------------------------------------------------------------------------
-	export LD	:=	$(CXX)
-#---------------------------------------------------------------------------------
-endif
-#---------------------------------------------------------------------------------
-
-export OFILES_BIN	:=	$(addsuffix .o,$(BINFILES))
-export OFILES_SRC	:=	$(CPPFILES:.cpp=.o) $(CFILES:.c=.o) $(SFILES:.s=.o)
-export OFILES 		:=	$(OFILES_BIN) $(OFILES_SRC)
-export HFILES_BIN	:=	$(addsuffix .h,$(subst .,_,$(BINFILES)))
-
-export INCLUDE	:=	$(foreach dir,$(INCLUDES),-I$(CURDIR)/$(dir)) \
-			$(foreach dir,$(LIBDIRS),-I$(dir)/include) \
-			-I$(CURDIR)/$(BUILD)
-
-export LIBPATHS	:=	$(foreach dir,$(LIBDIRS),-L$(dir)/lib)
-
-.PHONY: $(BUILD) clean all
-
-#---------------------------------------------------------------------------------
-all: $(BUILD)
-
-$(BUILD):
-	@[ -d $@ ] || mkdir -p $@
-	@$(MAKE) --no-print-directory -C $(BUILD) -f $(CURDIR)/Makefile
-
-#---------------------------------------------------------------------------------
-clean:
-	@echo clean ...
-	@rm -fr $(BUILD) $(TARGET).bin $(TARGET).elf
-
-#---------------------------------------------------------------------------------
-else
-.PHONY:	all
-
-DEPENDS	:=	$(OFILES:.o=.d)
-
-#---------------------------------------------------------------------------------
-# main targets
-#---------------------------------------------------------------------------------
-all	:	$(OUTPUT).bin
-
-$(OUTPUT).bin	:	$(OUTPUT).elf
-	$(OBJCOPY) -S -O binary $< $@
-	@echo built ... $(notdir $@)
-
-$(OUTPUT).elf	:	$(OFILES)
-
-%.elf: $(OFILES)
-	@echo linking $(notdir $@)
-	@$(LD) $(LDFLAGS) $(OFILES) $(LIBPATHS) $(LIBS) -o $@
-	@$(NM) -CSn $@ > $(notdir $*.lst)
-
-$(OFILES_SRC)	: $(HFILES_BIN)
-
-#---------------------------------------------------------------------------------
-# you need a rule like this for each extension you use as binary data
-#---------------------------------------------------------------------------------
-%.bin.o	%_bin.h:	%.bin
-#---------------------------------------------------------------------------------
-	@echo $(notdir $<)
-	@$(bin2o)
-
--include $(DEPENDS)
-
-#---------------------------------------------------------------------------------------
-endif
-#---------------------------------------------------------------------------------------

fusee/fusee-mtc/linker.ld

@@ -1,170 +0,0 @@
-OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-
-PHDRS
-{
-    crt0        PT_LOAD;
-    main        PT_LOAD;
-}
-
-/* Mostly copied from https://github.com/devkitPro/buildscripts/blob/master/dkarm-eabi/crtls/3dsx.ld */
-MEMORY
-{
-    NULL        : ORIGIN = 0x00000000, LENGTH = 0x1000
-    main        : ORIGIN = 0xF0000000, LENGTH = 0x10000000
-}
-
-SECTIONS
-{
-    PROVIDE(__start__           = 0xF0000000);
-    PROVIDE(__stack_bottom__    = 0x90010000);
-    PROVIDE(__stack_top__       = 0x90020000);
-    PROVIDE(__heap_start__      = 0x90020000);
-    PROVIDE(__heap_end__        = 0xA0020000);
-
-    . = __start__;
-    
-    .crt0 :
-    {
-        KEEP( *(.text.start) )
-        KEEP( *(.init) )
-        . = ALIGN(32);
-    } >main :crt0
-    
-    .text :
-    {
-        . = ALIGN(32);
-        /* .text */
-        *(.text)
-        *(.text.*)
-        *(.glue_7)
-        *(.glue_7t)
-        *(.stub)
-        *(.gnu.warning)
-        *(.gnu.linkonce.t*)
-
-        /* .fini */
-        KEEP( *(.fini) )
-        . = ALIGN(8);
-    } >main :main
-
-    .rodata :
-    {
-        *(.rodata)
-        *(.roda)
-        *(.rodata.*)
-        *all.rodata*(*)
-        *(.gnu.linkonce.r*)
-        SORT(CONSTRUCTORS)
-        . = ALIGN(8);
-    } >main
-    
-    .preinit_array :
-    {
-        PROVIDE (__preinit_array_start = .);
-        KEEP (*(.preinit_array))
-        PROVIDE (__preinit_array_end = .);
-    } >main
-
-    .init_array ALIGN(4) :
-    {
-        PROVIDE (__init_array_start = .);
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        PROVIDE (__init_array_end = .);
-    } >main
-
-    .fini_array ALIGN(4) :
-    {
-        PROVIDE (__fini_array_start = .);
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        PROVIDE (__fini_array_end = .);
-    } >main
-
-    .ctors ALIGN(4) :
-    {
-        KEEP (*crtbegin.o(.ctors)) /* MUST be first -- GCC requires it */
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*(.ctors))
-        . = ALIGN(4);   /* REQUIRED. LD is flaky without it. */
-    } >main
-
-    .dtors ALIGN(4) :
-    {
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*(.dtors))
-        . = ALIGN(4);   /* REQUIRED. LD is flaky without it. */
-    } >main
-
-    .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) __exidx_start = ABSOLUTE(.);} >main
-    ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*)  __exidx_end = ABSOLUTE(.);} >main
-
-    .data :
-    {
-        *(.data)
-        *(.data.*)
-        *(.gnu.linkonce.d*)
-        CONSTRUCTORS
-        . = ALIGN(32);
-    } >main
-
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(32);
-        PROVIDE (__bss_start__ = ABSOLUTE(.));
-        *(.dynbss)
-        *(.bss)
-        *(.bss.*)
-        *(.gnu.linkonce.b*)
-        *(COMMON)
-        . = ALIGN(32);
-        PROVIDE (__bss_end__ = ABSOLUTE(.));
-    } >main :NONE
-    __end__ = ABSOLUTE(.) ;
-
-
-    /* ==================
-       ==== Metadata ====
-       ================== */
-
-    /* Discard sections that difficult post-processing */
-    /DISCARD/ : { *(.group .comment .note) }
-
-    /* Stabs debugging sections. */
-    .stab          0 : { *(.stab) }
-    .stabstr       0 : { *(.stabstr) }
-    .stab.excl     0 : { *(.stab.excl) }
-    .stab.exclstr  0 : { *(.stab.exclstr) }
-    .stab.index    0 : { *(.stab.index) }
-    .stab.indexstr 0 : { *(.stab.indexstr) }
-
-    /* DWARF debug sections.
-       Symbols in the DWARF debugging sections are relative to the beginning
-       of the section so we begin them at 0. */
-
-    /* DWARF 1 */
-    .debug          0 : { *(.debug) }
-    .line           0 : { *(.line) }
-
-    /* GNU DWARF 1 extensions */
-    .debug_srcinfo  0 : { *(.debug_srcinfo) }
-    .debug_sfnames  0 : { *(.debug_sfnames) }
-
-    /* DWARF 1.1 and DWARF 2 */
-    .debug_aranges  0 : { *(.debug_aranges) }
-    .debug_pubnames 0 : { *(.debug_pubnames) }
-
-    /* DWARF 2 */
-    .debug_info     0 : { *(.debug_info) }
-    .debug_abbrev   0 : { *(.debug_abbrev) }
-    .debug_line     0 : { *(.debug_line) }
-    .debug_frame    0 : { *(.debug_frame) }
-    .debug_str      0 : { *(.debug_str) }
-    .debug_loc      0 : { *(.debug_loc) }
-    .debug_macinfo  0 : { *(.debug_macinfo) }
-}

fusee/fusee-mtc/linker.specs

@@ -1,7 +0,0 @@
-%rename link                old_link
-
-*link:
-%(old_link) -T %:getenv(TOPDIR /linker.ld) --nmagic --gc-sections
-
-*startfile:
-crti%O%s crtbegin%O%s

fusee/fusee-mtc/src/car.c

@@ -1,142 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include "car.h"
-#include "timers.h"
-#include "utils.h"
-
-static inline uint32_t get_clk_source_reg(CarDevice dev) {
-    switch (dev) {
-        case CARDEVICE_UARTA: return 0x178;
-        case CARDEVICE_UARTB: return 0x17C;
-        case CARDEVICE_UARTC: return 0x1A0;
-        case CARDEVICE_I2C1: return 0x124;
-        case CARDEVICE_I2C5: return 0x128;
-        case CARDEVICE_TZRAM: return 0;
-        case CARDEVICE_SE: return 0x42C;
-        case CARDEVICE_HOST1X: return 0x180;
-        case CARDEVICE_TSEC: return 0x1F4;
-        case CARDEVICE_SOR_SAFE: return 0;
-        case CARDEVICE_SOR0: return 0;
-        case CARDEVICE_SOR1: return 0x410;
-        case CARDEVICE_KFUSE: return 0;
-        case CARDEVICE_CL_DVFS: return 0;
-        case CARDEVICE_CORESIGHT: return 0x1D4;
-        case CARDEVICE_MSELECT: return 0x3B4;
-        case CARDEVICE_ACTMON: return 0x3E8;
-        case CARDEVICE_BPMP: return 0;
-        default: generic_panic();
-    }
-} 
-
-static inline uint32_t get_clk_source_val(CarDevice dev) {
-    switch (dev) {
-        case CARDEVICE_UARTA: return 0;
-        case CARDEVICE_UARTB: return 0;
-        case CARDEVICE_UARTC: return 0;
-        case CARDEVICE_I2C1: return 6;
-        case CARDEVICE_I2C5: return 6;
-        case CARDEVICE_TZRAM: return 0;
-        case CARDEVICE_SE: return 0;
-        case CARDEVICE_HOST1X: return 4;
-        case CARDEVICE_TSEC: return 0;
-        case CARDEVICE_SOR_SAFE: return 0;
-        case CARDEVICE_SOR0: return 0;
-        case CARDEVICE_SOR1: return 0;
-        case CARDEVICE_KFUSE: return 0;
-        case CARDEVICE_CL_DVFS: return 0;
-        case CARDEVICE_CORESIGHT: return 0;
-        case CARDEVICE_MSELECT: return 0;
-        case CARDEVICE_ACTMON: return 6;
-        case CARDEVICE_BPMP: return 0;
-        default: generic_panic();
-    }
-}
-
-static inline uint32_t get_clk_source_div(CarDevice dev) {
-    switch (dev) {
-        case CARDEVICE_UARTA: return 0;
-        case CARDEVICE_UARTB: return 0;
-        case CARDEVICE_UARTC: return 0;
-        case CARDEVICE_I2C1: return 0;
-        case CARDEVICE_I2C5: return 0;
-        case CARDEVICE_TZRAM: return 0;
-        case CARDEVICE_SE: return 0;
-        case CARDEVICE_HOST1X: return 3;
-        case CARDEVICE_TSEC: return 2;
-        case CARDEVICE_SOR_SAFE: return 0;
-        case CARDEVICE_SOR0: return 0;
-        case CARDEVICE_SOR1: return 2;
-        case CARDEVICE_KFUSE: return 0;
-        case CARDEVICE_CL_DVFS: return 0;
-        case CARDEVICE_CORESIGHT: return 4;
-        case CARDEVICE_MSELECT: return 6;
-        case CARDEVICE_ACTMON: return 0;
-        case CARDEVICE_BPMP: return 0;
-        default: generic_panic();
-    }
-}
-
-static uint32_t g_clk_reg_offsets[NUM_CAR_BANKS] = {0x010, 0x014, 0x018, 0x360, 0x364, 0x280, 0x298};
-static uint32_t g_rst_reg_offsets[NUM_CAR_BANKS] = {0x004, 0x008, 0x00C, 0x358, 0x35C, 0x28C, 0x2A4}; 
-
-void clk_enable(CarDevice dev) {
-    uint32_t clk_source_reg;
-    if ((clk_source_reg = get_clk_source_reg(dev))) {
-        MAKE_CAR_REG(clk_source_reg) = (get_clk_source_val(dev) << 29) | get_clk_source_div(dev);
-    }
-    MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5]) |= BIT(dev & 0x1F);
-}
-
-void clk_disable(CarDevice dev) {
-    MAKE_CAR_REG(g_clk_reg_offsets[dev >> 5]) &= ~(BIT(dev & 0x1F));
-}
-
-void rst_enable(CarDevice dev) {
-    MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5]) |= BIT(dev & 0x1F);
-}
-
-void rst_disable(CarDevice dev) {
-    MAKE_CAR_REG(g_rst_reg_offsets[dev >> 5]) &= ~(BIT(dev & 0x1F));
-}
-
-void clkrst_enable(CarDevice dev) {
-    clk_enable(dev);
-    rst_disable(dev);
-}
-
-void clkrst_disable(CarDevice dev) {
-    rst_enable(dev);
-    clk_disable(dev);
-}
-
-void clkrst_reboot(CarDevice dev) {
-    clkrst_disable(dev);
-    if (dev == CARDEVICE_KFUSE) {
-        /* Workaround for KFUSE clock. */
-        clk_enable(dev);
-        udelay(100);
-        rst_disable(dev);
-        udelay(200);
-    } else {
-        clkrst_enable(dev);
-    }
-}
-
-void clkrst_enable_fuse_regs(bool enable) {
-    volatile tegra_car_t *car = car_get_regs();
-    car->misc_clk_enb = ((car->misc_clk_enb & 0xEFFFFFFF) | ((enable & 1) << 28));
-}

fusee/fusee-mtc/src/car.h

@@ -1,510 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_CAR_H
-#define FUSEE_CAR_H
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#define CAR_BASE 0x60006000
-#define MAKE_CAR_REG(n) MAKE_REG32(CAR_BASE + n)
-
-#define CLK_L_SDMMC1    (1 << 14)
-#define CLK_L_SDMMC2    (1 << 9)
-#define CLK_U_SDMMC3    (1 << 5)
-#define CLK_L_SDMMC4    (1 << 15)
-
-#define CLK_SOURCE_MASK             (0b111 << 29)
-#define CLK_SOURCE_FIRST            (0b000 << 29)
-#define CLK_DIVIDER_MASK            (0xff << 0)
-#define CLK_DIVIDER_UNITY           (0x00 << 0)
-
-#define NUM_CAR_BANKS 7
-
-/* Clock and reset devices. */
-typedef enum {
-    CARDEVICE_BPMP      = ((0 << 5) | 0x1),
-    CARDEVICE_UARTA     = ((0 << 5) | 0x6),
-    CARDEVICE_UARTB     = ((0 << 5) | 0x7),
-    CARDEVICE_I2C1      = ((0 << 5) | 0xC),
-    CARDEVICE_USBD      = ((0 << 5) | 0x16),
-    CARDEVICE_HOST1X    = ((0 << 5) | 0x1C),
-    CARDEVICE_AHBDMA    = ((1 << 5) | 0x1),
-    CARDEVICE_APBDMA    = ((1 << 5) | 0x2),
-    CARDEVICE_KFUSE     = ((1 << 5) | 0x8),
-    CARDEVICE_I2C5      = ((1 << 5) | 0xF),
-    CARDEVICE_UARTC     = ((1 << 5) | 0x17),
-    CARDEVICE_USB2      = ((1 << 5) | 0x1A),
-    CARDEVICE_CORESIGHT = ((2 << 5) | 0x9),
-    CARDEVICE_TSEC      = ((2 << 5) | 0x13),
-    CARDEVICE_MSELECT   = ((3 << 5) | 0x8),
-    CARDEVICE_ACTMON    = ((3 << 5) | 0x17),
-    CARDEVICE_TZRAM     = ((3 << 5) | 0x1E),
-    CARDEVICE_SE        = ((3 << 5) | 0x1F),
-    CARDEVICE_CL_DVFS   = ((4 << 5) | 0x1B),
-    CARDEVICE_SOR0      = ((5 << 5) | 0x16),
-    CARDEVICE_SOR1      = ((5 << 5) | 0x17),
-    CARDEVICE_SOR_SAFE  = ((6 << 5) | 0x1E),
-} CarDevice;
-
-/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
-typedef struct {
-    uint32_t rst_src;           /* _RST_SOURCE_0,   0x00 */
-
-    /* _RST_DEVICES_L/H/U_0     0x4-0xc */
-    uint32_t rst_dev_l;
-    uint32_t rst_dev_h;
-    uint32_t rst_dev_u;
-
-    /* _CLK_OUT_ENB_L/H/U_0     0x10-0x18 */
-    uint32_t clk_out_enb_l;
-    uint32_t clk_out_enb_h;
-    uint32_t clk_out_enb_u;
-
-    uint32_t _0x1C;
-    uint32_t cclk_brst_pol;     /* _CCLK_BURST_POLICY_0,    0x20 */
-    uint32_t super_cclk_div;    /* _SUPER_CCLK_DIVIDER_0,   0x24 */
-    uint32_t sclk_brst_pol;     /* _SCLK_BURST_POLICY_0,    0x28 */
-    uint32_t super_sclk_div;    /* _SUPER_SCLK_DIVIDER_0,   0x2c */
-    uint32_t clk_sys_rate;      /* _CLK_SYSTEM_RATE_0,      0x30 */
-    uint32_t prog_dly_clk;      /* _PROG_DLY_CLK_0,         0x34 */
-    uint32_t aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,  0x38 */
-    uint32_t _0x3C;
-    uint32_t cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,  0x40 */
-    uint32_t clk_mask_arm;      /* _CLK_MASK_ARM_0,         0x44 */
-    uint32_t misc_clk_enb;      /* _MISC_CLK_ENB_0,         0x48 */
-    uint32_t clk_cpu_cmplx;     /* _CLK_CPU_CMPLX_0,        0x4c */
-    uint32_t osc_ctrl;          /* _OSC_CTRL_0,             0x50 */
-    uint32_t pll_lfsr;          /* _PLL_LFSR_0,             0x54 */
-    uint32_t osc_freq_det;      /* _OSC_FREQ_DET_0,         0x58 */
-    uint32_t osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,  0x5c */
-    uint32_t _0x60[2];
-    uint32_t plle_ss_cntl;      /* _PLLE_SS_CNTL_0,         0x68 */
-    uint32_t plle_misc1;        /* _PLLE_MISC1_0,           0x6c */
-    uint32_t _0x70[4];
-
-    /* PLLC 0x80-0x8c */
-    uint32_t pllc_base;
-    uint32_t pllc_out;
-    uint32_t pllc_misc0;
-    uint32_t pllc_misc1;
-
-    /* PLLM 0x90-0x9c */
-    uint32_t pllm_base;
-    uint32_t pllm_out;
-    uint32_t pllm_misc1;
-    uint32_t pllm_misc2;
-
-    /* PLLP 0xa0-0xac */
-    uint32_t pllp_base;
-    uint32_t pllp_outa;
-    uint32_t pllp_outb;
-    uint32_t pllp_misc;
-
-    /* PLLA 0xb0-0xbc */
-    uint32_t plla_base;
-    uint32_t plla_out;
-    uint32_t plla_misc0;
-    uint32_t plla_misc1;
-
-    /* PLLU 0xc0-0xcc */
-    uint32_t pllu_base;
-    uint32_t pllu_out;
-    uint32_t pllu_misc1;
-    uint32_t pllu_misc2;
-
-    /* PLLD 0xd0-0xdc */
-    uint32_t plld_base;
-    uint32_t plld_out;
-    uint32_t plld_misc1;
-    uint32_t plld_misc2;
-
-    /* PLLX 0xe0-0xe4 */
-    uint32_t pllx_base;
-    uint32_t pllx_misc;
-
-    /* PLLE 0xe8-0xf4 */
-    uint32_t plle_base;
-    uint32_t plle_misc;
-    uint32_t plle_ss_cntl1;
-    uint32_t plle_ss_cntl2;
-
-    uint32_t lvl2_clk_gate_ovra;            /* _LVL2_CLK_GATE_OVRA_0,   0xf8 */
-    uint32_t lvl2_clk_gate_ovrb;            /* _LVL2_CLK_GATE_OVRB_0,   0xfc */
-
-    uint32_t clk_source_i2s2;               /* _CLK_SOURCE_I2S2_0,      0x100 */
-    uint32_t clk_source_i2s3;               /* _CLK_SOURCE_I2S3_0,      0x104 */
-    uint32_t clk_source_spdif_out;          /* _CLK_SOURCE_SPDIF_OUT_0, 0x108 */
-    uint32_t clk_source_spdif_in;           /* _CLK_SOURCE_SPDIF_IN_0,  0x10c */
-    uint32_t clk_source_pwm;                /* _CLK_SOURCE_PWM_0,       0x110 */
-    uint32_t _0x114;
-    uint32_t clk_source_spi2;               /* _CLK_SOURCE_SPI2_0,      0x118 */
-    uint32_t clk_source_spi3;               /* _CLK_SOURCE_SPI3_0,      0x11c */
-    uint32_t _0x120;
-    uint32_t clk_source_i2c1;               /* _CLK_SOURCE_I2C1_0,      0x124 */
-    uint32_t clk_source_i2c5;               /* _CLK_SOURCE_I2C5_0,      0x128 */
-    uint32_t _0x12c[2];
-    uint32_t clk_source_spi1;               /* _CLK_SOURCE_SPI1_0,      0x134 */
-    uint32_t clk_source_disp1;              /* _CLK_SOURCE_DISP1_0,     0x138 */
-    uint32_t clk_source_disp2;              /* _CLK_SOURCE_DISP2_0,     0x13c */
-    uint32_t _0x140;
-    uint32_t clk_source_isp;                /* _CLK_SOURCE_ISP_0,       0x144 */
-    uint32_t clk_source_vi;                 /* _CLK_SOURCE_VI_0,        0x148 */
-    uint32_t _0x14c;
-    uint32_t clk_source_sdmmc1;             /* _CLK_SOURCE_SDMMC1_0,    0x150 */
-    uint32_t clk_source_sdmmc2;             /* _CLK_SOURCE_SDMMC2_0,    0x154 */
-    uint32_t _0x158[3];
-    uint32_t clk_source_sdmmc4;             /* _CLK_SOURCE_SDMMC4_0,    0x164 */
-    uint32_t _0x168[4];
-    uint32_t clk_source_uarta;              /* _CLK_SOURCE_UARTA_0,     0x178 */
-    uint32_t clk_source_uartb;              /* _CLK_SOURCE_UARTB_0,     0x17c */
-    uint32_t clk_source_host1x;             /* _CLK_SOURCE_HOST1X_0,    0x180 */
-    uint32_t _0x184[5];
-    uint32_t clk_source_i2c2;               /* _CLK_SOURCE_I2C2_0,      0x198 */
-    uint32_t clk_source_emc;                /* _CLK_SOURCE_EMC_0,       0x19c */
-    uint32_t clk_source_uartc;              /* _CLK_SOURCE_UARTC_0,     0x1a0 */
-    uint32_t _0x1a4;
-    uint32_t clk_source_vi_sensor;          /* _CLK_SOURCE_VI_SENSOR_0, 0x1a8 */
-    uint32_t _0x1ac[2];
-    uint32_t clk_source_spi4;               /* _CLK_SOURCE_SPI4_0,      0x1b4 */
-    uint32_t clk_source_i2c3;               /* _CLK_SOURCE_I2C3_0,      0x1b8 */
-    uint32_t clk_source_sdmmc3;             /* _CLK_SOURCE_SDMMC3_0,    0x1bc */
-    uint32_t clk_source_uartd;              /* _CLK_SOURCE_UARTD_0,     0x1c0 */
-    uint32_t _0x1c4[2];
-    uint32_t clk_source_owr;                /* _CLK_SOURCE_OWR_0,       0x1cc */
-    uint32_t _0x1d0;
-    uint32_t clk_source_csite;              /* _CLK_SOURCE_CSITE_0,     0x1d4 */
-    uint32_t clk_source_i2s1;               /* _CLK_SOURCE_I2S1_0,      0x1d8 */
-    uint32_t clk_source_dtv;                /* _CLK_SOURCE_DTV_0,       0x1dc */
-    uint32_t _0x1e0[5];
-    uint32_t clk_source_tsec;               /* _CLK_SOURCE_TSEC_0,      0x1f4 */
-    uint32_t _0x1f8;
-
-    uint32_t clk_spare2;                    /* _CLK_SPARE2_0,       0x1fc */
-    uint32_t _0x200[32];
-
-    uint32_t clk_out_enb_x;                 /* _CLK_OUT_ENB_X_0,    0x280 */
-    uint32_t clk_enb_x_set;                 /* _CLK_ENB_X_SET_0,    0x284 */
-    uint32_t clk_enb_x_clr;                 /* _CLK_ENB_X_CLR_0,    0x288 */
-
-    uint32_t rst_devices_x;                 /* _RST_DEVICES_X_0,    0x28c */
-    uint32_t rst_dev_x_set;                 /* _RST_DEV_X_SET_0,    0x290 */
-    uint32_t rst_dev_x_clr;                 /* _RST_DEV_X_CLR_0,    0x294 */
-
-    uint32_t clk_out_enb_y;                 /* _CLK_OUT_ENB_Y_0,    0x298 */
-    uint32_t clk_enb_y_set;                 /* _CLK_ENB_Y_SET_0,    0x29c */
-    uint32_t clk_enb_y_clr;                 /* _CLK_ENB_Y_CLR_0,    0x2a0 */
-
-    uint32_t rst_devices_y;                 /* _RST_DEVICES_Y_0,    0x2a4 */
-    uint32_t rst_dev_y_set;                 /* _RST_DEV_Y_SET_0,    0x2a8 */
-    uint32_t rst_dev_y_clr;                 /* _RST_DEV_Y_CLR_0,    0x2ac */
-
-    uint32_t _0x2b0[17];
-    uint32_t dfll_base;                     /* _DFLL_BASE_0,        0x2f4 */
-    uint32_t _0x2f8[2];
-
-    /* _RST_DEV_L/H/U_SET_0 0x300-0x314 */
-    uint32_t rst_dev_l_set;
-    uint32_t rst_dev_l_clr;
-    uint32_t rst_dev_h_set;
-    uint32_t rst_dev_h_clr;
-    uint32_t rst_dev_u_set;
-    uint32_t rst_dev_u_clr;
-
-    uint32_t _0x318[2];
-
-    /* _CLK_ENB_L/H/U_CLR_0 0x320-0x334 */
-    uint32_t clk_enb_l_set;
-    uint32_t clk_enb_l_clr;
-    uint32_t clk_enb_h_set;
-    uint32_t clk_enb_h_clr;
-    uint32_t clk_enb_u_set;
-    uint32_t clk_enb_u_clr;
-
-    uint32_t _0x338;
-    uint32_t ccplex_pg_sm_ovrd;         /* _CCPLEX_PG_SM_OVRD_0,    0x33c */
-    uint32_t rst_cpu_cmplx_set;         /* _RST_CPU_CMPLX_SET_0,    0x340 */
-    uint32_t rst_cpu_cmplx_clr;         /* _RST_CPU_CMPLX_CLR_0,    0x344 */
-
-    /* Additional (T30) registers */
-    uint32_t clk_cpu_cmplx_set;         /* _CLK_CPU_CMPLX_SET_0,    0x348 */
-    uint32_t clk_cpu_cmplx_clr;         /* _CLK_CPU_CMPLX_SET_0,    0x34c */
-
-    uint32_t _0x350[2];
-    uint32_t rst_dev_v;                 /* _RST_DEVICES_V_0,        0x358 */
-    uint32_t rst_dev_w;                 /* _RST_DEVICES_W_0,        0x35c */
-    uint32_t clk_out_enb_v;             /* _CLK_OUT_ENB_V_0,        0x360 */
-    uint32_t clk_out_enb_w;             /* _CLK_OUT_ENB_W_0,        0x364 */
-    uint32_t cclkg_brst_pol;            /* _CCLKG_BURST_POLICY_0,   0x368 */
-    uint32_t super_cclkg_div;           /* _SUPER_CCLKG_DIVIDER_0,  0x36c */
-    uint32_t cclklp_brst_pol;           /* _CCLKLP_BURST_POLICY_0,  0x370 */
-    uint32_t super_cclkp_div;           /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */
-    uint32_t clk_cpug_cmplx;            /* _CLK_CPUG_CMPLX_0,       0x378 */
-    uint32_t clk_cpulp_cmplx;           /* _CLK_CPULP_CMPLX_0,      0x37c */
-    uint32_t cpu_softrst_ctrl;          /* _CPU_SOFTRST_CTRL_0,     0x380 */
-    uint32_t cpu_softrst_ctrl1;         /* _CPU_SOFTRST_CTRL1_0,    0x384 */
-    uint32_t cpu_softrst_ctrl2;         /* _CPU_SOFTRST_CTRL2_0,    0x388 */
-    uint32_t _0x38c[5];
-    uint32_t lvl2_clk_gate_ovrc;        /* _LVL2_CLK_GATE_OVRC,     0x3a0 */
-    uint32_t lvl2_clk_gate_ovrd;        /* _LVL2_CLK_GATE_OVRD,     0x3a4 */
-    uint32_t _0x3a8[2];
-
-    uint32_t _0x3b0;
-    uint32_t clk_source_mselect;        /* _CLK_SOURCE_MSELECT_0,       0x3b4 */
-    uint32_t clk_source_tsensor;        /* _CLK_SOURCE_TSENSOR_0,       0x3b8 */
-    uint32_t clk_source_i2s4;           /* _CLK_SOURCE_I2S4_0,          0x3bc */
-    uint32_t clk_source_i2s5;           /* _CLK_SOURCE_I2S5_0,          0x3c0 */
-    uint32_t clk_source_i2c4;           /* _CLK_SOURCE_I2C4_0,          0x3c4 */
-    uint32_t _0x3c8[2];
-    uint32_t clk_source_ahub;           /* _CLK_SOURCE_AHUB_0,          0x3d0 */
-    uint32_t _0x3d4[4];
-    uint32_t clk_source_hda2codec_2x;   /* _CLK_SOURCE_HDA2CODEC_2X_0,  0x3e4 */
-    uint32_t clk_source_actmon;         /* _CLK_SOURCE_ACTMON_0,        0x3e8 */
-    uint32_t clk_source_extperiph1;     /* _CLK_SOURCE_EXTPERIPH1_0,    0x3ec */
-    uint32_t clk_source_extperiph2;     /* _CLK_SOURCE_EXTPERIPH2_0,    0x3f0 */
-    uint32_t clk_source_extperiph3;     /* _CLK_SOURCE_EXTPERIPH3_0,    0x3f4 */
-    uint32_t _0x3f8;
-    uint32_t clk_source_i2c_slow;       /* _CLK_SOURCE_I2C_SLOW_0,      0x3fc */
-    uint32_t clk_source_sys;            /* _CLK_SOURCE_SYS_0,           0x400 */
-    uint32_t clk_source_ispb;           /* _CLK_SOURCE_ISPB_0,          0x404 */
-    uint32_t _0x408[2];
-    uint32_t clk_source_sor1;           /* _CLK_SOURCE_SOR1_0,          0x410 */
-    uint32_t clk_source_sor0;           /* _CLK_SOURCE_SOR0_0,          0x414 */
-    uint32_t _0x418[2];
-    uint32_t clk_source_sata_oob;       /* _CLK_SOURCE_SATA_OOB_0,      0x420 */
-    uint32_t clk_source_sata;           /* _CLK_SOURCE_SATA_0,          0x424 */
-    uint32_t clk_source_hda;            /* _CLK_SOURCE_HDA_0,           0x428 */
-    uint32_t clk_source_se;             /* _CLK_SOURCE_SE_0,            0x42c */
-
-    /* _RST_DEV_V/W_SET_0 0x430-0x43c */
-    uint32_t rst_dev_v_set;
-    uint32_t rst_dev_v_clr;
-    uint32_t rst_dev_w_set;
-    uint32_t rst_dev_w_clr;
-
-    /* _CLK_ENB_V/W_CLR_0 0x440-0x44c */
-    uint32_t clk_enb_v_set;
-    uint32_t clk_enb_v_clr;
-    uint32_t clk_enb_w_set;
-    uint32_t clk_enb_w_clr;
-
-    /* Additional (T114+) registers */
-    uint32_t rst_cpug_cmplx_set;    /* _RST_CPUG_CMPLX_SET_0,   0x450 */
-    uint32_t rst_cpug_cmplx_clr;    /* _RST_CPUG_CMPLX_CLR_0,   0x454 */
-    uint32_t rst_cpulp_cmplx_set;   /* _RST_CPULP_CMPLX_SET_0,  0x458 */
-    uint32_t rst_cpulp_cmplx_clr;   /* _RST_CPULP_CMPLX_CLR_0,  0x45c */
-    uint32_t clk_cpug_cmplx_set;    /* _CLK_CPUG_CMPLX_SET_0,   0x460 */
-    uint32_t clk_cpug_cmplx_clr;    /* _CLK_CPUG_CMPLX_CLR_0,   0x464 */
-    uint32_t clk_cpulp_cmplx_set;   /* _CLK_CPULP_CMPLX_SET_0,  0x468 */
-    uint32_t clk_cpulp_cmplx_clr;   /* _CLK_CPULP_CMPLX_CLR_0,  0x46c */
-    uint32_t cpu_cmplx_status;      /* _CPU_CMPLX_STATUS_0,     0x470 */
-    uint32_t _0x474;
-    uint32_t intstatus;             /* _INTSTATUS_0,            0x478 */
-    uint32_t intmask;               /* _INTMASK_0,              0x47c */
-    uint32_t utmip_pll_cfg0;        /* _UTMIP_PLL_CFG0_0,       0x480 */
-    uint32_t utmip_pll_cfg1;        /* _UTMIP_PLL_CFG1_0,       0x484 */
-    uint32_t utmip_pll_cfg2;        /* _UTMIP_PLL_CFG2_0,       0x488 */
-
-    uint32_t plle_aux;              /* _PLLE_AUX_0,             0x48c */
-    uint32_t sata_pll_cfg0;         /* _SATA_PLL_CFG0_0,        0x490 */
-    uint32_t sata_pll_cfg1;         /* _SATA_PLL_CFG1_0,        0x494 */
-    uint32_t pcie_pll_cfg0;         /* _PCIE_PLL_CFG0_0,        0x498 */
-
-    uint32_t prog_audio_dly_clk;    /* _PROG_AUDIO_DLY_CLK_0,   0x49c */
-    uint32_t audio_sync_clk_i2s0;   /* _AUDIO_SYNC_CLK_I2S0_0,  0x4a0 */
-    uint32_t audio_sync_clk_i2s1;   /* _AUDIO_SYNC_CLK_I2S1_0,  0x4a4 */
-    uint32_t audio_sync_clk_i2s2;   /* _AUDIO_SYNC_CLK_I2S2_0,  0x4a8 */
-    uint32_t audio_sync_clk_i2s3;   /* _AUDIO_SYNC_CLK_I2S3_0,  0x4ac */
-    uint32_t audio_sync_clk_i2s4;   /* _AUDIO_SYNC_CLK_I2S4_0,  0x4b0 */
-    uint32_t audio_sync_clk_spdif;  /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4b4 */
-
-    uint32_t plld2_base;            /* _PLLD2_BASE_0, 0x4b8 */
-    uint32_t plld2_misc;            /* _PLLD2_MISC_0, 0x4bc */
-    uint32_t utmip_pll_cfg3;        /* _UTMIP_PLL_CFG3_0, 0x4c0 */
-    uint32_t pllrefe_base;          /* _PLLREFE_BASE_0, 0x4c4 */
-    uint32_t pllrefe_misc;          /* _PLLREFE_MISC_0, 0x4c8 */
-    uint32_t pllrefe_out;           /* _PLLREFE_OUT_0, 0x4cc */
-    uint32_t cpu_finetrim_byp;      /* _CPU_FINETRIM_BYP_0, 0x4d0 */
-    uint32_t cpu_finetrim_select;   /* _CPU_FINETRIM_SELECT_0, 0x4d4 */
-    uint32_t cpu_finetrim_dr;       /* _CPU_FINETRIM_DR_0, 0x4d8 */
-    uint32_t cpu_finetrim_df;       /* _CPU_FINETRIM_DF_0, 0x4dc */
-    uint32_t cpu_finetrim_f;        /* _CPU_FINETRIM_F_0, 0x4e0 */
-    uint32_t cpu_finetrim_r;        /* _CPU_FINETRIM_R_0, 0x4e4 */
-    uint32_t pllc2_base;            /* _PLLC2_BASE_0, 0x4e8 */
-    uint32_t pllc2_misc0;           /* _PLLC2_MISC_0_0, 0x4ec */
-    uint32_t pllc2_misc1;           /* _PLLC2_MISC_1_0, 0x4f0 */
-    uint32_t pllc2_misc2;           /* _PLLC2_MISC_2_0, 0x4f4 */
-    uint32_t pllc2_misc3;           /* _PLLC2_MISC_3_0, 0x4f8 */
-    uint32_t pllc3_base;            /* _PLLC3_BASE_0, 0x4fc */
-    uint32_t pllc3_misc0;           /* _PLLC3_MISC_0_0, 0x500 */
-    uint32_t pllc3_misc1;           /* _PLLC3_MISC_1_0, 0x504 */
-    uint32_t pllc3_misc2;           /* _PLLC3_MISC_2_0, 0x508 */
-    uint32_t pllc3_misc3;           /* _PLLC3_MISC_3_0, 0x50c */
-    uint32_t pllx_misc1;            /* _PLLX_MISC_1_0, 0x510 */
-    uint32_t pllx_misc2;            /* _PLLX_MISC_2_0, 0x514 */
-    uint32_t pllx_misc3;            /* _PLLX_MISC_3_0, 0x518 */
-    uint32_t xusbio_pll_cfg0;       /* _XUSBIO_PLL_CFG0_0, 0x51c */
-    uint32_t xusbio_pll_cfg1;       /* _XUSBIO_PLL_CFG0_1, 0x520 */
-    uint32_t plle_aux1;             /* _PLLE_AUX1_0, 0x524 */
-    uint32_t pllp_reshift;          /* _PLLP_RESHIFT_0, 0x528 */
-    uint32_t utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52c */
-    uint32_t pllu_hw_pwrdn_cfg0;    /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */
-    uint32_t xusb_pll_cfg0;         /* _XUSB_PLL_CFG0_0, 0x534 */
-    uint32_t _0x538;
-    uint32_t clk_cpu_misc;          /* _CLK_CPU_MISC_0, 0x53c */
-    uint32_t clk_cpug_misc;         /* _CLK_CPUG_MISC_0, 0x540 */
-    uint32_t clk_cpulp_misc;        /* _CLK_CPULP_MISC_0, 0x544 */
-    uint32_t pllx_hw_ctrl_cfg;      /* _PLLX_HW_CTRL_CFG_0, 0x548 */
-    uint32_t pllx_sw_ramp_cfg;      /* _PLLX_SW_RAMP_CFG_0, 0x54c */
-    uint32_t pllx_hw_ctrl_status;   /* _PLLX_HW_CTRL_STATUS_0, 0x550 */
-    uint32_t lvl2_clk_gate_ovre;    /* _LVL2_CLK_GATE_OVRE, 0x554 */
-    uint32_t super_gr3d_clk_div;    /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */
-    uint32_t spare_reg0;            /* _SPARE_REG0_0, 0x55c */
-    uint32_t audio_sync_clk_dmic1;  /* _AUDIO_SYNC_CLK_DMIC1_0, 0x560 */
-    uint32_t audio_sync_clk_dmic2;  /* _AUDIO_SYNC_CLK_DMIC2_0, 0x564 */
-
-    uint32_t _0x568[2];
-    uint32_t plld2_ss_cfg;          /* _PLLD2_SS_CFG,           0x570 */
-    uint32_t plld2_ss_ctrl1;        /* _PLLD2_SS_CTRL1_0,       0x574 */
-    uint32_t plld2_ss_ctrl2;        /* _PLLD2_SS_CTRL2_0,       0x578 */
-    uint32_t _0x57c[5];
-
-    uint32_t plldp_base;            /* _PLLDP_BASE, 0x590*/
-    uint32_t plldp_misc;            /* _PLLDP_MISC, 0x594 */
-    uint32_t plldp_ss_cfg;          /* _PLLDP_SS_CFG, 0x598 */
-    uint32_t plldp_ss_ctrl1;        /* _PLLDP_SS_CTRL1_0, 0x59c */
-    uint32_t plldp_ss_ctrl2;        /* _PLLDP_SS_CTRL2_0, 0x5a0 */
-    uint32_t pllc4_base;            /* _PLLC4_BASE_0, 0x5a4 */
-    uint32_t pllc4_misc;            /* _PLLC4_MISC_0, 0x5a8 */
-    uint32_t _0x5ac[6];
-    uint32_t clk_spare0;            /* _CLK_SPARE0_0, 0x5c4 */
-    uint32_t clk_spare1;            /* _CLK_SPARE1_0, 0x5c8 */
-    uint32_t gpu_isob_ctrl;         /* _GPU_ISOB_CTRL_0, 0x5cc */
-    uint32_t pllc_misc2;            /* _PLLC_MISC_2_0, 0x5d0 */
-    uint32_t pllc_misc3;            /* _PLLC_MISC_3_0, 0x5d4 */
-    uint32_t plla_misc2;            /* _PLLA_MISC2_0, 0x5d8 */
-    uint32_t _0x5dc[2];
-    uint32_t pllc4_out;             /* _PLLC4_OUT_0, 0x5e4 */
-    uint32_t pllmb_base;            /* _PLLMB_BASE_0, 0x5e8 */
-    uint32_t pllmb_misc1;           /* _PLLMB_MISC1_0, 0x5ec */
-    uint32_t pllx_misc4;            /* _PLLX_MISC_4_0, 0x5f0 */
-    uint32_t pllx_misc5;            /* _PLLX_MISC_5_0, 0x5f4 */
-    uint32_t _0x5f8[2];
-
-    uint32_t clk_source_xusb_core_host;             /* _CLK_SOURCE_XUSB_CORE_HOST_0,    0x600 */
-    uint32_t clk_source_xusb_falcon;                /* _CLK_SOURCE_XUSB_FALCON_0,    0x604 */
-    uint32_t clk_source_xusb_fs;                    /* _CLK_SOURCE_XUSB_FS_0,    0x608 */
-    uint32_t clk_source_xusb_core_dev;              /* _CLK_SOURCE_XUSB_CORE_DEV_0,    0x60c */
-    uint32_t clk_source_xusb_ss;                    /* _CLK_SOURCE_XUSB_SS_0,    0x610 */
-    uint32_t clk_source_cilab;                      /* _CLK_SOURCE_CILAB_0,    0x614 */
-    uint32_t clk_source_cilcd;                      /* _CLK_SOURCE_CILCD_0,    0x618 */
-    uint32_t clk_source_cilef;                      /* _CLK_SOURCE_CILEF_0,    0x61c */
-    uint32_t clk_source_dsia_lp;                    /* _CLK_SOURCE_DSIA_LP_0,    0x620 */
-    uint32_t clk_source_dsib_lp;                    /* _CLK_SOURCE_DSIB_LP_0,    0x624 */
-    uint32_t clk_source_entropy;                    /* _CLK_SOURCE_ENTROPY_0,    0x628 */
-    uint32_t clk_source_dvfs_ref;                   /* _CLK_SOURCE_DVFS_REF_0,    0x62c */
-    uint32_t clk_source_dvfs_soc;                   /* _CLK_SOURCE_DVFS_SOC_0,    0x630 */
-    uint32_t _0x634[3];
-    uint32_t clk_source_emc_latency;                /* _CLK_SOURCE_EMC_LATENCY_0,    0x640 */
-    uint32_t clk_source_soc_therm;                  /* _CLK_SOURCE_SOC_THERM_0,    0x644 */
-    uint32_t _0x648;
-    uint32_t clk_source_dmic1;                      /* _CLK_SOURCE_DMIC1_0,    0x64c */
-    uint32_t clk_source_dmic2;                      /* _CLK_SOURCE_DMIC2_0,    0x650 */
-    uint32_t _0x654;
-    uint32_t clk_source_vi_sensor2;                 /* _CLK_SOURCE_VI_SENSOR2_0,    0x658 */
-    uint32_t clk_source_i2c6;                       /* _CLK_SOURCE_I2C6_0,    0x65c */
-    uint32_t clk_source_mipibif;                    /* _CLK_SOURCE_MIPIBIF_0,    0x660 */
-    uint32_t clk_source_emc_dll;                    /* _CLK_SOURCE_EMC_DLL_0,    0x664 */
-    uint32_t _0x668;
-    uint32_t clk_source_uart_fst_mipi_cal;          /* _CLK_SOURCE_UART_FST_MIPI_CAL_0,    0x66c */
-    uint32_t _0x670[2];
-    uint32_t clk_source_vic;                        /* _CLK_SOURCE_VIC_0,    0x678 */
-
-    uint32_t pllp_outc;                             /* _PLLP_OUTC_0, 0x67c */
-    uint32_t pllp_misc1;                            /* _PLLP_MISC1_0, 0x680 */
-    uint32_t _0x684[2];
-    uint32_t emc_div_clk_shaper_ctrl;               /* _EMC_DIV_CLK_SHAPER_CTRL_0, 0x68c */
-    uint32_t emc_pllc_shaper_ctrl;                  /* _EMC_PLLC_SHAPER_CTRL_0, 0x690 */
-
-    uint32_t clk_source_sdmmc_legacy_tm;            /* _CLK_SOURCE_SDMMC_LEGACY_TM_0,    0x694 */
-    uint32_t clk_source_nvdec;                      /* _CLK_SOURCE_NVDEC_0,    0x698 */
-    uint32_t clk_source_nvjpg;                      /* _CLK_SOURCE_NVJPG_0,    0x69c */
-    uint32_t clk_source_nvenc;                      /* _CLK_SOURCE_NVENC_0,    0x6a0 */
-
-    uint32_t plla1_base;                            /* _PLLA1_BASE_0, 0x6a4 */
-    uint32_t plla1_misc0;                           /* _PLLA1_MISC_0_0, 0x6a8 */
-    uint32_t plla1_misc1;                           /* _PLLA1_MISC_1_0, 0x6ac */
-    uint32_t plla1_misc2;                           /* _PLLA1_MISC_2_0, 0x6b0 */
-    uint32_t plla1_misc3;                           /* _PLLA1_MISC_3_0, 0x6b4 */
-    uint32_t audio_sync_clk_dmic3;                  /* _AUDIO_SYNC_CLK_DMIC3_0, 0x6b8 */
-
-    uint32_t clk_source_dmic3;                      /* _CLK_SOURCE_DMIC3_0,    0x6bc */
-    uint32_t clk_source_ape;                        /* _CLK_SOURCE_APE_0,    0x6c0 */
-    uint32_t clk_source_qspi;                       /* _CLK_SOURCE_QSPI_0,    0x6c4 */
-    uint32_t clk_source_vi_i2c;                     /* _CLK_SOURCE_VI_I2C_0,    0x6c8 */
-    uint32_t clk_source_usb2_hsic_trk;              /* _CLK_SOURCE_USB2_HSIC_TRK_0,    0x6cc */
-    uint32_t clk_source_pex_sata_usb_rx_byp;        /* _CLK_SOURCE_PEX_SATA_USB_RX_BYP_0,    0x6d0 */
-    uint32_t clk_source_maud;                       /* _CLK_SOURCE_MAUD_0,    0x6d4 */
-    uint32_t clk_source_tsecb;                      /* _CLK_SOURCE_TSECB_0,    0x6d8 */
-
-    uint32_t clk_cpug_misc1;                        /* _CLK_CPUG_MISC1_0, 0x6dc */
-    uint32_t aclk_burst_policy;                     /* _ACLK_BURST_POLICY_0, 0x6e0 */
-    uint32_t super_aclk_divider;                    /* _SUPER_ACLK_DIVIDER_0, 0x6e4 */
-
-    uint32_t nvenc_super_clk_divider;               /* _NVENC_SUPER_CLK_DIVIDER_0, 0x6e8 */
-    uint32_t vi_super_clk_divider;                  /* _VI_SUPER_CLK_DIVIDER_0, 0x6ec */
-    uint32_t vic_super_clk_divider;                 /* _VIC_SUPER_CLK_DIVIDER_0, 0x6f0 */
-    uint32_t nvdec_super_clk_divider;               /* _NVDEC_SUPER_CLK_DIVIDER_0, 0x6f4 */
-    uint32_t isp_super_clk_divider;                 /* _ISP_SUPER_CLK_DIVIDER_0, 0x6f8 */
-    uint32_t ispb_super_clk_divider;                /* _ISPB_SUPER_CLK_DIVIDER_0, 0x6fc */
-    uint32_t nvjpg_super_clk_divider;               /* _NVJPG_SUPER_CLK_DIVIDER_0, 0x700 */
-    uint32_t se_super_clk_divider;                  /* _SE_SUPER_CLK_DIVIDER_0, 0x704 */
-    uint32_t tsec_super_clk_divider;                /* _TSEC_SUPER_CLK_DIVIDER_0, 0x708 */
-    uint32_t tsecb_super_clk_divider;               /* _TSECB_SUPER_CLK_DIVIDER_0, 0x70c */
-
-    uint32_t clk_source_uartape;                    /* _CLK_SOURCE_UARTAPE_0, 0x710 */
-    uint32_t clk_cpug_misc2;                        /* _CLK_CPUG_MISC2_0, 0x714 */
-    uint32_t clk_source_dbgapb;                     /* _CLK_SOURCE_DBGAPB_0, 0x718 */
-    uint32_t clk_ccplex_cc4_ret_clk_enb;            /* _CLK_CCPLEX_CC4_RET_CLK_ENB_0, 0x71c */
-    uint32_t actmon_cpu_clk;                        /* _ACTMON_CPU_CLK_0, 0x720 */
-    uint32_t clk_source_emc_safe;                   /* _CLK_SOURCE_EMC_SAFE_0, 0x724 */
-    uint32_t sdmmc2_pllc4_out0_shaper_ctrl;         /* _SDMMC2_PLLC4_OUT0_SHAPER_CTRL_0, 0x728 */
-    uint32_t sdmmc2_pllc4_out1_shaper_ctrl;         /* _SDMMC2_PLLC4_OUT1_SHAPER_CTRL_0, 0x72c */
-    uint32_t sdmmc2_pllc4_out2_shaper_ctrl;         /* _SDMMC2_PLLC4_OUT2_SHAPER_CTRL_0, 0x730 */
-    uint32_t sdmmc2_div_clk_shaper_ctrl;            /* _SDMMC2_DIV_CLK_SHAPER_CTRL_0, 0x734 */
-    uint32_t sdmmc4_pllc4_out0_shaper_ctrl;         /* _SDMMC4_PLLC4_OUT0_SHAPER_CTRL_0, 0x738 */
-    uint32_t sdmmc4_pllc4_out1_shaper_ctrl;         /* _SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0, 0x73c */
-    uint32_t sdmmc4_pllc4_out2_shaper_ctrl;         /* _SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0, 0x740 */
-    uint32_t sdmmc4_div_clk_shaper_ctrl;            /* _SDMMC4_DIV_CLK_SHAPER_CTRL_0, 0x744 */    
-} tegra_car_t;
-
-static inline volatile tegra_car_t *car_get_regs(void) {
-    return (volatile tegra_car_t *)CAR_BASE;
-}
-
-void clk_enable(CarDevice dev);
-void clk_disable(CarDevice dev);
-void rst_enable(CarDevice dev);
-void rst_disable(CarDevice dev);
-
-void clkrst_enable(CarDevice dev);
-void clkrst_disable(CarDevice dev);
-void clkrst_reboot(CarDevice dev);
-
-void clkrst_enable_fuse_regs(bool enable);
-
-#endif

fusee/fusee-mtc/src/fuse.c

@@ -1,346 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <stdbool.h>
-#include <stdint.h>
-#include <string.h>
-#include <vapours/ams_version.h>
-
-#include "car.h"
-#include "fuse.h"
-#include "pmc.h"
-#include "timers.h"
-
-/* Initialize the fuse driver */
-void fuse_init(void) {
-    /* Make all fuse registers visible, disable the private key and disable programming. */
-    clkrst_enable_fuse_regs(true);
-    fuse_disable_private_key();
-    fuse_disable_programming();
-}
-
-/* Disable access to the private key and set the TZ sticky bit. */
-void fuse_disable_private_key(void) {
-    volatile tegra_fuse_t *fuse = fuse_get_regs();
-    fuse->FUSE_PRIVATEKEYDISABLE = 0x10;
-}
-
-/* Disable all fuse programming. */
-void fuse_disable_programming(void) {
-    volatile tegra_fuse_t *fuse = fuse_get_regs();
-    fuse->FUSE_DISABLEREGPROGRAM = 1;
-}
-
-/* Enable power to the fuse hardware array. */
-void fuse_enable_power(void) {
-    volatile tegra_pmc_t *pmc = pmc_get_regs();
-    pmc->fuse_control &= ~(0x200);      /* Clear PMC_FUSE_CTRL_PS18_LATCH_CLEAR. */
-    mdelay(1);
-    pmc->fuse_control |= 0x100;         /* Set PMC_FUSE_CTRL_PS18_LATCH_SET. */
-    mdelay(1);
-}
-
-/* Disable power to the fuse hardware array. */
-void fuse_disable_power(void) {
-    volatile tegra_pmc_t *pmc = pmc_get_regs();
-    pmc->fuse_control &= ~(0x100);      /* Clear PMC_FUSE_CTRL_PS18_LATCH_SET. */
-    mdelay(1);
-    pmc->fuse_control |= 0x200;         /* Set PMC_FUSE_CTRL_PS18_LATCH_CLEAR. */
-    mdelay(1);
-}
-
-/* Wait for the fuse driver to go idle. */
-static void fuse_wait_idle(void) {
-    volatile tegra_fuse_t *fuse = fuse_get_regs();
-    uint32_t ctrl_val = 0;
-
-    /* Wait for STATE_IDLE */
-    while ((ctrl_val & (0xF0000)) != 0x40000) {
-        ctrl_val = fuse->FUSE_FUSECTRL;
-    }
-}
-
-/* Read a fuse from the hardware array. */
-uint32_t fuse_hw_read(uint32_t addr) {
-    volatile tegra_fuse_t *fuse = fuse_get_regs();
-
-    /* Wait for idle state. */
-    fuse_wait_idle();
-
-    /* Program the target address. */
-    fuse->FUSE_FUSEADDR = addr;
-
-    /* Enable read operation in control register. */
-    uint32_t ctrl_val = fuse->FUSE_FUSECTRL;
-    ctrl_val &= ~0x3;
-    ctrl_val |= 0x1;    /* Set READ command. */
-    fuse->FUSE_FUSECTRL = ctrl_val;
-
-    /* Wait for idle state. */
-    fuse_wait_idle();
-
-    return fuse->FUSE_FUSERDATA;
-}
-
-/* Write a fuse in the hardware array. */
-void fuse_hw_write(uint32_t value, uint32_t addr) {
-    volatile tegra_fuse_t *fuse = fuse_get_regs();
-
-    /* Wait for idle state. */
-    fuse_wait_idle();
-
-    /* Program the target address and value. */
-    fuse->FUSE_FUSEADDR = addr;
-    fuse->FUSE_FUSEWDATA = value;
-
-    /* Enable write operation in control register. */
-    uint32_t ctrl_val = fuse->FUSE_FUSECTRL;
-    ctrl_val &= ~0x3;
-    ctrl_val |= 0x2;    /* Set WRITE command. */
-    fuse->FUSE_FUSECTRL = ctrl_val;
-
-    /* Wait for idle state. */
-    fuse_wait_idle();
-}
-
-/* Sense the fuse hardware array into the fuse cache. */
-void fuse_hw_sense(void) {
-    volatile tegra_fuse_t *fuse = fuse_get_regs();
-
-    /* Wait for idle state. */
-    fuse_wait_idle();
-
-    /* Enable sense operation in control register */
-    uint32_t ctrl_val = fuse->FUSE_FUSECTRL;
-    ctrl_val &= ~0x3;
-    ctrl_val |= 0x3;    /* Set SENSE_CTRL command */
-    fuse->FUSE_FUSECTRL = ctrl_val;
-
-    /* Wait for idle state. */
-    fuse_wait_idle();
-}
-
-/* Read the SKU info register. */
-uint32_t fuse_get_sku_info(void) {
-    volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
-    return fuse_chip->FUSE_SKU_INFO;
-}
-
-/* Read the bootrom patch version. */
-uint32_t fuse_get_bootrom_patch_version(void) {
-    volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
-    return fuse_chip->FUSE_SOC_SPEEDO_1_CALIB;
-}
-
-/* Read a spare bit register. */
-uint32_t fuse_get_spare_bit(uint32_t index) {
-    uint32_t soc_type = fuse_get_soc_type();
-    if (soc_type == 0) {
-        if (index < 32) {
-            volatile tegra_fuse_chip_erista_t *fuse_chip = fuse_chip_erista_get_regs();
-            return fuse_chip->FUSE_SPARE_BIT[index];
-        }
-    } else if (soc_type == 1) {
-        if (index < 30) {
-            volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs();
-            return fuse_chip->FUSE_SPARE_BIT[index];
-        }
-    }
-    return 0;
-}
-
-/* Read a reserved ODM register. */
-uint32_t fuse_get_reserved_odm(uint32_t index) {
-    if (index < 8) {
-        volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
-        return fuse_chip->FUSE_RESERVED_ODM0[index];
-    } else {
-        uint32_t soc_type = fuse_get_soc_type();
-        if (soc_type == 1) {
-            volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs();
-            if (index < 22) {
-                return fuse_chip->FUSE_RESERVED_ODM8[index - 8];
-            } else if (index < 25) {
-                return fuse_chip->FUSE_RESERVED_ODM22[index - 22];
-            } else if (index < 26) {
-                return fuse_chip->FUSE_RESERVED_ODM25;
-            } else if (index < 29) {
-                return fuse_chip->FUSE_RESERVED_ODM26[index - 26];
-            } else if (index < 30) {
-                return fuse_chip->FUSE_RESERVED_ODM29;
-            }
-        }
-    }
-    return 0;
-}
-
-/* Get the DramId. */
-uint32_t fuse_get_dram_id(void) {
-    return ((fuse_get_reserved_odm(4) >> 3) & 0x1F);
-}
-
-/* Derive the DeviceId. */
-uint64_t fuse_get_device_id(void) {
-    volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
-
-    uint64_t device_id = 0;
-    uint64_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF;
-    uint64_t x_coord = fuse_chip->FUSE_OPT_X_COORDINATE & 0x1FF;
-    uint64_t wafer_id = fuse_chip->FUSE_OPT_WAFER_ID & 0x3F;
-    uint32_t lot_code = fuse_chip->FUSE_OPT_LOT_CODE_0;
-    uint64_t fab_code = fuse_chip->FUSE_OPT_FAB_CODE & 0x3F;
-
-    uint64_t derived_lot_code = 0;
-    for (unsigned int i = 0; i < 5; i++) {
-        derived_lot_code = (derived_lot_code * 0x24) + ((lot_code >> (24 - 6*i)) & 0x3F);
-    }
-    derived_lot_code &= 0x03FFFFFF;
-
-    device_id |= y_coord << 0;
-    device_id |= x_coord << 9;
-    device_id |= wafer_id << 18;
-    device_id |= derived_lot_code << 24;
-    device_id |= fab_code << 50;
-
-    return device_id;
-}
-
-/* Derive the HardwareType with firmware specific checks. */
-uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware) {
-    uint32_t fuse_reserved_odm4 = fuse_get_reserved_odm(4);
-    uint32_t hardware_type = (((fuse_reserved_odm4 >> 7) & 2) | ((fuse_reserved_odm4 >> 2) & 1));
-
-    if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_4_0_0) {
-        volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
-        uint32_t fuse_spare_bit9 = (fuse_chip->FUSE_SPARE_BIT[9] & 1);
-
-        switch (hardware_type) {
-            case 0x00: return (fuse_spare_bit9 == 0) ? 0 : 3;
-            case 0x01: return 0;        /* HardwareType_Icosa */
-            case 0x02: return 1;        /* HardwareType_Copper */
-            default:   return 3;        /* HardwareType_Undefined */
-        }
-    } else {
-        hardware_type |= ((fuse_reserved_odm4 >> 14) & 0x3C);
-
-        if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_7_0_0) {
-            switch (hardware_type) {
-                case 0x01: return 0;        /* HardwareType_Icosa */
-                case 0x02: return 1;        /* HardwareType_Copper */
-                case 0x04: return 3;        /* HardwareType_Iowa */
-                default:   return 4;        /* HardwareType_Undefined */
-            }
-        } else {
-            if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_10_0_0) {
-                switch (hardware_type) {
-                    case 0x01: return 0;        /* HardwareType_Icosa */
-                    case 0x02: return 4;        /* HardwareType_Calcio */
-                    case 0x04: return 3;        /* HardwareType_Iowa */
-                    case 0x08: return 2;        /* HardwareType_Hoag */
-                    default:   return 0xF;      /* HardwareType_Undefined */
-                }
-            } else {
-                switch (hardware_type) {
-                    case 0x01: return 0;        /* HardwareType_Icosa */
-                    case 0x02: return 4;        /* HardwareType_Calcio */
-                    case 0x04: return 3;        /* HardwareType_Iowa */
-                    case 0x08: return 2;        /* HardwareType_Hoag */
-                    case 0x10: return 5;        /* HardwareType_Five */
-                    default:   return 0xF;      /* HardwareType_Undefined */
-                }
-            }
-        }
-    }
-}
-
-/* Derive the HardwareType. */
-uint32_t fuse_get_hardware_type(void) {
-    return fuse_get_hardware_type_with_firmware_check(ATMOSPHERE_TARGET_FIRMWARE_CURRENT);
-}
-
-/* Derive the HardwareState. */
-uint32_t fuse_get_hardware_state(void) {
-    uint32_t fuse_reserved_odm4 = fuse_get_reserved_odm(4);
-    uint32_t hardware_state = (((fuse_reserved_odm4 >> 7) & 4) | (fuse_reserved_odm4 & 3));
-
-    switch (hardware_state) {
-        case 0x03: return 0;        /* HardwareState_Development */
-        case 0x04: return 1;        /* HardwareState_Production */
-        default:   return 2;        /* HardwareState_Undefined */
-    }
-}
-
-/* Derive the 16-byte HardwareInfo and copy to output buffer. */
-void fuse_get_hardware_info(void *dst) {
-    volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
-    uint32_t hw_info[0x4];
-
-    uint32_t ops_reserved = fuse_chip->FUSE_OPT_OPS_RESERVED & 0x3F;
-    uint32_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF;
-    uint32_t x_coord = fuse_chip->FUSE_OPT_X_COORDINATE & 0x1FF;
-    uint32_t wafer_id = fuse_chip->FUSE_OPT_WAFER_ID & 0x3F;
-    uint32_t lot_code_0 = fuse_chip->FUSE_OPT_LOT_CODE_0;
-    uint32_t lot_code_1 = fuse_chip->FUSE_OPT_LOT_CODE_1 & 0x0FFFFFFF;
-    uint32_t fab_code = fuse_chip->FUSE_OPT_FAB_CODE & 0x3F;
-    uint32_t vendor_code = fuse_chip->FUSE_OPT_VENDOR_CODE & 0xF;
-
-    /* Hardware Info = OPS_RESERVED || Y_COORD || X_COORD || WAFER_ID || LOT_CODE || FAB_CODE || VENDOR_ID */
-    hw_info[0] = (uint32_t)((lot_code_1 << 30) | (wafer_id << 24) | (x_coord << 15) | (y_coord << 6) | (ops_reserved));
-    hw_info[1] = (uint32_t)((lot_code_0 << 26) | (lot_code_1 >> 2));
-    hw_info[2] = (uint32_t)((fab_code << 26) | (lot_code_0 >> 6));
-    hw_info[3] = (uint32_t)(vendor_code);
-
-    memcpy(dst, hw_info, 0x10);
-}
-
-/* Check if have a new ODM fuse format. */
-bool fuse_is_new_format(void) {
-    return ((fuse_get_reserved_odm(4) & 0x800) && (fuse_get_reserved_odm(0) == 0x8E61ECAE) && (fuse_get_reserved_odm(1) == 0xF2BA3BB2));
-}
-
-/* Get the DeviceUniqueKeyGeneration. */
-uint32_t fuse_get_device_unique_key_generation(void) {
-    if (fuse_is_new_format()) {
-        return (fuse_get_reserved_odm(2) & 0x1F);
-    } else {
-        return 0;
-    }
-}
-
-/* Get the SocType from the HardwareType. */
-uint32_t fuse_get_soc_type(void) {
-    switch (fuse_get_hardware_type()) {
-        case 0:
-        case 1:
-            return 0;           /* SocType_Erista */
-        case 3:
-        case 2:
-        case 4:
-        case 5:
-            return 1;           /* SocType_Mariko */
-        default:
-            return 0xF;         /* SocType_Undefined */
-    }
-}
-
-/* Get the Regulator type. */
-uint32_t fuse_get_regulator(void) {
-    if (fuse_get_soc_type() == 1) {
-        return ((fuse_get_reserved_odm(28) & 1) + 1);   /* Regulator_Mariko_Max77812_A or Regulator_Mariko_Max77812_B */
-    } else {
-        return 0;               /* Regulator_Erista_Max77621 */
-    }
-}

fusee/fusee-mtc/src/fuse.h

@@ -1,484 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef FUSEE_FUSE_H
-#define FUSEE_FUSE_H
-
-#define FUSE_BASE 0x7000F800
-#define FUSE_CHIP_BASE (FUSE_BASE + 0x98)
-#define MAKE_FUSE_REG(n) MAKE_REG32(FUSE_BASE + n)
-#define MAKE_FUSE_CHIP_REG(n) MAKE_REG32(FUSE_CHIP_BASE + n)
-
-typedef struct {
-    uint32_t FUSE_FUSECTRL;
-    uint32_t FUSE_FUSEADDR;
-    uint32_t FUSE_FUSERDATA;
-    uint32_t FUSE_FUSEWDATA;
-    uint32_t FUSE_FUSETIME_RD1;
-    uint32_t FUSE_FUSETIME_RD2;
-    uint32_t FUSE_FUSETIME_PGM1;
-    uint32_t FUSE_FUSETIME_PGM2;
-    uint32_t FUSE_PRIV2INTFC_START;
-    uint32_t FUSE_FUSEBYPASS;
-    uint32_t FUSE_PRIVATEKEYDISABLE;
-    uint32_t FUSE_DISABLEREGPROGRAM;
-    uint32_t FUSE_WRITE_ACCESS_SW;
-    uint32_t FUSE_PWR_GOOD_SW;
-    uint32_t _0x38;
-    uint32_t FUSE_PRIV2RESHIFT;
-    uint32_t _0x40[0x3];
-    uint32_t FUSE_FUSETIME_RD3;
-    uint32_t _0x50[0xC];
-    uint32_t FUSE_PRIVATE_KEY0_NONZERO;
-    uint32_t FUSE_PRIVATE_KEY1_NONZERO;
-    uint32_t FUSE_PRIVATE_KEY2_NONZERO;
-    uint32_t FUSE_PRIVATE_KEY3_NONZERO;
-    uint32_t FUSE_PRIVATE_KEY4_NONZERO;
-    uint32_t _0x94;
-} tegra_fuse_t;
-
-typedef struct {
-    uint32_t _0x98[0x1A];
-    uint32_t FUSE_PRODUCTION_MODE;
-    uint32_t FUSE_JTAG_SECUREID_VALID;
-    uint32_t FUSE_ODM_LOCK;
-    uint32_t FUSE_OPT_OPENGL_EN;
-    uint32_t FUSE_SKU_INFO;
-    uint32_t FUSE_CPU_SPEEDO_0_CALIB;
-    uint32_t FUSE_CPU_IDDQ_CALIB;
-    uint32_t _0x11C[0x3];
-    uint32_t FUSE_OPT_FT_REV;
-    uint32_t FUSE_CPU_SPEEDO_1_CALIB;
-    uint32_t FUSE_CPU_SPEEDO_2_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_0_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_1_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_2_CALIB;
-    uint32_t FUSE_SOC_IDDQ_CALIB;
-    uint32_t _0x144;
-    uint32_t FUSE_FA;
-    uint32_t FUSE_RESERVED_PRODUCTION;
-    uint32_t FUSE_HDMI_LANE0_CALIB;
-    uint32_t FUSE_HDMI_LANE1_CALIB;
-    uint32_t FUSE_HDMI_LANE2_CALIB;
-    uint32_t FUSE_HDMI_LANE3_CALIB;
-    uint32_t FUSE_ENCRYPTION_RATE;
-    uint32_t FUSE_PUBLIC_KEY[0x8];
-    uint32_t FUSE_TSENSOR1_CALIB;
-    uint32_t FUSE_TSENSOR2_CALIB;
-    uint32_t _0x18C;
-    uint32_t FUSE_OPT_CP_REV;
-    uint32_t FUSE_OPT_PFG;
-    uint32_t FUSE_TSENSOR0_CALIB;
-    uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
-    uint32_t FUSE_SECURITY_MODE;
-    uint32_t FUSE_PRIVATE_KEY[0x5];
-    uint32_t FUSE_ARM_JTAG_DIS;
-    uint32_t FUSE_BOOT_DEVICE_INFO;
-    uint32_t FUSE_RESERVED_SW;
-    uint32_t FUSE_OPT_VP9_DISABLE;
-    uint32_t FUSE_RESERVED_ODM0[0x8];
-    uint32_t FUSE_OBS_DIS;
-    uint32_t _0x1EC;
-    uint32_t FUSE_USB_CALIB;
-    uint32_t FUSE_SKU_DIRECT_CONFIG;
-    uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
-    uint32_t FUSE_PACKAGE_INFO;
-    uint32_t FUSE_OPT_VENDOR_CODE;
-    uint32_t FUSE_OPT_FAB_CODE;
-    uint32_t FUSE_OPT_LOT_CODE_0;
-    uint32_t FUSE_OPT_LOT_CODE_1;
-    uint32_t FUSE_OPT_WAFER_ID;
-    uint32_t FUSE_OPT_X_COORDINATE;
-    uint32_t FUSE_OPT_Y_COORDINATE;
-    uint32_t FUSE_OPT_SEC_DEBUG_EN;
-    uint32_t FUSE_OPT_OPS_RESERVED;
-    uint32_t _0x224;
-    uint32_t FUSE_GPU_IDDQ_CALIB;
-    uint32_t FUSE_TSENSOR3_CALIB;
-    uint32_t FUSE_CLOCK_BOUNDOUT0;
-    uint32_t FUSE_CLOCK_BOUNDOUT1;
-    uint32_t _0x238[0x3];
-    uint32_t FUSE_OPT_SAMPLE_TYPE;
-    uint32_t FUSE_OPT_SUBREVISION;
-    uint32_t FUSE_OPT_SW_RESERVED_0;
-    uint32_t FUSE_OPT_SW_RESERVED_1;
-    uint32_t FUSE_TSENSOR4_CALIB;
-    uint32_t FUSE_TSENSOR5_CALIB;
-    uint32_t FUSE_TSENSOR6_CALIB;
-    uint32_t FUSE_TSENSOR7_CALIB;
-    uint32_t FUSE_OPT_PRIV_SEC_EN;
-    uint32_t _0x268[0x5];
-    uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
-    uint32_t FUSE_TSENSOR_COMMON;
-    uint32_t FUSE_OPT_CP_BIN;
-    uint32_t FUSE_OPT_GPU_DISABLE;
-    uint32_t FUSE_OPT_FT_BIN;
-    uint32_t FUSE_OPT_DONE_MAP;
-    uint32_t _0x294;
-    uint32_t FUSE_APB2JTAG_DISABLE;
-    uint32_t FUSE_ODM_INFO;
-    uint32_t _0x2A0[0x2];
-    uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
-    uint32_t _0x2AC[0x5];
-    uint32_t FUSE_WOA_SKU_FLAG;
-    uint32_t FUSE_ECO_RESERVE_1;
-    uint32_t FUSE_GCPLEX_CONFIG_FUSE;
-    uint32_t FUSE_PRODUCTION_MONTH;
-    uint32_t FUSE_RAM_REPAIR_INDICATOR;
-    uint32_t FUSE_TSENSOR9_CALIB;
-    uint32_t _0x2D8;
-    uint32_t FUSE_VMIN_CALIBRATION;
-    uint32_t FUSE_AGING_SENSOR_CALIBRATION;
-    uint32_t FUSE_DEBUG_AUTHENTICATION;
-    uint32_t FUSE_SECURE_PROVISION_INDEX;
-    uint32_t FUSE_SECURE_PROVISION_INFO;
-    uint32_t FUSE_OPT_GPU_DISABLE_CP1;
-    uint32_t FUSE_SPARE_ENDIS;
-    uint32_t FUSE_ECO_RESERVE_0;
-    uint32_t _0x2FC[0x2];
-    uint32_t FUSE_RESERVED_CALIB0;
-    uint32_t FUSE_RESERVED_CALIB1;
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
-    uint32_t FUSE_OPT_CPU_DISABLE;
-    uint32_t FUSE_OPT_CPU_DISABLE_CP1;
-    uint32_t FUSE_TSENSOR10_CALIB;
-    uint32_t FUSE_TSENSOR10_CALIB_AUX;
-    uint32_t _0x324[0x5];
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
-    uint32_t FUSE_OPT_CPU_DISABLE_CP2;
-    uint32_t FUSE_OPT_GPU_DISABLE_CP2;
-    uint32_t FUSE_USB_CALIB_EXT;
-    uint32_t FUSE_RESERVED_FIELD;
-    uint32_t _0x358[0x9];
-    uint32_t FUSE_SPARE_REALIGNMENT_REG;
-    uint32_t FUSE_SPARE_BIT[0x20];
-} tegra_fuse_chip_common_t;
-
-typedef struct {
-    uint32_t _0x98[0x1A];
-    uint32_t FUSE_PRODUCTION_MODE;
-    uint32_t FUSE_JTAG_SECUREID_VALID;
-    uint32_t FUSE_ODM_LOCK;
-    uint32_t FUSE_OPT_OPENGL_EN;
-    uint32_t FUSE_SKU_INFO;
-    uint32_t FUSE_CPU_SPEEDO_0_CALIB;
-    uint32_t FUSE_CPU_IDDQ_CALIB;
-    uint32_t _0x11C[0x3];
-    uint32_t FUSE_OPT_FT_REV;
-    uint32_t FUSE_CPU_SPEEDO_1_CALIB;
-    uint32_t FUSE_CPU_SPEEDO_2_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_0_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_1_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_2_CALIB;
-    uint32_t FUSE_SOC_IDDQ_CALIB;
-    uint32_t _0x144;
-    uint32_t FUSE_FA;
-    uint32_t FUSE_RESERVED_PRODUCTION;
-    uint32_t FUSE_HDMI_LANE0_CALIB;
-    uint32_t FUSE_HDMI_LANE1_CALIB;
-    uint32_t FUSE_HDMI_LANE2_CALIB;
-    uint32_t FUSE_HDMI_LANE3_CALIB;
-    uint32_t FUSE_ENCRYPTION_RATE;
-    uint32_t FUSE_PUBLIC_KEY[0x8];
-    uint32_t FUSE_TSENSOR1_CALIB;
-    uint32_t FUSE_TSENSOR2_CALIB;
-    uint32_t _0x18C;
-    uint32_t FUSE_OPT_CP_REV;
-    uint32_t FUSE_OPT_PFG;
-    uint32_t FUSE_TSENSOR0_CALIB;
-    uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
-    uint32_t FUSE_SECURITY_MODE;
-    uint32_t FUSE_PRIVATE_KEY[0x5];
-    uint32_t FUSE_ARM_JTAG_DIS;
-    uint32_t FUSE_BOOT_DEVICE_INFO;
-    uint32_t FUSE_RESERVED_SW;
-    uint32_t FUSE_OPT_VP9_DISABLE;
-    uint32_t FUSE_RESERVED_ODM0[0x8];
-    uint32_t FUSE_OBS_DIS;
-    uint32_t _0x1EC;
-    uint32_t FUSE_USB_CALIB;
-    uint32_t FUSE_SKU_DIRECT_CONFIG;
-    uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
-    uint32_t FUSE_PACKAGE_INFO;
-    uint32_t FUSE_OPT_VENDOR_CODE;
-    uint32_t FUSE_OPT_FAB_CODE;
-    uint32_t FUSE_OPT_LOT_CODE_0;
-    uint32_t FUSE_OPT_LOT_CODE_1;
-    uint32_t FUSE_OPT_WAFER_ID;
-    uint32_t FUSE_OPT_X_COORDINATE;
-    uint32_t FUSE_OPT_Y_COORDINATE;
-    uint32_t FUSE_OPT_SEC_DEBUG_EN;
-    uint32_t FUSE_OPT_OPS_RESERVED;
-    uint32_t FUSE_SATA_CALIB;               /* Erista only. */
-    uint32_t FUSE_GPU_IDDQ_CALIB;
-    uint32_t FUSE_TSENSOR3_CALIB;
-    uint32_t FUSE_CLOCK_BOUNDOUT0;
-    uint32_t FUSE_CLOCK_BOUNDOUT1;
-    uint32_t _0x238[0x3];
-    uint32_t FUSE_OPT_SAMPLE_TYPE;
-    uint32_t FUSE_OPT_SUBREVISION;
-    uint32_t FUSE_OPT_SW_RESERVED_0;
-    uint32_t FUSE_OPT_SW_RESERVED_1;
-    uint32_t FUSE_TSENSOR4_CALIB;
-    uint32_t FUSE_TSENSOR5_CALIB;
-    uint32_t FUSE_TSENSOR6_CALIB;
-    uint32_t FUSE_TSENSOR7_CALIB;
-    uint32_t FUSE_OPT_PRIV_SEC_EN;
-    uint32_t FUSE_PKC_DISABLE;              /* Erista only. */
-    uint32_t _0x26C[0x4];
-    uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
-    uint32_t FUSE_TSENSOR_COMMON;
-    uint32_t FUSE_OPT_CP_BIN;
-    uint32_t FUSE_OPT_GPU_DISABLE;
-    uint32_t FUSE_OPT_FT_BIN;
-    uint32_t FUSE_OPT_DONE_MAP;
-    uint32_t _0x294;
-    uint32_t FUSE_APB2JTAG_DISABLE;
-    uint32_t FUSE_ODM_INFO;
-    uint32_t _0x2A0[0x2];
-    uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
-    uint32_t _0x2AC[0x5];
-    uint32_t FUSE_WOA_SKU_FLAG;
-    uint32_t FUSE_ECO_RESERVE_1;
-    uint32_t FUSE_GCPLEX_CONFIG_FUSE;
-    uint32_t FUSE_PRODUCTION_MONTH;
-    uint32_t FUSE_RAM_REPAIR_INDICATOR;
-    uint32_t FUSE_TSENSOR9_CALIB;
-    uint32_t _0x2D8;
-    uint32_t FUSE_VMIN_CALIBRATION;
-    uint32_t FUSE_AGING_SENSOR_CALIBRATION;
-    uint32_t FUSE_DEBUG_AUTHENTICATION;
-    uint32_t FUSE_SECURE_PROVISION_INDEX;
-    uint32_t FUSE_SECURE_PROVISION_INFO;
-    uint32_t FUSE_OPT_GPU_DISABLE_CP1;
-    uint32_t FUSE_SPARE_ENDIS;
-    uint32_t FUSE_ECO_RESERVE_0;
-    uint32_t _0x2FC[0x2];
-    uint32_t FUSE_RESERVED_CALIB0;
-    uint32_t FUSE_RESERVED_CALIB1;
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
-    uint32_t FUSE_OPT_CPU_DISABLE;
-    uint32_t FUSE_OPT_CPU_DISABLE_CP1;
-    uint32_t FUSE_TSENSOR10_CALIB;
-    uint32_t FUSE_TSENSOR10_CALIB_AUX;
-    uint32_t FUSE_OPT_RAM_SVOP_DP;          /* Erista only. */
-    uint32_t FUSE_OPT_RAM_SVOP_PDP;         /* Erista only. */
-    uint32_t FUSE_OPT_RAM_SVOP_REG;         /* Erista only. */
-    uint32_t FUSE_OPT_RAM_SVOP_SP;          /* Erista only. */
-    uint32_t FUSE_OPT_RAM_SVOP_SMPDP;       /* Erista only. */
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
-    uint32_t FUSE_OPT_CPU_DISABLE_CP2;
-    uint32_t FUSE_OPT_GPU_DISABLE_CP2;
-    uint32_t FUSE_USB_CALIB_EXT;
-    uint32_t FUSE_RESERVED_FIELD;
-    uint32_t _0x358[0x9];
-    uint32_t FUSE_SPARE_REALIGNMENT_REG;
-    uint32_t FUSE_SPARE_BIT[0x20];
-} tegra_fuse_chip_erista_t;
-
-typedef struct {
-    uint32_t FUSE_RESERVED_ODM8[0xE];       /* Mariko only. */
-    uint32_t FUSE_KEK[0x4];                 /* Mariko only. */
-    uint32_t FUSE_BEK[0x4];                 /* Mariko only. */
-    uint32_t _0xF0;                         /* Mariko only. */
-    uint32_t _0xF4;                         /* Mariko only. */
-    uint32_t _0xF8;                         /* Mariko only. */
-    uint32_t _0xFC;                         /* Mariko only. */
-    uint32_t FUSE_PRODUCTION_MODE;
-    uint32_t FUSE_JTAG_SECUREID_VALID;
-    uint32_t FUSE_ODM_LOCK;
-    uint32_t FUSE_OPT_OPENGL_EN;
-    uint32_t FUSE_SKU_INFO;
-    uint32_t FUSE_CPU_SPEEDO_0_CALIB;
-    uint32_t FUSE_CPU_IDDQ_CALIB;
-    uint32_t FUSE_RESERVED_ODM22[0x3];      /* Mariko only. */
-    uint32_t FUSE_OPT_FT_REV;
-    uint32_t FUSE_CPU_SPEEDO_1_CALIB;
-    uint32_t FUSE_CPU_SPEEDO_2_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_0_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_1_CALIB;
-    uint32_t FUSE_SOC_SPEEDO_2_CALIB;
-    uint32_t FUSE_SOC_IDDQ_CALIB;
-    uint32_t FUSE_RESERVED_ODM25;           /* Mariko only. */
-    uint32_t FUSE_FA;
-    uint32_t FUSE_RESERVED_PRODUCTION;
-    uint32_t FUSE_HDMI_LANE0_CALIB;
-    uint32_t FUSE_HDMI_LANE1_CALIB;
-    uint32_t FUSE_HDMI_LANE2_CALIB;
-    uint32_t FUSE_HDMI_LANE3_CALIB;
-    uint32_t FUSE_ENCRYPTION_RATE;
-    uint32_t FUSE_PUBLIC_KEY[0x8];
-    uint32_t FUSE_TSENSOR1_CALIB;
-    uint32_t FUSE_TSENSOR2_CALIB;
-    uint32_t FUSE_OPT_SECURE_SCC_DIS;       /* Mariko only. */
-    uint32_t FUSE_OPT_CP_REV;
-    uint32_t FUSE_OPT_PFG;
-    uint32_t FUSE_TSENSOR0_CALIB;
-    uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
-    uint32_t FUSE_SECURITY_MODE;
-    uint32_t FUSE_PRIVATE_KEY[0x5];
-    uint32_t FUSE_ARM_JTAG_DIS;
-    uint32_t FUSE_BOOT_DEVICE_INFO;
-    uint32_t FUSE_RESERVED_SW;
-    uint32_t FUSE_OPT_VP9_DISABLE;
-    uint32_t FUSE_RESERVED_ODM0[0x8];
-    uint32_t FUSE_OBS_DIS;
-    uint32_t _0x1EC;                        /* Mariko only. */
-    uint32_t FUSE_USB_CALIB;
-    uint32_t FUSE_SKU_DIRECT_CONFIG;
-    uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
-    uint32_t FUSE_PACKAGE_INFO;
-    uint32_t FUSE_OPT_VENDOR_CODE;
-    uint32_t FUSE_OPT_FAB_CODE;
-    uint32_t FUSE_OPT_LOT_CODE_0;
-    uint32_t FUSE_OPT_LOT_CODE_1;
-    uint32_t FUSE_OPT_WAFER_ID;
-    uint32_t FUSE_OPT_X_COORDINATE;
-    uint32_t FUSE_OPT_Y_COORDINATE;
-    uint32_t FUSE_OPT_SEC_DEBUG_EN;
-    uint32_t FUSE_OPT_OPS_RESERVED;
-    uint32_t _0x224;                        /* Mariko only. */
-    uint32_t FUSE_GPU_IDDQ_CALIB;
-    uint32_t FUSE_TSENSOR3_CALIB;
-    uint32_t FUSE_CLOCK_BOUNDOUT0;
-    uint32_t FUSE_CLOCK_BOUNDOUT1;
-    uint32_t FUSE_RESERVED_ODM26[0x3];      /* Mariko only. */
-    uint32_t FUSE_OPT_SAMPLE_TYPE;
-    uint32_t FUSE_OPT_SUBREVISION;
-    uint32_t FUSE_OPT_SW_RESERVED_0;
-    uint32_t FUSE_OPT_SW_RESERVED_1;
-    uint32_t FUSE_TSENSOR4_CALIB;
-    uint32_t FUSE_TSENSOR5_CALIB;
-    uint32_t FUSE_TSENSOR6_CALIB;
-    uint32_t FUSE_TSENSOR7_CALIB;
-    uint32_t FUSE_OPT_PRIV_SEC_EN;
-    uint32_t FUSE_BOOT_SECURITY_INFO;       /* Mariko only. */
-    uint32_t _0x26C;                        /* Mariko only. */
-    uint32_t _0x270;                        /* Mariko only. */
-    uint32_t _0x274;                        /* Mariko only. */
-    uint32_t _0x278;                        /* Mariko only. */
-    uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
-    uint32_t FUSE_TSENSOR_COMMON;
-    uint32_t FUSE_OPT_CP_BIN;
-    uint32_t FUSE_OPT_GPU_DISABLE;
-    uint32_t FUSE_OPT_FT_BIN;
-    uint32_t FUSE_OPT_DONE_MAP;
-    uint32_t FUSE_RESERVED_ODM29;           /* Mariko only. */
-    uint32_t FUSE_APB2JTAG_DISABLE;
-    uint32_t FUSE_ODM_INFO;
-    uint32_t _0x2A0[0x2];
-    uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
-    uint32_t _0x2AC;
-    uint32_t _0x2B0;                        /* Mariko only. */
-    uint32_t _0x2B4;                        /* Mariko only. */
-    uint32_t _0x2B8;                        /* Mariko only. */
-    uint32_t _0x2BC;                        /* Mariko only. */
-    uint32_t FUSE_WOA_SKU_FLAG;
-    uint32_t FUSE_ECO_RESERVE_1;
-    uint32_t FUSE_GCPLEX_CONFIG_FUSE;
-    uint32_t FUSE_PRODUCTION_MONTH;
-    uint32_t FUSE_RAM_REPAIR_INDICATOR;
-    uint32_t FUSE_TSENSOR9_CALIB;
-    uint32_t _0x2D8;
-    uint32_t FUSE_VMIN_CALIBRATION;
-    uint32_t FUSE_AGING_SENSOR_CALIBRATION;
-    uint32_t FUSE_DEBUG_AUTHENTICATION;
-    uint32_t FUSE_SECURE_PROVISION_INDEX;
-    uint32_t FUSE_SECURE_PROVISION_INFO;
-    uint32_t FUSE_OPT_GPU_DISABLE_CP1;
-    uint32_t FUSE_SPARE_ENDIS;
-    uint32_t FUSE_ECO_RESERVE_0;
-    uint32_t _0x2FC[0x2];
-    uint32_t FUSE_RESERVED_CALIB0;
-    uint32_t FUSE_RESERVED_CALIB1;
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
-    uint32_t FUSE_OPT_CPU_DISABLE;
-    uint32_t FUSE_OPT_CPU_DISABLE_CP1;
-    uint32_t FUSE_TSENSOR10_CALIB;
-    uint32_t FUSE_TSENSOR10_CALIB_AUX;
-    uint32_t _0x324;                        /* Mariko only. */
-    uint32_t _0x328;                        /* Mariko only. */
-    uint32_t _0x32C;                        /* Mariko only. */
-    uint32_t _0x330;                        /* Mariko only. */
-    uint32_t _0x334;                        /* Mariko only. */
-    uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
-    uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
-    uint32_t FUSE_OPT_CPU_DISABLE_CP2;
-    uint32_t FUSE_OPT_GPU_DISABLE_CP2;
-    uint32_t FUSE_USB_CALIB_EXT;
-    uint32_t FUSE_RESERVED_FIELD;
-    uint32_t _0x358[0x9];
-    uint32_t FUSE_SPARE_REALIGNMENT_REG;
-    uint32_t FUSE_SPARE_BIT[0x1E];
-} tegra_fuse_chip_mariko_t;
-
-static inline volatile tegra_fuse_t *fuse_get_regs(void)
-{
-    return (volatile tegra_fuse_t *)FUSE_BASE;
-}
-
-static inline volatile tegra_fuse_chip_common_t *fuse_chip_common_get_regs(void)
-{
-    return (volatile tegra_fuse_chip_common_t *)FUSE_CHIP_BASE;
-}
-
-static inline volatile tegra_fuse_chip_erista_t *fuse_chip_erista_get_regs(void)
-{
-    return (volatile tegra_fuse_chip_erista_t *)FUSE_CHIP_BASE;
-}
-
-static inline volatile tegra_fuse_chip_mariko_t *fuse_chip_mariko_get_regs(void)
-{
-    return (volatile tegra_fuse_chip_mariko_t *)FUSE_CHIP_BASE;
-}
-
-void fuse_init(void);
-void fuse_disable_programming(void);
-void fuse_disable_private_key(void);
-void fuse_enable_power(void);
-void fuse_disable_power(void);
-
-uint32_t fuse_get_sku_info(void);
-uint32_t fuse_get_spare_bit(uint32_t index);
-uint32_t fuse_get_reserved_odm(uint32_t index);
-uint32_t fuse_get_bootrom_patch_version(void);
-uint64_t fuse_get_device_id(void);
-uint32_t fuse_get_dram_id(void);
-uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware);
-uint32_t fuse_get_hardware_type(void);
-uint32_t fuse_get_retail_type(void);
-void fuse_get_hardware_info(void *dst);
-bool fuse_is_new_format(void);
-uint32_t fuse_get_device_unique_key_generation(void);
-uint32_t fuse_get_soc_type(void);
-uint32_t fuse_get_regulator(void);
-
-uint32_t fuse_hw_read(uint32_t addr);
-void fuse_hw_write(uint32_t value, uint32_t addr);
-void fuse_hw_sense(void);
-
-#endif

fusee/fusee-mtc/src/init.c

@@ -1,86 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include <stdint.h>
-#include <stddef.h>
-#include <string.h>
-#include <malloc.h>
-#include <sys/iosupport.h>
-#include "stage2.h"
-#include "utils.h"
-
-void __libc_init_array(void);
-void __libc_fini_array(void);
-
-extern uint8_t __bss_start__[], __bss_end__[];
-extern uint8_t __heap_start__[], __heap_end__[];
-
-extern char *fake_heap_start;
-extern char *fake_heap_end;
-
-int __program_argc;
-void **__program_argv;
-
-void __program_exit(int rc);
-static void __program_parse_argc_argv(int argc, char *argdata);
-static void __program_cleanup_argv(void);
-
-static void __program_init_heap(void) {
-    fake_heap_start = (char*)__heap_start__;
-    fake_heap_end   = (char*)__heap_end__;
-}
-
-static void __program_init_newlib_hooks(void) {
-    __syscalls.exit = __program_exit; /* For exit, etc. */
-}
-
-void __program_init(int argc, char *argdata) {
-    /* Zero-fill the .bss section */
-    memset(__bss_start__, 0, __bss_end__ - __bss_start__);
-    
-    __program_init_heap();
-    __program_init_newlib_hooks();
-    __program_parse_argc_argv(argc, argdata);
-    __libc_init_array();
-}
-
-void __program_exit(int rc) {
-    __libc_fini_array();
-    __program_cleanup_argv();
-}
-
-static void __program_parse_argc_argv(int argc, char *argdata) {
-    __program_argc = argc;
-
-    __program_argv = malloc(argc * sizeof(void **));
-    if (__program_argv == NULL) {
-        generic_panic();
-    }
-    
-    __program_argv[0] = malloc(sizeof(stage2_mtc_args_t));
-    if (__program_argv[0] == NULL) {
-        generic_panic();
-    }
-    memcpy(__program_argv[0], argdata, sizeof(stage2_mtc_args_t));
-}
-
-static void __program_cleanup_argv(void) {
-    for (int i = 0; i < __program_argc; i++) {
-        free(__program_argv[i]);
-        __program_argv[i] = NULL;
-    }
-    free(__program_argv);
-}

fusee/fusee-mtc/src/main.c

@@ -1,57 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <string.h>
-#include "mtc.h"
-#include "stage2.h"
-#include "../../../fusee/common/display/video_fb.h"
-
-static void *g_framebuffer;
-static __attribute__((__aligned__(0x200))) stage2_mtc_args_t g_mtc_args_store;
-static stage2_mtc_args_t *g_mtc_args;
-
-/* Allow for main(int argc, void **argv) signature. */
-#pragma GCC diagnostic ignored "-Wmain"
-
-int main(int argc, void **argv) {
-    ScreenLogLevel log_level = SCREEN_LOG_LEVEL_NONE;
-    
-    /* Check argc. */
-    if (argc != MTC_ARGC) {
-        return 1;
-    }
-    
-    /* Extract arguments from argv. */
-    g_mtc_args = &g_mtc_args_store;
-    memcpy(g_mtc_args, (stage2_mtc_args_t *)argv[MTC_ARGV_ARGUMENT_STRUCT], sizeof(*g_mtc_args));
-    log_level = g_mtc_args->log_level;
-    
-    /* Override the global logging level. */
-    log_set_log_level(log_level);
-    
-    if (log_level != SCREEN_LOG_LEVEL_NONE) {
-        /* Set framebuffer address. */
-        g_framebuffer = (void *)0xC0000000;
-    
-        /* Zero-fill the framebuffer and register it as printk provider. */
-        video_init(g_framebuffer);
-    }
-    
-    /* Train DRAM. */
-    train_dram();
-
-    return 0;
-}

fusee/fusee-mtc/src/mc.c

@@ -1,167 +0,0 @@
-/*
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include "mc.h"
-#include "car.h"
-#include "timers.h"
-
-void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock)
-{
-    MAKE_MC_REG(MC_SEC_CARVEOUT_BOM) = bom;
-    MAKE_MC_REG(MC_SEC_CARVEOUT_SIZE_MB) = size1mb;
-    
-    if (lock)
-        MAKE_MC_REG(MC_SEC_CARVEOUT_REG_CTRL) = 1;
-}
-
-void mc_config_carveout()
-{
-    *(volatile uint32_t *)0x8005FFFC = 0xC0EDBBCC;
-    
-    MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = 1;
-    MAKE_MC_REG(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 0;
-    MAKE_MC_REG(MC_VIDEO_PROTECT_BOM) = 0;
-    MAKE_MC_REG(MC_VIDEO_PROTECT_SIZE_MB) = 0;
-    MAKE_MC_REG(MC_VIDEO_PROTECT_REG_CTRL) = 1;
-
-    mc_config_tsec_carveout(0, 0, true);
-
-    MAKE_MC_REG(MC_MTS_CARVEOUT_BOM) = 0;
-    MAKE_MC_REG(MC_MTS_CARVEOUT_SIZE_MB) = 0;
-    MAKE_MC_REG(MC_MTS_CARVEOUT_ADR_HI) = 0;
-    MAKE_MC_REG(MC_MTS_CARVEOUT_REG_CTRL) = 1;
-    
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_BOM_HI) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_SIZE_128KB) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT1_CFG0) = 0x4000006;
-
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_BOM) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_BOM_HI) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_SIZE_128KB) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR));
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = (BIT(CSR_GPUSRD2) | BIT(CSW_GPUSWR2));
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT3_CFG0) = 0x4401E7E;
-    
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_BOM_HI) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_SIZE_128KB) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT4_CFG0) = 0x8F;
-    
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_BOM_HI) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_SIZE_128KB) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT5_CFG0) = 0x8F;
-}
-
-void mc_config_carveout_finalize()
-{
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_BOM) = 0x80020000;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_BOM_HI) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_SIZE_128KB) = 2;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = (BIT(CSR_GPUSRD) | BIT(CSW_GPUSWR));
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = (BIT(CSR_GPUSRD2) | BIT(CSW_GPUSWR2));
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-    MAKE_MC_REG(MC_SECURITY_CARVEOUT2_CFG0) = 0x440167E;
-}
-
-void mc_enable_ahb_redirect()
-{
-    volatile tegra_car_t *car = car_get_regs();
-    car->lvl2_clk_gate_ovrd = ((car->lvl2_clk_gate_ovrd & 0xFFF7FFFF) | 0x80000);
-    
-    MAKE_MC_REG(MC_IRAM_BOM) = 0x40000000;
-    MAKE_MC_REG(MC_IRAM_TOM) = 0x4003F000;
-}
-
-void mc_disable_ahb_redirect()
-{
-    volatile tegra_car_t *car = car_get_regs();
-    
-    MAKE_MC_REG(MC_IRAM_BOM) = 0xFFFFF000;
-    MAKE_MC_REG(MC_IRAM_TOM) = 0;
-    
-    car->lvl2_clk_gate_ovrd &= 0xFFF7FFFF;
-}
-
-void mc_enable()
-{
-    volatile tegra_car_t *car = car_get_regs();
-    
-    /* Set EMC clock source. */
-    car->clk_source_emc = ((car->clk_source_emc & 0x1FFFFFFF) | 0x40000000);
-    
-    /* Enable MIPI CAL clock. */
-    car->clk_enb_h_set = ((car->clk_enb_h_set & 0xFDFFFFFF) | 0x2000000);
-    
-    /* Enable MC clock. */
-    car->clk_enb_h_set = ((car->clk_enb_h_set & 0xFFFFFFFE) | 1);
-
-    /* Enable EMC DLL clock. */
-    car->clk_enb_x_set = ((car->clk_enb_x_set & 0xFFFFBFFF) | 0x4000);
-    
-    /* Clear EMC and MC reset. */
-    car->rst_dev_h_set = 0x2000001; 
-    udelay(5);
-
-    mc_disable_ahb_redirect();
-}

fusee/fusee-mtc/src/mc.h

@@ -1,606 +0,0 @@
-/*
- * Copyright (c) 2014, NVIDIA Corporation. All rights reserved.
- * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_MC_H_
-#define FUSEE_MC_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#define MC_BASE  0x70019000
-#define MAKE_MC_REG(n) MAKE_REG32(MC_BASE + n)
-
-#define MC_INTSTATUS                                            0x0
-#define MC_INTMASK                                              0x4
-#define MC_ERR_STATUS                                           0x8
-#define MC_ERR_ADR                                              0xc
-#define MC_SMMU_CONFIG                                          0x10
-#define MC_SMMU_TLB_CONFIG                                      0x14
-#define MC_SMMU_PTC_CONFIG                                      0x18
-#define MC_SMMU_PTB_ASID                                        0x1c
-#define MC_SMMU_PTB_DATA                                        0x20
-#define MC_SMMU_TLB_FLUSH                                       0x30
-#define MC_SMMU_PTC_FLUSH                                       0x34
-#define MC_SMMU_ASID_SECURITY                                   0x38
-#define MC_SMMU_ASID_SECURITY_1                                 0x3c
-#define MC_SMMU_ASID_SECURITY_2                                 0x9e0
-#define MC_SMMU_ASID_SECURITY_3                                 0x9e4
-#define MC_SMMU_ASID_SECURITY_4                                 0x9e8
-#define MC_SMMU_ASID_SECURITY_5                                 0x9ec
-#define MC_SMMU_ASID_SECURITY_6                                 0x9f0
-#define MC_SMMU_ASID_SECURITY_7                                 0x9f4
-#define MC_SMMU_AFI_ASID                                        0x238
-#define MC_SMMU_AVPC_ASID                                       0x23c
-#define MC_SMMU_TSEC_ASID                                       0x294
-#define MC_SMMU_PPCS1_ASID                                      0x298
-#define MC_SMMU_TRANSLATION_ENABLE_0                            0x228
-#define MC_SMMU_TRANSLATION_ENABLE_1                            0x22c
-#define MC_SMMU_TRANSLATION_ENABLE_2                            0x230
-#define MC_SMMU_TRANSLATION_ENABLE_3                            0x234
-#define MC_SMMU_TRANSLATION_ENABLE_4                            0xb98
-#define MC_PCFIFO_CLIENT_CONFIG0                                0xdd0
-#define MC_PCFIFO_CLIENT_CONFIG1                                0xdd4
-#define MC_PCFIFO_CLIENT_CONFIG2                                0xdd8
-#define MC_PCFIFO_CLIENT_CONFIG3                                0xddc
-#define MC_PCFIFO_CLIENT_CONFIG4                                0xde0
-#define MC_EMEM_CFG                                             0x50
-#define MC_EMEM_ADR_CFG                                         0x54
-#define MC_EMEM_ADR_CFG_DEV0                                    0x58
-#define MC_EMEM_ADR_CFG_DEV1                                    0x5c
-#define MC_EMEM_ADR_CFG_CHANNEL_MASK                            0x60
-#define MC_EMEM_ADR_CFG_BANK_MASK_0                             0x64
-#define MC_EMEM_ADR_CFG_BANK_MASK_1                             0x68
-#define MC_EMEM_ADR_CFG_BANK_MASK_2                             0x6c
-#define MC_SECURITY_CFG0                                        0x70
-#define MC_SECURITY_CFG1                                        0x74
-#define MC_SECURITY_CFG3                                        0x9bc
-#define MC_SECURITY_RSV                                         0x7c
-#define MC_EMEM_ARB_CFG                                         0x90
-#define MC_EMEM_ARB_OUTSTANDING_REQ                             0x94
-#define MC_EMEM_ARB_TIMING_RCD                                  0x98
-#define MC_EMEM_ARB_TIMING_RP                                   0x9c
-#define MC_EMEM_ARB_TIMING_RC                                   0xa0
-#define MC_EMEM_ARB_TIMING_RAS                                  0xa4
-#define MC_EMEM_ARB_TIMING_FAW                                  0xa8
-#define MC_EMEM_ARB_TIMING_RRD                                  0xac
-#define MC_EMEM_ARB_TIMING_RAP2PRE                              0xb0
-#define MC_EMEM_ARB_TIMING_WAP2PRE                              0xb4
-#define MC_EMEM_ARB_TIMING_R2R                                  0xb8
-#define MC_EMEM_ARB_TIMING_W2W                                  0xbc
-#define MC_EMEM_ARB_TIMING_R2W                                  0xc0
-#define MC_EMEM_ARB_TIMING_W2R                                  0xc4
-#define MC_EMEM_ARB_TIMING_RFCPB                                0x6c0
-#define MC_EMEM_ARB_TIMING_CCDMW                                0x6c4
-#define MC_EMEM_ARB_REFPB_HP_CTRL                               0x6f0
-#define MC_EMEM_ARB_REFPB_BANK_CTRL                             0x6f4
-#define MC_EMEM_ARB_DA_TURNS                                    0xd0
-#define MC_EMEM_ARB_DA_COVERS                                   0xd4
-#define MC_EMEM_ARB_MISC0                                       0xd8
-#define MC_EMEM_ARB_MISC1                                       0xdc
-#define MC_EMEM_ARB_MISC2                                       0xc8
-#define MC_EMEM_ARB_RING1_THROTTLE                              0xe0
-#define MC_EMEM_ARB_RING3_THROTTLE                              0xe4
-#define MC_EMEM_ARB_NISO_THROTTLE                               0x6b0
-#define MC_EMEM_ARB_OVERRIDE                                    0xe8
-#define MC_EMEM_ARB_RSV                                         0xec
-#define MC_CLKEN_OVERRIDE                                       0xf4
-#define MC_TIMING_CONTROL_DBG                                   0xf8
-#define MC_TIMING_CONTROL                                       0xfc
-#define MC_STAT_CONTROL                                         0x100
-#define MC_STAT_STATUS                                          0x104
-#define MC_STAT_EMC_CLOCK_LIMIT                                 0x108
-#define MC_STAT_EMC_CLOCK_LIMIT_MSBS                            0x10c
-#define MC_STAT_EMC_CLOCKS                                      0x110
-#define MC_STAT_EMC_CLOCKS_MSBS                                 0x114
-#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_LO                    0x118
-#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_LO                    0x158
-#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_HI                    0x11c
-#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_HI                    0x15c
-#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_UPPER                 0xa20
-#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_UPPER                 0xa24
-#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_LO            0x198
-#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_LO            0x1a8
-#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_HI            0x19c
-#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_HI            0x1ac
-#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_UPPER         0xa28
-#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_UPPER         0xa2c
-#define MC_STAT_EMC_FILTER_SET0_ASID                            0x1a0
-#define MC_STAT_EMC_FILTER_SET1_ASID                            0x1b0
-#define MC_STAT_EMC_FILTER_SET0_SLACK_LIMIT                     0x120
-#define MC_STAT_EMC_FILTER_SET1_SLACK_LIMIT                     0x160
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_0                        0x128
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_0                        0x168
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_1                        0x12c
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_1                        0x16c
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_2                        0x130
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_2                        0x170
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_3                        0x134
-#define MC_STAT_EMC_FILTER_SET0_CLIENT_4                        0xb88
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_3                        0x174
-#define MC_STAT_EMC_FILTER_SET1_CLIENT_4                        0xb8c
-#define MC_STAT_EMC_SET0_COUNT                                  0x138
-#define MC_STAT_EMC_SET0_COUNT_MSBS                             0x13c
-#define MC_STAT_EMC_SET1_COUNT                                  0x178
-#define MC_STAT_EMC_SET1_COUNT_MSBS                             0x17c
-#define MC_STAT_EMC_SET0_SLACK_ACCUM                            0x140
-#define MC_STAT_EMC_SET0_SLACK_ACCUM_MSBS                       0x144
-#define MC_STAT_EMC_SET1_SLACK_ACCUM                            0x180
-#define MC_STAT_EMC_SET1_SLACK_ACCUM_MSBS                       0x184
-#define MC_STAT_EMC_SET0_HISTO_COUNT                            0x148
-#define MC_STAT_EMC_SET0_HISTO_COUNT_MSBS                       0x14c
-#define MC_STAT_EMC_SET1_HISTO_COUNT                            0x188
-#define MC_STAT_EMC_SET1_HISTO_COUNT_MSBS                       0x18c
-#define MC_STAT_EMC_SET0_MINIMUM_SLACK_OBSERVED                 0x150
-#define MC_STAT_EMC_SET1_MINIMUM_SLACK_OBSERVED                 0x190
-#define MC_STAT_EMC_SET0_IDLE_CYCLE_COUNT                       0x1b8
-#define MC_STAT_EMC_SET0_IDLE_CYCL_COUNT_MSBS                   0x1bc
-#define MC_STAT_EMC_SET1_IDLE_CYCLE_COUNT                       0x1c8
-#define MC_STAT_EMC_SET1_IDLE_CYCL_COUNT_MSBS                   0x1cc
-#define MC_STAT_EMC_SET0_IDLE_CYCLE_PARTITION_SELECT            0x1c0
-#define MC_STAT_EMC_SET1_IDLE_CYCLE_PARTITION_SELECT            0x1d0
-#define MC_CLIENT_HOTRESET_CTRL                                 0x200
-#define MC_CLIENT_HOTRESET_CTRL_1                               0x970
-#define MC_CLIENT_HOTRESET_STATUS                               0x204
-#define MC_CLIENT_HOTRESET_STATUS_1                             0x974
-#define MC_EMEM_ARB_ISOCHRONOUS_0                               0x208
-#define MC_EMEM_ARB_ISOCHRONOUS_1                               0x20c
-#define MC_EMEM_ARB_ISOCHRONOUS_2                               0x210
-#define MC_EMEM_ARB_ISOCHRONOUS_3                               0x214
-#define MC_EMEM_ARB_ISOCHRONOUS_4                               0xb94
-#define MC_EMEM_ARB_HYSTERESIS_0                                0x218
-#define MC_EMEM_ARB_HYSTERESIS_1                                0x21c
-#define MC_EMEM_ARB_HYSTERESIS_2                                0x220
-#define MC_EMEM_ARB_HYSTERESIS_3                                0x224
-#define MC_EMEM_ARB_HYSTERESIS_4                                0xb84
-#define MC_EMEM_ARB_DHYSTERESIS_0                               0xbb0
-#define MC_EMEM_ARB_DHYSTERESIS_1                               0xbb4
-#define MC_EMEM_ARB_DHYSTERESIS_2                               0xbb8
-#define MC_EMEM_ARB_DHYSTERESIS_3                               0xbbc
-#define MC_EMEM_ARB_DHYSTERESIS_4                               0xbc0
-#define MC_EMEM_ARB_DHYST_CTRL                                  0xbcc
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0                        0xbd0
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1                        0xbd4
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2                        0xbd8
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3                        0xbdc
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4                        0xbe0
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5                        0xbe4
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6                        0xbe8
-#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7                        0xbec
-#define MC_RESERVED_RSV                                         0x3fc
-#define MC_DISB_EXTRA_SNAP_LEVELS                               0x408
-#define MC_APB_EXTRA_SNAP_LEVELS                                0x2a4
-#define MC_AHB_EXTRA_SNAP_LEVELS                                0x2a0
-#define MC_USBD_EXTRA_SNAP_LEVELS                               0xa18
-#define MC_ISP_EXTRA_SNAP_LEVELS                                0xa08
-#define MC_AUD_EXTRA_SNAP_LEVELS                                0xa10
-#define MC_MSE_EXTRA_SNAP_LEVELS                                0x40c
-#define MC_GK2_EXTRA_SNAP_LEVELS                                0xa40
-#define MC_A9AVPPC_EXTRA_SNAP_LEVELS                            0x414
-#define MC_FTOP_EXTRA_SNAP_LEVELS                               0x2bc
-#define MC_JPG_EXTRA_SNAP_LEVELS                                0xa3c
-#define MC_HOST_EXTRA_SNAP_LEVELS                               0xa14
-#define MC_SAX_EXTRA_SNAP_LEVELS                                0x2c0
-#define MC_DIS_EXTRA_SNAP_LEVELS                                0x2ac
-#define MC_VICPC_EXTRA_SNAP_LEVELS                              0xa1c
-#define MC_HDAPC_EXTRA_SNAP_LEVELS                              0xa48
-#define MC_AVP_EXTRA_SNAP_LEVELS                                0x2a8
-#define MC_USBX_EXTRA_SNAP_LEVELS                               0x404
-#define MC_PCX_EXTRA_SNAP_LEVELS                                0x2b8
-#define MC_SD_EXTRA_SNAP_LEVELS                                 0xa04
-#define MC_DFD_EXTRA_SNAP_LEVELS                                0xa4c
-#define MC_VE_EXTRA_SNAP_LEVELS                                 0x2d8
-#define MC_GK_EXTRA_SNAP_LEVELS                                 0xa00
-#define MC_VE2_EXTRA_SNAP_LEVELS                                0x410
-#define MC_SDM_EXTRA_SNAP_LEVELS                                0xa44
-#define MC_VIDEO_PROTECT_BOM                                    0x648
-#define MC_VIDEO_PROTECT_SIZE_MB                                0x64c
-#define MC_VIDEO_PROTECT_BOM_ADR_HI                             0x978
-#define MC_VIDEO_PROTECT_REG_CTRL                               0x650
-#define MC_ERR_VPR_STATUS                                       0x654
-#define MC_ERR_VPR_ADR                                          0x658
-#define MC_VIDEO_PROTECT_VPR_OVERRIDE                           0x418
-#define MC_VIDEO_PROTECT_VPR_OVERRIDE1                          0x590
-#define MC_IRAM_BOM                                             0x65c
-#define MC_IRAM_TOM                                             0x660
-#define MC_IRAM_ADR_HI                                          0x980
-#define MC_IRAM_REG_CTRL                                        0x964
-#define MC_EMEM_CFG_ACCESS_CTRL                                 0x664
-#define MC_TZ_SECURITY_CTRL                                     0x668
-#define MC_EMEM_ARB_OUTSTANDING_REQ_RING3                       0x66c
-#define MC_EMEM_ARB_OUTSTANDING_REQ_NISO                        0x6b4
-#define MC_EMEM_ARB_RING0_THROTTLE_MASK                         0x6bc
-#define MC_EMEM_ARB_NISO_THROTTLE_MASK                          0x6b8
-#define MC_EMEM_ARB_NISO_THROTTLE_MASK_1                        0xb80
-#define MC_SEC_CARVEOUT_BOM                                     0x670
-#define MC_SEC_CARVEOUT_SIZE_MB                                 0x674
-#define MC_SEC_CARVEOUT_ADR_HI                                  0x9d4
-#define MC_SEC_CARVEOUT_REG_CTRL                                0x678
-#define MC_ERR_SEC_STATUS                                       0x67c
-#define MC_ERR_SEC_ADR                                          0x680
-#define MC_PC_IDLE_CLOCK_GATE_CONFIG                            0x684
-#define MC_STUTTER_CONTROL                                      0x688
-#define MC_RESERVED_RSV_1                                       0x958
-#define MC_DVFS_PIPE_SELECT                                     0x95c
-#define MC_AHB_PTSA_MIN                                         0x4e0
-#define MC_AUD_PTSA_MIN                                         0x54c
-#define MC_MLL_MPCORER_PTSA_RATE                                0x44c
-#define MC_RING2_PTSA_RATE                                      0x440
-#define MC_USBD_PTSA_RATE                                       0x530
-#define MC_USBX_PTSA_MIN                                        0x528
-#define MC_USBD_PTSA_MIN                                        0x534
-#define MC_APB_PTSA_MAX                                         0x4f0
-#define MC_JPG_PTSA_RATE                                        0x584
-#define MC_DIS_PTSA_MIN                                         0x420
-#define MC_AVP_PTSA_MAX                                         0x4fc
-#define MC_AVP_PTSA_RATE                                        0x4f4
-#define MC_RING1_PTSA_MIN                                       0x480
-#define MC_DIS_PTSA_MAX                                         0x424
-#define MC_SD_PTSA_MAX                                          0x4d8
-#define MC_MSE_PTSA_RATE                                        0x4c4
-#define MC_VICPC_PTSA_MIN                                       0x558
-#define MC_PCX_PTSA_MAX                                         0x4b4
-#define MC_ISP_PTSA_RATE                                        0x4a0
-#define MC_A9AVPPC_PTSA_MIN                                     0x48c
-#define MC_RING2_PTSA_MAX                                       0x448
-#define MC_AUD_PTSA_RATE                                        0x548
-#define MC_HOST_PTSA_MIN                                        0x51c
-#define MC_MLL_MPCORER_PTSA_MAX                                 0x454
-#define MC_SD_PTSA_MIN                                          0x4d4
-#define MC_RING1_PTSA_RATE                                      0x47c
-#define MC_JPG_PTSA_MIN                                         0x588
-#define MC_HDAPC_PTSA_MIN                                       0x62c
-#define MC_AVP_PTSA_MIN                                         0x4f8
-#define MC_JPG_PTSA_MAX                                         0x58c
-#define MC_VE_PTSA_MAX                                          0x43c
-#define MC_DFD_PTSA_MAX                                         0x63c
-#define MC_VICPC_PTSA_RATE                                      0x554
-#define MC_GK_PTSA_MAX                                          0x544
-#define MC_VICPC_PTSA_MAX                                       0x55c
-#define MC_SDM_PTSA_MAX                                         0x624
-#define MC_SAX_PTSA_RATE                                        0x4b8
-#define MC_PCX_PTSA_MIN                                         0x4b0
-#define MC_APB_PTSA_MIN                                         0x4ec
-#define MC_GK2_PTSA_MIN                                         0x614
-#define MC_PCX_PTSA_RATE                                        0x4ac
-#define MC_RING1_PTSA_MAX                                       0x484
-#define MC_HDAPC_PTSA_RATE                                      0x628
-#define MC_MLL_MPCORER_PTSA_MIN                                 0x450
-#define MC_GK2_PTSA_MAX                                         0x618
-#define MC_AUD_PTSA_MAX                                         0x550
-#define MC_GK2_PTSA_RATE                                        0x610
-#define MC_ISP_PTSA_MAX                                         0x4a8
-#define MC_DISB_PTSA_RATE                                       0x428
-#define MC_VE2_PTSA_MAX                                         0x49c
-#define MC_DFD_PTSA_MIN                                         0x638
-#define MC_FTOP_PTSA_RATE                                       0x50c
-#define MC_A9AVPPC_PTSA_RATE                                    0x488
-#define MC_VE2_PTSA_MIN                                         0x498
-#define MC_USBX_PTSA_MAX                                        0x52c
-#define MC_DIS_PTSA_RATE                                        0x41c
-#define MC_USBD_PTSA_MAX                                        0x538
-#define MC_A9AVPPC_PTSA_MAX                                     0x490
-#define MC_USBX_PTSA_RATE                                       0x524
-#define MC_FTOP_PTSA_MAX                                        0x514
-#define MC_HDAPC_PTSA_MAX                                       0x630
-#define MC_SD_PTSA_RATE                                         0x4d0
-#define MC_DFD_PTSA_RATE                                        0x634
-#define MC_FTOP_PTSA_MIN                                        0x510
-#define MC_SDM_PTSA_RATE                                        0x61c
-#define MC_AHB_PTSA_RATE                                        0x4dc
-#define MC_SMMU_SMMU_PTSA_MAX                                   0x460
-#define MC_RING2_PTSA_MIN                                       0x444
-#define MC_SDM_PTSA_MIN                                         0x620
-#define MC_APB_PTSA_RATE                                        0x4e8
-#define MC_MSE_PTSA_MIN                                         0x4c8
-#define MC_HOST_PTSA_RATE                                       0x518
-#define MC_VE_PTSA_RATE                                         0x434
-#define MC_AHB_PTSA_MAX                                         0x4e4
-#define MC_SAX_PTSA_MIN                                         0x4bc
-#define MC_SMMU_SMMU_PTSA_MIN                                   0x45c
-#define MC_ISP_PTSA_MIN                                         0x4a4
-#define MC_HOST_PTSA_MAX                                        0x520
-#define MC_SAX_PTSA_MAX                                         0x4c0
-#define MC_VE_PTSA_MIN                                          0x438
-#define MC_GK_PTSA_MIN                                          0x540
-#define MC_MSE_PTSA_MAX                                         0x4cc
-#define MC_DISB_PTSA_MAX                                        0x430
-#define MC_DISB_PTSA_MIN                                        0x42c
-#define MC_SMMU_SMMU_PTSA_RATE                                  0x458
-#define MC_VE2_PTSA_RATE                                        0x494
-#define MC_GK_PTSA_RATE                                         0x53c
-#define MC_PTSA_GRANT_DECREMENT                                 0x960
-#define MC_LATENCY_ALLOWANCE_AVPC_0                             0x2e4
-#define MC_LATENCY_ALLOWANCE_AXIAP_0                            0x3a0
-#define MC_LATENCY_ALLOWANCE_XUSB_1                             0x380
-#define MC_LATENCY_ALLOWANCE_ISP2B_0                            0x384
-#define MC_LATENCY_ALLOWANCE_SDMMCAA_0                          0x3bc
-#define MC_LATENCY_ALLOWANCE_SDMMCA_0                           0x3b8
-#define MC_LATENCY_ALLOWANCE_ISP2_0                             0x370
-#define MC_LATENCY_ALLOWANCE_SE_0                               0x3e0
-#define MC_LATENCY_ALLOWANCE_ISP2_1                             0x374
-#define MC_LATENCY_ALLOWANCE_DC_0                               0x2e8
-#define MC_LATENCY_ALLOWANCE_VIC_0                              0x394
-#define MC_LATENCY_ALLOWANCE_DCB_1                              0x2f8
-#define MC_LATENCY_ALLOWANCE_NVDEC_0                            0x3d8
-#define MC_LATENCY_ALLOWANCE_DCB_2                              0x2fc
-#define MC_LATENCY_ALLOWANCE_TSEC_0                             0x390
-#define MC_LATENCY_ALLOWANCE_DC_2                               0x2f0
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB                  0x694
-#define MC_LATENCY_ALLOWANCE_PPCS_1                             0x348
-#define MC_LATENCY_ALLOWANCE_XUSB_0                             0x37c
-#define MC_LATENCY_ALLOWANCE_PPCS_0                             0x344
-#define MC_LATENCY_ALLOWANCE_TSECB_0                            0x3f0
-#define MC_LATENCY_ALLOWANCE_AFI_0                              0x2e0
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B                   0x698
-#define MC_LATENCY_ALLOWANCE_DC_1                               0x2ec
-#define MC_LATENCY_ALLOWANCE_APE_0                              0x3dc
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C                   0x6a0
-#define MC_LATENCY_ALLOWANCE_A9AVP_0                            0x3a4
-#define MC_LATENCY_ALLOWANCE_GPU2_0                             0x3e8
-#define MC_LATENCY_ALLOWANCE_DCB_0                              0x2f4
-#define MC_LATENCY_ALLOWANCE_HC_1                               0x314
-#define MC_LATENCY_ALLOWANCE_SDMMC_0                            0x3c0
-#define MC_LATENCY_ALLOWANCE_NVJPG_0                            0x3e4
-#define MC_LATENCY_ALLOWANCE_PTC_0                              0x34c
-#define MC_LATENCY_ALLOWANCE_ETR_0                              0x3ec
-#define MC_LATENCY_ALLOWANCE_MPCORE_0                           0x320
-#define MC_LATENCY_ALLOWANCE_VI2_0                              0x398
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB                  0x69c
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB                  0x6a4
-#define MC_LATENCY_ALLOWANCE_SATA_0                             0x350
-#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A                   0x690
-#define MC_LATENCY_ALLOWANCE_HC_0                               0x310
-#define MC_LATENCY_ALLOWANCE_DC_3                               0x3c8
-#define MC_LATENCY_ALLOWANCE_GPU_0                              0x3ac
-#define MC_LATENCY_ALLOWANCE_SDMMCAB_0                          0x3c4
-#define MC_LATENCY_ALLOWANCE_ISP2B_1                            0x388
-#define MC_LATENCY_ALLOWANCE_NVENC_0                            0x328
-#define MC_LATENCY_ALLOWANCE_HDA_0                              0x318
-#define MC_MIN_LENGTH_APE_0                                     0xb34
-#define MC_MIN_LENGTH_DCB_2                                     0x8a8
-#define MC_MIN_LENGTH_A9AVP_0                                   0x950
-#define MC_MIN_LENGTH_TSEC_0                                    0x93c
-#define MC_MIN_LENGTH_DC_1                                      0x898
-#define MC_MIN_LENGTH_AXIAP_0                                   0x94c
-#define MC_MIN_LENGTH_ISP2B_0                                   0x930
-#define MC_MIN_LENGTH_VI2_0                                     0x944
-#define MC_MIN_LENGTH_DCB_0                                     0x8a0
-#define MC_MIN_LENGTH_DCB_1                                     0x8a4
-#define MC_MIN_LENGTH_PPCS_1                                    0x8f4
-#define MC_MIN_LENGTH_NVJPG_0                                   0xb3c
-#define MC_MIN_LENGTH_HDA_0                                     0x8c4
-#define MC_MIN_LENGTH_NVENC_0                                   0x8d4
-#define MC_MIN_LENGTH_SDMMC_0                                   0xb18
-#define MC_MIN_LENGTH_ISP2B_1                                   0x934
-#define MC_MIN_LENGTH_HC_1                                      0x8c0
-#define MC_MIN_LENGTH_DC_3                                      0xb20
-#define MC_MIN_LENGTH_AVPC_0                                    0x890
-#define MC_MIN_LENGTH_VIC_0                                     0x940
-#define MC_MIN_LENGTH_ISP2_0                                    0x91c
-#define MC_MIN_LENGTH_HC_0                                      0x8bc
-#define MC_MIN_LENGTH_SE_0                                      0xb38
-#define MC_MIN_LENGTH_NVDEC_0                                   0xb30
-#define MC_MIN_LENGTH_SATA_0                                    0x8fc
-#define MC_MIN_LENGTH_DC_0                                      0x894
-#define MC_MIN_LENGTH_XUSB_1                                    0x92c
-#define MC_MIN_LENGTH_DC_2                                      0x89c
-#define MC_MIN_LENGTH_SDMMCAA_0                                 0xb14
-#define MC_MIN_LENGTH_GPU_0                                     0xb04
-#define MC_MIN_LENGTH_ETR_0                                     0xb44
-#define MC_MIN_LENGTH_AFI_0                                     0x88c
-#define MC_MIN_LENGTH_PPCS_0                                    0x8f0
-#define MC_MIN_LENGTH_ISP2_1                                    0x920
-#define MC_MIN_LENGTH_XUSB_0                                    0x928
-#define MC_MIN_LENGTH_MPCORE_0                                  0x8cc
-#define MC_MIN_LENGTH_TSECB_0                                   0xb48
-#define MC_MIN_LENGTH_SDMMCA_0                                  0xb10
-#define MC_MIN_LENGTH_GPU2_0                                    0xb40
-#define MC_MIN_LENGTH_SDMMCAB_0                                 0xb1c
-#define MC_MIN_LENGTH_PTC_0                                     0x8f8
-#define MC_EMEM_ARB_OVERRIDE_1                                  0x968
-#define MC_VIDEO_PROTECT_GPU_OVERRIDE_0                         0x984
-#define MC_VIDEO_PROTECT_GPU_OVERRIDE_1                         0x988
-#define MC_EMEM_ARB_STATS_0                                     0x990
-#define MC_EMEM_ARB_STATS_1                                     0x994
-#define MC_MTS_CARVEOUT_BOM                                     0x9a0
-#define MC_MTS_CARVEOUT_SIZE_MB                                 0x9a4
-#define MC_MTS_CARVEOUT_ADR_HI                                  0x9a8
-#define MC_MTS_CARVEOUT_REG_CTRL                                0x9ac
-#define MC_ERR_MTS_STATUS                                       0x9b0
-#define MC_ERR_MTS_ADR                                          0x9b4
-#define MC_ERR_GENERALIZED_CARVEOUT_STATUS                      0xc00
-#define MC_ERR_GENERALIZED_CARVEOUT_ADR                         0xc04
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2     0xd74
-#define MC_SECURITY_CARVEOUT4_CFG0                              0xcf8
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2                    0xd10
-#define MC_SECURITY_CARVEOUT4_SIZE_128KB                        0xd04
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4                    0xc28
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1     0xc30
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4     0xc8c
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0     0xd1c
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1     0xd70
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0     0xc2c
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4     0xd7c
-#define MC_SECURITY_CARVEOUT3_SIZE_128KB                        0xcb4
-#define MC_SECURITY_CARVEOUT2_CFG0                              0xc58
-#define MC_SECURITY_CARVEOUT1_CFG0                              0xc08
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2     0xc84
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0                    0xc68
-#define MC_SECURITY_CARVEOUT3_BOM                               0xcac
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2                    0xc70
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3     0xd78
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0     0xc7c
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4                    0xd18
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1                    0xcbc
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3     0xc38
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2     0xc34
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2                    0xcc0
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2                    0xd60
-#define MC_SECURITY_CARVEOUT3_CFG0                              0xca8
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0                    0xcb8
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3     0xc88
-#define MC_SECURITY_CARVEOUT2_SIZE_128KB                        0xc64
-#define MC_SECURITY_CARVEOUT5_BOM_HI                            0xd50
-#define MC_SECURITY_CARVEOUT1_SIZE_128KB                        0xc14
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3                    0xd14
-#define MC_SECURITY_CARVEOUT1_BOM                               0xc0c
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4     0xd2c
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4                    0xd68
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4                    0xcc8
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0                    0xd58
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2     0xd24
-#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3                    0xcc4
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4                    0xc78
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1                    0xc1c
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0                    0xc18
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3     0xd28
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1                    0xd5c
-#define MC_SECURITY_CARVEOUT3_BOM_HI                            0xcb0
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3     0xcd8
-#define MC_SECURITY_CARVEOUT2_BOM_HI                            0xc60
-#define MC_SECURITY_CARVEOUT4_BOM_HI                            0xd00
-#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3                    0xd64
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4     0xcdc
-#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1     0xc80
-#define MC_SECURITY_CARVEOUT5_SIZE_128KB                        0xd54
-#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1     0xd20
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2     0xcd4
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1                    0xd0c
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3                    0xc74
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0     0xccc
-#define MC_SECURITY_CARVEOUT4_BOM                               0xcfc
-#define MC_SECURITY_CARVEOUT5_CFG0                              0xd48
-#define MC_SECURITY_CARVEOUT2_BOM                               0xc5c
-#define MC_SECURITY_CARVEOUT5_BOM                               0xd4c
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3                    0xc24
-#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0     0xd6c
-#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1     0xcd0
-#define MC_SECURITY_CARVEOUT1_BOM_HI                            0xc10
-#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2                    0xc20
-#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4     0xc3c
-#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1                    0xc6c
-#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0                    0xd08
-#define MC_ERR_APB_ASID_UPDATE_STATUS                           0x9d0
-#define MC_DA_CONFIG0                                           0x9dc
-#define MC_UNTRANSLATED_REGION_CHECK                            0x948
-
-/* Memory Controller clients */
-#define CLIENT_ACCESS_NUM_CLIENTS   32
-typedef enum {
-    /* _ACCESS0 */
-    CSR_PTCR = (0 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0A = (1 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0AB = (2 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0B = (3 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0BB = (4 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0C = (5 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAY0CB = (6 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_AFIR = (14 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_AVPCARM7R = (15 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAYHC = (16 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_DISPLAYHCB = (17 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_HDAR = (21 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_HOST1XDMAR = (22 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_HOST1XR = (23 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_NVENCSRD = (28 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_PPCSAHBDMAR = (29 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_PPCSAHBSLVR = (30 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    CSR_SATAR = (31 - (CLIENT_ACCESS_NUM_CLIENTS * 0)),
-    
-    /* _ACCESS1 */
-    CSR_VDEBSEVR = (34 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSR_VDEMBER = (35 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSR_VDEMCER = (36 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSR_VDETPER = (37 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSR_MPCORELPR = (38 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSR_MPCORER = (39 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_NVENCSWR = (43 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_AFIW = (49 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_AVPCARM7W = (50 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_HDAW = (53 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_HOST1XW = (54 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_MPCORELPW = (56 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_MPCOREW = (57 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_PPCSAHBDMAW = (59 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_PPCSAHBSLVW = (60 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_SATAW = (61 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_VDEBSEVW = (62 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    CSW_VDEDBGW = (63 - (CLIENT_ACCESS_NUM_CLIENTS * 1)),
-    
-    /* _ACCESS2 */
-    CSW_VDEMBEW = (64 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_VDETPMW = (65 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_ISPRA = (68 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_ISPWA = (70 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_ISPWB = (71 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_XUSB_HOSTR = (74 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_XUSB_HOSTW = (75 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_XUSB_DEVR = (76 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_XUSB_DEVW = (77 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_ISPRAB = (78 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_ISPWAB = (80 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_ISPWBB = (81 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_TSECSRD = (84 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_TSECSWR = (85 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_A9AVPSCR = (86 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_A9AVPSCW = (87 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_GPUSRD = (88 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSW_GPUSWR = (89 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    CSR_DISPLAYT = (90 - (CLIENT_ACCESS_NUM_CLIENTS * 2)),
-    
-    /* _ACCESS3 */
-    CSR_SDMMCRA = (96 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_SDMMCRAA = (97 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_SDMMCR = (98 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_SDMMCRAB = (99 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_SDMMCWA = (100 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_SDMMCWAA = (101 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_SDMMCW = (102 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_SDMMCWAB = (103 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_VICSRD = (108 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_VICSWR = (109 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_VIW = (114 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_DISPLAYD = (115 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_NVDECSRD = (120 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_NVDECSWR = (121 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_APER = (122 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_APEW = (123 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSR_NVJPGSRD = (126 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    CSW_NVJPGSWR = (127 - (CLIENT_ACCESS_NUM_CLIENTS * 3)),
-    
-    /* _ACCESS4 */
-    CSR_SESRD = (128 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSW_SESWR = (129 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSR_AXIAPR = (130 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSW_AXIAPW = (131 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSR_ETRR = (132 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSW_ETRW = (133 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSR_TSECSRDB = (134 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSW_TSECSWRB = (135 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSR_GPUSRD2 = (136 - (CLIENT_ACCESS_NUM_CLIENTS * 4)),
-    CSW_GPUSWR2 = (137 - (CLIENT_ACCESS_NUM_CLIENTS * 4))
-} McClient;
-
-void mc_config_tsec_carveout(uint32_t bom, uint32_t size1mb, bool lock);
-void mc_config_carveout();
-void mc_config_carveout_finalize();
-void mc_enable_ahb_redirect();
-void mc_disable_ahb_redirect();
-void mc_enable();
-
-#endif

fusee/fusee-mtc/src/mtc.h

@@ -1,759 +0,0 @@
-/*
- * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
- * Copyright (c) 2018 CTCaer  <ctcaer@gmail.com>
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef FUSEE_MTC_H_
-#define FUSEE_MTC_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "emc.h"
-#include "mc.h"
-
-#define MTC_TABLES_MAX_ENTRIES      10
-#define MAX_PLL_CFGS                14
-
-#define DVFS_FGCG_HIGH_SPEED_THRESHOLD              1000
-#define IOBRICK_DCC_THRESHOLD                   2400
-#define DVFS_FGCG_MID_SPEED_THRESHOLD               600
-
-#define TEGRA21_MAX_TABLE_ID_LEN                50
-#define TEGRA_EMC_ISO_USE_FREQ_MAX_NUM              12
-#define PLL_C_DIRECT_FLOOR                  333500000
-#define EMC_STATUS_UPDATE_TIMEOUT               1000
-#define TEGRA_EMC_DEFAULT_CLK_LATENCY_US    2000
-
-#define TEGRA_EMC_MODE_REG_17                   0x00110000
-#define TEGRA_EMC_MRW_DEV_SHIFT                 30
-#define TEGRA_EMC_MRW_DEV1                  2
-#define TEGRA_EMC_MRW_DEV2                  1
-
-#define EMC_CLK_EMC_2X_CLK_SRC_SHIFT                29
-#define EMC_CLK_EMC_2X_CLK_SRC_MASK             \
-    (0x7 << EMC_CLK_EMC_2X_CLK_SRC_SHIFT)
-#define EMC_CLK_EMC_2X_CLK_DIVISOR_SHIFT            0
-#define EMC_CLK_EMC_2X_CLK_DIVISOR_MASK             \
-    (0xff << EMC_CLK_EMC_2X_CLK_DIVISOR_SHIFT)
-
-enum {
-    REG_MC,
-    REG_EMC,
-    REG_EMC0,
-    REG_EMC1,
-};
-
-#define BURST_REGS_PER_CH_LIST                      \
-{                                   \
-    DEFINE_REG(REG_EMC0, EMC_MRW10),                \
-    DEFINE_REG(REG_EMC1, EMC_MRW10),                \
-    DEFINE_REG(REG_EMC0, EMC_MRW11),                \
-    DEFINE_REG(REG_EMC1, EMC_MRW11),                \
-    DEFINE_REG(REG_EMC0, EMC_MRW12),                \
-    DEFINE_REG(REG_EMC1, EMC_MRW12),                \
-    DEFINE_REG(REG_EMC0, EMC_MRW13),                \
-    DEFINE_REG(REG_EMC1, EMC_MRW13),                \
-}
-
-#define BURST_REGS_LIST                         \
-{                                   \
-    DEFINE_REG(REG_EMC, EMC_RC),                    \
-    DEFINE_REG(REG_EMC, EMC_RFC),                   \
-    DEFINE_REG(REG_EMC, EMC_RFCPB),                 \
-    DEFINE_REG(REG_EMC, EMC_REFCTRL2),              \
-    DEFINE_REG(REG_EMC, EMC_RFC_SLR),               \
-    DEFINE_REG(REG_EMC, EMC_RAS),                   \
-    DEFINE_REG(REG_EMC, EMC_RP),                    \
-    DEFINE_REG(REG_EMC, EMC_R2W),                   \
-    DEFINE_REG(REG_EMC, EMC_W2R),                   \
-    DEFINE_REG(REG_EMC, EMC_R2P),                   \
-    DEFINE_REG(REG_EMC, EMC_W2P),                   \
-    DEFINE_REG(REG_EMC, EMC_R2R),                   \
-    DEFINE_REG(REG_EMC, EMC_TPPD),                  \
-    DEFINE_REG(REG_EMC, EMC_CCDMW),                 \
-    DEFINE_REG(REG_EMC, EMC_RD_RCD),                \
-    DEFINE_REG(REG_EMC, EMC_WR_RCD),                \
-    DEFINE_REG(REG_EMC, EMC_RRD),                   \
-    DEFINE_REG(REG_EMC, EMC_REXT),                  \
-    DEFINE_REG(REG_EMC, EMC_WEXT),                  \
-    DEFINE_REG(REG_EMC, EMC_WDV_CHK),               \
-    DEFINE_REG(REG_EMC, EMC_WDV),                   \
-    DEFINE_REG(REG_EMC, EMC_WSV),                   \
-    DEFINE_REG(REG_EMC, EMC_WEV),                   \
-    DEFINE_REG(REG_EMC, EMC_WDV_MASK),              \
-    DEFINE_REG(REG_EMC, EMC_WS_DURATION),               \
-    DEFINE_REG(REG_EMC, EMC_WE_DURATION),               \
-    DEFINE_REG(REG_EMC, EMC_QUSE),                  \
-    DEFINE_REG(REG_EMC, EMC_QUSE_WIDTH),                \
-    DEFINE_REG(REG_EMC, EMC_IBDLY),                 \
-    DEFINE_REG(REG_EMC, EMC_OBDLY),                 \
-    DEFINE_REG(REG_EMC, EMC_EINPUT),                \
-    DEFINE_REG(REG_EMC, EMC_MRW6),                  \
-    DEFINE_REG(REG_EMC, EMC_EINPUT_DURATION),           \
-    DEFINE_REG(REG_EMC, EMC_PUTERM_EXTRA),              \
-    DEFINE_REG(REG_EMC, EMC_PUTERM_WIDTH),              \
-    DEFINE_REG(REG_EMC, EMC_QRST),                  \
-    DEFINE_REG(REG_EMC, EMC_QSAFE),                 \
-    DEFINE_REG(REG_EMC, EMC_RDV),                   \
-    DEFINE_REG(REG_EMC, EMC_RDV_MASK),              \
-    DEFINE_REG(REG_EMC, EMC_RDV_EARLY),             \
-    DEFINE_REG(REG_EMC, EMC_RDV_EARLY_MASK),            \
-    DEFINE_REG(REG_EMC, EMC_REFRESH),               \
-    DEFINE_REG(REG_EMC, EMC_BURST_REFRESH_NUM),         \
-    DEFINE_REG(REG_EMC, EMC_PRE_REFRESH_REQ_CNT),           \
-    DEFINE_REG(REG_EMC, EMC_PDEX2WR),               \
-    DEFINE_REG(REG_EMC, EMC_PDEX2RD),               \
-    DEFINE_REG(REG_EMC, EMC_PCHG2PDEN),             \
-    DEFINE_REG(REG_EMC, EMC_ACT2PDEN),              \
-    DEFINE_REG(REG_EMC, EMC_AR2PDEN),               \
-    DEFINE_REG(REG_EMC, EMC_RW2PDEN),               \
-    DEFINE_REG(REG_EMC, EMC_CKE2PDEN),              \
-    DEFINE_REG(REG_EMC, EMC_PDEX2CKE),              \
-    DEFINE_REG(REG_EMC, EMC_PDEX2MRR),              \
-    DEFINE_REG(REG_EMC, EMC_TXSR),                  \
-    DEFINE_REG(REG_EMC, EMC_TXSRDLL),               \
-    DEFINE_REG(REG_EMC, EMC_TCKE),                  \
-    DEFINE_REG(REG_EMC, EMC_TCKESR),                \
-    DEFINE_REG(REG_EMC, EMC_TPD),                   \
-    DEFINE_REG(REG_EMC, EMC_TFAW),                  \
-    DEFINE_REG(REG_EMC, EMC_TRPAB),                 \
-    DEFINE_REG(REG_EMC, EMC_TCLKSTABLE),                \
-    DEFINE_REG(REG_EMC, EMC_TCLKSTOP),              \
-    DEFINE_REG(REG_EMC, EMC_MRW7),                  \
-    DEFINE_REG(REG_EMC, EMC_TREFBW),                \
-    DEFINE_REG(REG_EMC, EMC_ODT_WRITE),             \
-    DEFINE_REG(REG_EMC, EMC_FBIO_CFG5),             \
-    DEFINE_REG(REG_EMC, EMC_FBIO_CFG7),             \
-    DEFINE_REG(REG_EMC, EMC_CFG_DIG_DLL),               \
-    DEFINE_REG(REG_EMC, EMC_CFG_DIG_DLL_PERIOD),            \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_RXRT),            \
-    DEFINE_REG(REG_EMC, EMC_CFG_PIPE_1),                \
-    DEFINE_REG(REG_EMC, EMC_CFG_PIPE_2),                \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK0_4),      \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK0_5),      \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK1_4),      \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK1_5),      \
-    DEFINE_REG(REG_EMC, EMC_MRW8),                  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4),    \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5),    \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0),   \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1),   \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2),   \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3),   \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4),   \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5),   \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0),   \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1),   \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2),   \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3),   \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4),   \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5),   \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_LONG_CMD_0),        \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_LONG_CMD_1),        \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_LONG_CMD_2),        \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_LONG_CMD_3),        \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_LONG_CMD_4),        \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_SHORT_CMD_0),       \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_SHORT_CMD_1),       \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_SHORT_CMD_2),       \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3),  \
-    DEFINE_REG(REG_EMC, EMC_TXDSRVTTGEN),               \
-    DEFINE_REG(REG_EMC, EMC_FDPD_CTRL_DQ),              \
-    DEFINE_REG(REG_EMC, EMC_FDPD_CTRL_CMD),             \
-    DEFINE_REG(REG_EMC, EMC_FBIO_SPARE),                \
-    DEFINE_REG(REG_EMC, EMC_ZCAL_INTERVAL),             \
-    DEFINE_REG(REG_EMC, EMC_ZCAL_WAIT_CNT),             \
-    DEFINE_REG(REG_EMC, EMC_MRS_WAIT_CNT),              \
-    DEFINE_REG(REG_EMC, EMC_MRS_WAIT_CNT2),             \
-    DEFINE_REG(REG_EMC, EMC_AUTO_CAL_CHANNEL),          \
-    DEFINE_REG(REG_EMC, EMC_DLL_CFG_0),             \
-    DEFINE_REG(REG_EMC, EMC_DLL_CFG_1),             \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_AUTOCAL_CFG_COMMON),     \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_ZCTRL),              \
-    DEFINE_REG(REG_EMC, EMC_CFG),                   \
-    DEFINE_REG(REG_EMC, EMC_CFG_PIPE),              \
-    DEFINE_REG(REG_EMC, EMC_DYN_SELF_REF_CONTROL),          \
-    DEFINE_REG(REG_EMC, EMC_QPOP),                  \
-    DEFINE_REG(REG_EMC, EMC_DQS_BRLSHFT_0),             \
-    DEFINE_REG(REG_EMC, EMC_DQS_BRLSHFT_1),             \
-    DEFINE_REG(REG_EMC, EMC_CMD_BRLSHFT_2),             \
-    DEFINE_REG(REG_EMC, EMC_CMD_BRLSHFT_3),             \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_PAD_CFG_CTRL),           \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_DATA_PAD_RX_CTRL),       \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_CMD_PAD_RX_CTRL),        \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_DATA_RX_TERM_MODE),      \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_CMD_RX_TERM_MODE),       \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_CMD_PAD_TX_CTRL),        \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_DATA_PAD_TX_CTRL),       \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_COMMON_PAD_TX_CTRL),     \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_VTTGEN_CTRL_0),          \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_VTTGEN_CTRL_1),          \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_VTTGEN_CTRL_2),          \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_BRICK_CTRL_RFU1),        \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_CMD_BRICK_CTRL_FDPD),        \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_BRICK_CTRL_RFU2),        \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_DATA_BRICK_CTRL_FDPD),       \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_BG_BIAS_CTRL_0),         \
-    DEFINE_REG(REG_EMC, EMC_CFG_3),                 \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_TX_PWRD_0),          \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_TX_PWRD_1),          \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_TX_PWRD_2),          \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_TX_PWRD_3),          \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_TX_PWRD_4),          \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_TX_PWRD_5),          \
-    DEFINE_REG(REG_EMC, EMC_CONFIG_SAMPLE_DELAY),           \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_TX_SEL_CLK_SRC_0),       \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_TX_SEL_CLK_SRC_1),       \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_TX_SEL_CLK_SRC_2),       \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_TX_SEL_CLK_SRC_3),       \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_TX_SEL_CLK_SRC_4),       \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_TX_SEL_CLK_SRC_5),       \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_BYPASS),            \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_PWRD_0),            \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_PWRD_1),            \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_PWRD_2),            \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_CMD_CTRL_0),         \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_CMD_CTRL_1),         \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_CMD_CTRL_2),         \
-    DEFINE_REG(REG_EMC, EMC_TR_TIMING_0),               \
-    DEFINE_REG(REG_EMC, EMC_TR_DVFS),               \
-    DEFINE_REG(REG_EMC, EMC_TR_CTRL_1),             \
-    DEFINE_REG(REG_EMC, EMC_TR_RDV),                \
-    DEFINE_REG(REG_EMC, EMC_TR_QPOP),               \
-    DEFINE_REG(REG_EMC, EMC_TR_RDV_MASK),               \
-    DEFINE_REG(REG_EMC, EMC_MRW14),                 \
-    DEFINE_REG(REG_EMC, EMC_TR_QSAFE),              \
-    DEFINE_REG(REG_EMC, EMC_TR_QRST),               \
-    DEFINE_REG(REG_EMC, EMC_TRAINING_CTRL),             \
-    DEFINE_REG(REG_EMC, EMC_TRAINING_SETTLE),           \
-    DEFINE_REG(REG_EMC, EMC_TRAINING_VREF_SETTLE),          \
-    DEFINE_REG(REG_EMC, EMC_TRAINING_CA_FINE_CTRL),         \
-    DEFINE_REG(REG_EMC, EMC_TRAINING_CA_CTRL_MISC),         \
-    DEFINE_REG(REG_EMC, EMC_TRAINING_CA_CTRL_MISC1),        \
-    DEFINE_REG(REG_EMC, EMC_TRAINING_CA_VREF_CTRL),         \
-    DEFINE_REG(REG_EMC, EMC_TRAINING_QUSE_CORS_CTRL),       \
-    DEFINE_REG(REG_EMC, EMC_TRAINING_QUSE_FINE_CTRL),       \
-    DEFINE_REG(REG_EMC, EMC_TRAINING_QUSE_CTRL_MISC),       \
-    DEFINE_REG(REG_EMC, EMC_TRAINING_QUSE_VREF_CTRL),       \
-    DEFINE_REG(REG_EMC, EMC_TRAINING_READ_FINE_CTRL),       \
-    DEFINE_REG(REG_EMC, EMC_TRAINING_READ_CTRL_MISC),       \
-    DEFINE_REG(REG_EMC, EMC_TRAINING_READ_VREF_CTRL),       \
-    DEFINE_REG(REG_EMC, EMC_TRAINING_WRITE_FINE_CTRL),      \
-    DEFINE_REG(REG_EMC, EMC_TRAINING_WRITE_CTRL_MISC),      \
-    DEFINE_REG(REG_EMC, EMC_TRAINING_WRITE_VREF_CTRL),      \
-    DEFINE_REG(REG_EMC, EMC_TRAINING_MPC),              \
-    DEFINE_REG(REG_EMC, EMC_MRW15),                 \
-}
-
-#define TRIM_REGS_PER_CH_LIST                       \
-{                                   \
-    DEFINE_REG(REG_EMC0, EMC_CMD_BRLSHFT_0),            \
-    DEFINE_REG(REG_EMC1, EMC_CMD_BRLSHFT_1),            \
-    DEFINE_REG(REG_EMC0, EMC_DATA_BRLSHFT_0),           \
-    DEFINE_REG(REG_EMC1, EMC_DATA_BRLSHFT_0),           \
-    DEFINE_REG(REG_EMC0, EMC_DATA_BRLSHFT_1),           \
-    DEFINE_REG(REG_EMC1, EMC_DATA_BRLSHFT_1),           \
-    DEFINE_REG(REG_EMC0, EMC_QUSE_BRLSHFT_0),           \
-    DEFINE_REG(REG_EMC1, EMC_QUSE_BRLSHFT_1),           \
-    DEFINE_REG(REG_EMC0, EMC_QUSE_BRLSHFT_2),           \
-    DEFINE_REG(REG_EMC1, EMC_QUSE_BRLSHFT_3),           \
-}
-
-#define TRIM_REGS_LIST                          \
-{                                   \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0),   \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1),   \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2),   \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3),   \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0),   \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1),   \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2),   \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3),   \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_VREF_DQS_0),          \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_VREF_DQS_1),          \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_VREF_DQ_0),           \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_IB_VREF_DQ_1),           \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0),    \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1),    \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2),    \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3),    \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4),    \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5),    \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0),    \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1),    \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2),    \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3),    \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2),  \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2), \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK0_0),      \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK0_1),      \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK0_2),      \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK0_3),      \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK1_0),      \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK1_1),      \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK1_2),      \
-    DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK1_3),      \
-}
-
-#define VREF_REGS_PER_CH_LIST                       \
-{                                   \
-    DEFINE_REG(REG_EMC0, EMC_TRAINING_OPT_DQS_IB_VREF_RANK0),   \
-    DEFINE_REG(REG_EMC1, EMC_TRAINING_OPT_DQS_IB_VREF_RANK0),   \
-    DEFINE_REG(REG_EMC0, EMC_TRAINING_OPT_DQS_IB_VREF_RANK1),   \
-    DEFINE_REG(REG_EMC1, EMC_TRAINING_OPT_DQS_IB_VREF_RANK1),   \
-}
-
-#define TRAINING_MOD_REGS_PER_CH_LIST                       \
-{                                   \
-    DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_IB_BYTE0),          \
-    DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_IB_BYTE0),          \
-    DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_IB_BYTE1),          \
-    DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_IB_BYTE1),          \
-    DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_IB_BYTE2),          \
-    DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_IB_BYTE2),          \
-    DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_IB_BYTE3),          \
-    DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_IB_BYTE3),          \
-    DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_IB_MISC),           \
-    DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_IB_MISC),           \
-    DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_OB_BYTE0),          \
-    DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_OB_BYTE0),          \
-    DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_OB_BYTE1),          \
-    DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_OB_BYTE1),          \
-    DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_OB_BYTE2),          \
-    DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_OB_BYTE2),          \
-    DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_OB_BYTE3),          \
-    DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_OB_BYTE3),          \
-    DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_OB_MISC),           \
-    DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_OB_MISC),           \
-}
-
-#define BURST_MC_REGS_LIST                          \
-{                                   \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_CFG),    \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_OUTSTANDING_REQ),    \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_REFPB_HP_CTRL),  \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_REFPB_BANK_CTRL),    \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_RCD), \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_RP),  \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_RC),  \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_RAS), \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_FAW), \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_RRD), \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_RAP2PRE), \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_WAP2PRE), \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_R2R), \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_W2W), \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_R2W), \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_CCDMW),   \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_W2R), \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_RFCPB),   \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_DA_TURNS),   \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_DA_COVERS),  \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_MISC0),  \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_MISC1),  \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_MISC2),  \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_RING1_THROTTLE), \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_CTRL), \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0),   \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1),   \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2),   \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3),   \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4),   \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5),   \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6),   \
-    DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7),   \
-}
-
-#define BURST_UP_DOWN_REGS_LIST                         \
-{                                   \
-    DEFINE_REG(REG_MC, MC_MLL_MPCORER_PTSA_RATE),   \
-    DEFINE_REG(REG_MC, MC_FTOP_PTSA_RATE),  \
-    DEFINE_REG(REG_MC, MC_PTSA_GRANT_DECREMENT),    \
-    DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_XUSB_0),    \
-    DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_XUSB_1),    \
-    DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_TSEC_0),    \
-    DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_SDMMCA_0),  \
-    DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_SDMMCAA_0), \
-    DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_SDMMC_0),   \
-    DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_SDMMCAB_0), \
-    DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_PPCS_0),    \
-    DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_PPCS_1),    \
-    DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_MPCORE_0),  \
-    DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_HC_0),  \
-    DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_HC_1),  \
-    DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_AVPC_0),    \
-    DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_GPU_0), \
-    DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_GPU2_0),    \
-    DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_NVENC_0),   \
-    DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_NVDEC_0),   \
-    DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_VIC_0), \
-    DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_VI2_0), \
-    DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_ISP2_0),    \
-    DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_ISP2_1),    \
-}
-
-#define DEFINE_REG(type, reg)   reg##_INDEX
-enum BURST_REGS_LIST;
-enum TRIM_REGS_LIST;
-enum BURST_MC_REGS_LIST;
-enum BURST_UP_DOWN_REGS_LIST;
-#undef DEFINE_REG
-
-#define DEFINE_REG(type, reg)   type##_##reg##_INDEX
-enum BURST_REGS_PER_CH_LIST;
-enum TRIM_REGS_PER_CH_LIST;
-enum VREF_REGS_PER_CH_LIST;
-enum TRAINING_MOD_REGS_PER_CH_LIST;
-#undef DEFINE_REG
-
-typedef struct {
-    uint32_t rev;
-    char dvfs_ver[60];
-    uint32_t rate;
-    uint32_t min_volt;
-    uint32_t gpu_min_volt;
-    char clock_src[32];
-    uint32_t clk_src_emc;
-    uint32_t needs_training;
-    uint32_t training_pattern;
-    uint32_t trained;
-
-    uint32_t periodic_training;
-    uint32_t trained_dram_clktree_c0d0u0;
-    uint32_t trained_dram_clktree_c0d0u1;
-    uint32_t trained_dram_clktree_c0d1u0;
-    uint32_t trained_dram_clktree_c0d1u1;
-    uint32_t trained_dram_clktree_c1d0u0;
-    uint32_t trained_dram_clktree_c1d0u1;
-    uint32_t trained_dram_clktree_c1d1u0;
-    uint32_t trained_dram_clktree_c1d1u1;
-    uint32_t current_dram_clktree_c0d0u0;
-    uint32_t current_dram_clktree_c0d0u1;
-    uint32_t current_dram_clktree_c0d1u0;
-    uint32_t current_dram_clktree_c0d1u1;
-    uint32_t current_dram_clktree_c1d0u0;
-    uint32_t current_dram_clktree_c1d0u1;
-    uint32_t current_dram_clktree_c1d1u0;
-    uint32_t current_dram_clktree_c1d1u1;
-    uint32_t run_clocks;
-    uint32_t tree_margin;
-
-    uint32_t num_burst;
-    uint32_t num_burst_per_ch;
-    uint32_t num_trim;
-    uint32_t num_trim_per_ch;
-    uint32_t num_mc_regs;
-    uint32_t num_up_down;
-    uint32_t vref_num;
-    uint32_t training_mod_num;
-    uint32_t dram_timing_num;
-
-    uint32_t ptfv_list[12];
-
-    uint32_t burst_regs[221];
-    uint32_t burst_reg_per_ch[8];
-    uint32_t shadow_regs_ca_train[221];
-    uint32_t shadow_regs_quse_train[221];
-    uint32_t shadow_regs_rdwr_train[221];
-
-    uint32_t trim_regs[138];
-    uint32_t trim_perch_regs[10];
-
-    uint32_t vref_perch_regs[4];
-
-    uint32_t dram_timings[5];
-    uint32_t training_mod_regs[20];
-    uint32_t save_restore_mod_regs[12];
-    uint32_t burst_mc_regs[33];
-    uint32_t la_scale_regs[24];
-
-    uint32_t min_mrs_wait;
-    uint32_t emc_mrw;
-    uint32_t emc_mrw2;
-    uint32_t emc_mrw3;
-    uint32_t emc_mrw4;
-    uint32_t emc_mrw9;
-    uint32_t emc_mrs;
-    uint32_t emc_emrs;
-    uint32_t emc_emrs2;
-    uint32_t emc_auto_cal_config;
-    uint32_t emc_auto_cal_config2;
-    uint32_t emc_auto_cal_config3;
-    uint32_t emc_auto_cal_config4;
-    uint32_t emc_auto_cal_config5;
-    uint32_t emc_auto_cal_config6;
-    uint32_t emc_auto_cal_config7;
-    uint32_t emc_auto_cal_config8;
-    uint32_t emc_cfg_2;
-    uint32_t emc_sel_dpd_ctrl;
-    uint32_t emc_fdpd_ctrl_cmd_no_ramp;
-    uint32_t dll_clk_src;
-    uint32_t clk_out_enb_x_0_clk_enb_emc_dll;
-    uint32_t latency;
-} tegra_emc_timing_t;
-
-typedef struct {
-    uint32_t osc_freq;
-    uint32_t out_freq;
-    uint32_t feedback_div;
-    uint32_t input_div;
-    uint32_t post_div;
-} pll_cfg_t;
-
-typedef enum {
-    OP_SWITCH = 0,
-    OP_TRAIN = 1,
-    OP_TRAIN_SWITCH = 2
-} TrainMode;
-
-typedef enum {
-    TEGRA_EMC_SRC_PLLM,
-    TEGRA_EMC_SRC_PLLC,
-    TEGRA_EMC_SRC_PLLP,
-    TEGRA_EMC_SRC_CLKM,
-    TEGRA_EMC_SRC_PLLM_UD,
-    TEGRA_EMC_SRC_PLLMB_UD,
-    TEGRA_EMC_SRC_PLLMB,
-    TEGRA_EMC_SRC_PLLP_UD,
-    TEGRA_EMC_SRC_COUNT,
-} EmcSource;
-
-enum {
-    DRAM_TYPE_DDR3   = 0,
-    DRAM_TYPE_LPDDR4 = 1,
-    DRAM_TYPE_LPDDR2 = 2,
-    DRAM_TYPE_DDR2 = 3,
-};
-
-enum {
-    DLL_CHANGE_NONE = 0,
-    DLL_CHANGE_ON,
-    DLL_CHANGE_OFF,
-};
-
-enum {
-    DLL_OFF,
-    DLL_ON
-};
-
-enum {
-    AUTO_PD = 0,
-    MAN_SR  = 2
-};
-
-enum {
-    ASSEMBLY = 0,
-    ACTIVE
-};
-
-enum {
-    T_RP = 0,
-    T_FC_LPDDR4,
-    T_RFC,
-    T_PDEX,
-    RL
-};
-
-enum {
-    ONE_RANK = 1,
-    TWO_RANK = 2
-};
-
-enum {
-    SINGLE_CHANNEL = 0,
-    DUAL_CHANNEL
-};
-
-enum {
-    DRAM_DEV_SEL_ALL = 0,
-    DRAM_DEV_SEL_0   = (2 << 30),
-    DRAM_DEV_SEL_1   = (1 << 30),
-};
-
-enum {
-    EMC_CFG5_QUSE_MODE_NORMAL = 0,
-    EMC_CFG5_QUSE_MODE_ALWAYS_ON,
-    EMC_CFG5_QUSE_MODE_INTERNAL_LPBK,
-    EMC_CFG5_QUSE_MODE_PULSE_INTERN,
-    EMC_CFG5_QUSE_MODE_PULSE_EXTERN,
-    EMC_CFG5_QUSE_MODE_DIRECT_QUSE,
-};
-
-enum {
-    DVFS_SEQUENCE = 1,
-    WRITE_TRAINING_SEQUENCE = 2,
-    PERIODIC_TRAINING_SEQUENCE = 3,
-    DVFS_PT1 = 10,
-    DVFS_UPDATE = 11,
-    TRAINING_PT1 = 12,
-    TRAINING_UPDATE = 13,
-    PERIODIC_TRAINING_UPDATE = 14
-};
-
-enum {
-    TEGRA_DRAM_OVER_TEMP_NONE = 0,
-    TEGRA_DRAM_OVER_TEMP_REFRESH_X2,
-    TEGRA_DRAM_OVER_TEMP_REFRESH_X4,
-    TEGRA_DRAM_OVER_TEMP_THROTTLE,
-    TEGRA_DRAM_OVER_TEMP_MAX,
-};
-
-/* Train all possible DRAM sequences. */
-void train_dram(void);
-
-#endif

fusee/fusee-mtc/src/pmc.h

@@ -1,713 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_PMC_H
-#define FUSEE_PMC_H
-
-#include <stdint.h>
-
-#define PMC_BASE 0x7000E400
-#define MAKE_PMC_REG(n) MAKE_REG32(PMC_BASE + n)
-
-#define PMC_CONTROL_SDMMC1      (1 << 12)
-#define PMC_CONTROL_SDMMC3      (1 << 13)
-#define PMC_CONTROL_SDMMC4      (1 << 14)
-
-#define APBDEV_PMC_CONTROL MAKE_PMC_REG(0x00)
-#define APBDEV_PM_0 MAKE_PMC_REG(0x14)
-#define APBDEV_PMC_DPD_ENABLE_0 MAKE_PMC_REG(0x24)
-#define APBDEV_PMC_PWRGATE_TOGGLE_0 MAKE_PMC_REG(0x30)
-#define APBDEV_PMC_PWRGATE_STATUS_0 MAKE_PMC_REG(0x38)
-#define APBDEV_PMC_NO_IOPOWER_0 MAKE_PMC_REG(0x44)
-#define APBDEV_PMC_SCRATCH0_0 MAKE_PMC_REG(0x50)
-#define APBDEV_PMC_SCRATCH1_0 MAKE_PMC_REG(0x54)
-#define APBDEV_PMC_SCRATCH20_0 MAKE_PMC_REG(0xA0)
-#define APBDEV_PMC_PWR_DET_VAL_0 MAKE_PMC_REG(0xE4)
-#define APBDEV_PMC_DDR_PWR_0 MAKE_PMC_REG(0xE8)
-#define APBDEV_PMC_CRYPTO_OP_0 MAKE_PMC_REG(0xF4)
-#define APBDEV_PMC_WAKE2_STATUS_0 MAKE_PMC_REG(0x168)
-#define APBDEV_PMC_OSC_EDPD_OVER_0 MAKE_PMC_REG(0x1A4)
-#define APBDEV_PMC_RST_STATUS_0 MAKE_PMC_REG(0x1B4)
-#define APBDEV_PMC_IO_DPD_REQ_0 MAKE_PMC_REG(0x1B8)
-#define APBDEV_PMC_IO_DPD2_REQ_0 MAKE_PMC_REG(0x1C0)
-#define APBDEV_PMC_VDDP_SEL_0 MAKE_PMC_REG(0x1CC)
-#define APBDEV_PMC_SCRATCH49_0 MAKE_PMC_REG(0x244)
-#define APBDEV_PMC_TSC_MULT_0 MAKE_PMC_REG(0x2B4)
-#define APBDEV_PMC_REG_SHORT_0 MAKE_PMC_REG(0x2CC)
-#define APBDEV_PMC_WEAK_BIAS_0 MAKE_PMC_REG(0x2C8)
-#define APBDEV_PMC_SECURE_SCRATCH21_0 MAKE_PMC_REG(0x334)
-#define APBDEV_PMC_SECURE_SCRATCH32_0 MAKE_PMC_REG(0x360)
-#define APBDEV_PMC_SECURE_SCRATCH49_0 MAKE_PMC_REG(0x3A4)
-#define APBDEV_PMC_CNTRL2_0 MAKE_PMC_REG(0x440)
-#define APBDEV_PMC_IO_DPD4_REQ_0 MAKE_PMC_REG(0x464)
-#define APBDEV_PMC_UTMIP_PAD_CFG1_0 MAKE_PMC_REG(0x4C4)
-#define APBDEV_PMC_UTMIP_PAD_CFG3_0 MAKE_PMC_REG(0x4CC)
-#define APBDEV_PMC_DDR_CNTRL_0 MAKE_PMC_REG(0x4E4)
-#define APBDEV_PMC_SCRATCH43_0 MAKE_PMC_REG(0x22C)
-#define APBDEV_PMC_SCRATCH188_0 MAKE_PMC_REG(0x810)
-#define APBDEV_PMC_SCRATCH190_0 MAKE_PMC_REG(0x818)
-#define APBDEV_PMC_SCRATCH200_0 MAKE_PMC_REG(0x840)
-
-#define APBDEV_PMC_SCRATCH45_0 MAKE_PMC_REG(0x234)
-#define APBDEV_PMC_SCRATCH46_0 MAKE_PMC_REG(0x238)
-#define APBDEV_PMC_SCRATCH33_0 MAKE_PMC_REG(0x120)
-#define APBDEV_PMC_SCRATCH40_0 MAKE_PMC_REG(0x13C)
-
-/* Power Management Controller (APBDEV_PMC_) regs */
-typedef struct {
-    uint32_t cntrl;                             /* _CNTRL_0,                        0x00 */
-    uint32_t sec_disable;                       /* _SEC_DISABLE_0,                  0x04 */
-    uint32_t pmc_swrst;                         /* _PMC_SWRST_0,                    0x08 */
-    uint32_t wake_mask;                         /* _WAKE_MASK_0,                    0x0c */
-    uint32_t wake_lvl;                          /* _WAKE_LVL_0,                     0x10 */
-    uint32_t wake_status;                       /* _WAKE_STATUS_0,                  0x14 */
-    uint32_t sw_wake_status;                    /* _SW_WAKE_STATUS_0,               0x18 */
-    uint32_t dpd_pads_oride;                    /* _DPD_PADS_ORIDE_0,               0x1c */
-    uint32_t dpd_sample;                        /* _DPD_SAMPLE_0,                   0x20 */
-    uint32_t dpd_enable;                        /* _DPD_ENABLE_0,                   0x24 */
-    uint32_t pwrgate_timer_off;                 /* _PWRGATE_TIMER_OFF_0,            0x28 */
-    uint32_t clamp_status;                      /* _CLAMP_STATUS_0,                 0x2c */
-    uint32_t pwrgate_toggle;                    /* _PWRGATE_TOGGLE_0,               0x30 */
-    uint32_t remove_clamping;                   /* _REMOVE_CLAMPING_0,              0x34 */
-    uint32_t pwrgate_status;                    /* _PWRGATE_STATUS_0,               0x38 */
-    uint32_t pwrgood_timer;                     /* _PWRGOOD_TIMER_0,                0x3c */
-    uint32_t blink_timer;                       /* _BLINK_TIMER_0,                  0x40 */
-    uint32_t no_iopower;                        /* _NO_IOPOWER_0,                   0x44 */
-    uint32_t pwr_det;                           /* _PWR_DET_0,                      0x48 */
-    uint32_t pwr_det_latch;                     /* _PWR_DET_LATCH_0,                0x4c */
-    uint32_t scratch0;                          /* _SCRATCH0_0,                     0x50 */
-    uint32_t scratch1;                          /* _SCRATCH1_0,                     0x54 */
-    uint32_t scratch2;                          /* _SCRATCH2_0,                     0x58 */
-    uint32_t scratch3;                          /* _SCRATCH3_0,                     0x5c */
-    uint32_t scratch4;                          /* _SCRATCH4_0,                     0x60 */
-    uint32_t scratch5;                          /* _SCRATCH5_0,                     0x64 */
-    uint32_t scratch6;                          /* _SCRATCH6_0,                     0x68 */
-    uint32_t scratch7;                          /* _SCRATCH7_0,                     0x6c */
-    uint32_t scratch8;                          /* _SCRATCH8_0,                     0x70 */
-    uint32_t scratch9;                          /* _SCRATCH9_0,                     0x74 */
-    uint32_t scratch10;                         /* _SCRATCH10_0,                    0x78 */
-    uint32_t scratch11;                         /* _SCRATCH11_0,                    0x7c */
-    uint32_t scratch12;                         /* _SCRATCH12_0,                    0x80 */
-    uint32_t scratch13;                         /* _SCRATCH13_0,                    0x84 */
-    uint32_t scratch14;                         /* _SCRATCH14_0,                    0x88 */
-    uint32_t scratch15;                         /* _SCRATCH15_0,                    0x8c */
-    uint32_t scratch16;                         /* _SCRATCH16_0,                    0x90 */
-    uint32_t scratch17;                         /* _SCRATCH17_0,                    0x94 */
-    uint32_t scratch18;                         /* _SCRATCH18_0,                    0x98 */
-    uint32_t scratch19;                         /* _SCRATCH19_0,                    0x9c */
-    uint32_t scratch20;                         /* _SCRATCH20_0,                    0xa0 */
-    uint32_t scratch21;                         /* _SCRATCH21_0,                    0xa4 */
-    uint32_t scratch22;                         /* _SCRATCH22_0,                    0xa8 */
-    uint32_t scratch23;                         /* _SCRATCH23_0,                    0xac */
-    uint32_t secure_scratch0;                   /* _SECURE_SCRATCH0_0,              0xb0 */
-    uint32_t secure_scratch1;                   /* _SECURE_SCRATCH1_0,              0xb4 */
-    uint32_t secure_scratch2;                   /* _SECURE_SCRATCH2_0,              0xb8 */
-    uint32_t secure_scratch3;                   /* _SECURE_SCRATCH3_0,              0xbc */
-    uint32_t secure_scratch4;                   /* _SECURE_SCRATCH4_0,              0xc0 */
-    uint32_t secure_scratch5;                   /* _SECURE_SCRATCH5_0,              0xc4 */
-    uint32_t cpupwrgood_timer;                  /* _CPUPWRGOOD_TIMER_0,             0xc8 */
-    uint32_t cpupwroff_timer;                   /* _CPUPWROFF_TIMER_0,              0xcc */
-    uint32_t pg_mask;                           /* _PG_MASK_0,                      0xd0 */
-    uint32_t pg_mask_1;                         /* _PG_MASK_1_0,                    0xd4 */
-    uint32_t auto_wake_lvl;                     /* _AUTO_WAKE_LVL_0,                0xd8 */
-    uint32_t auto_wake_lvl_mask;                /* _AUTO_WAKE_LVL_MASK_0,           0xdc */
-    uint32_t wake_delay;                        /* _WAKE_DELAY_0,                   0xe0 */
-    uint32_t pwr_det_val;                       /* _PWR_DET_VAL_0,                  0xe4 */
-    uint32_t ddr_pwr;                           /* _DDR_PWR_0,                      0xe8 */
-    uint32_t usb_debounce_del;                  /* _USB_DEBOUNCE_DEL_0,             0xec */
-    uint32_t usb_ao;                            /* _USB_AO_0,                       0xf0 */
-    uint32_t crypto_op;                         /* _CRYPTO_OP_0,                    0xf4 */
-    uint32_t pllp_wb0_override;                 /* _PLLP_WB0_OVERRIDE_0,            0xf8 */
-    uint32_t scratch24;                         /* _SCRATCH24_0,                    0xfc */
-    uint32_t scratch25;                         /* _SCRATCH25_0,                    0x100 */
-    uint32_t scratch26;                         /* _SCRATCH26_0,                    0x104 */
-    uint32_t scratch27;                         /* _SCRATCH27_0,                    0x108 */
-    uint32_t scratch28;                         /* _SCRATCH28_0,                    0x10c */
-    uint32_t scratch29;                         /* _SCRATCH29_0,                    0x110 */
-    uint32_t scratch30;                         /* _SCRATCH30_0,                    0x114 */
-    uint32_t scratch31;                         /* _SCRATCH31_0,                    0x118 */
-    uint32_t scratch32;                         /* _SCRATCH32_0,                    0x11c */
-    uint32_t scratch33;                         /* _SCRATCH33_0,                    0x120 */
-    uint32_t scratch34;                         /* _SCRATCH34_0,                    0x124 */
-    uint32_t scratch35;                         /* _SCRATCH35_0,                    0x128 */
-    uint32_t scratch36;                         /* _SCRATCH36_0,                    0x12c */
-    uint32_t scratch37;                         /* _SCRATCH37_0,                    0x130 */
-    uint32_t scratch38;                         /* _SCRATCH38_0,                    0x134 */
-    uint32_t scratch39;                         /* _SCRATCH39_0,                    0x138 */
-    uint32_t scratch40;                         /* _SCRATCH40_0,                    0x13c */
-    uint32_t scratch41;                         /* _SCRATCH41_0,                    0x140 */
-    uint32_t scratch42;                         /* _SCRATCH42_0,                    0x144 */
-    uint32_t bondout_mirror0;                   /* _BONDOUT_MIRROR0_0,              0x148 */
-    uint32_t bondout_mirror1;                   /* _BONDOUT_MIRROR1_0,              0x14c */
-    uint32_t bondout_mirror2;                   /* _BONDOUT_MIRROR2_0,              0x150 */
-    uint32_t sys_33v_en;                        /* _SYS_33V_EN_0,                   0x154 */
-    uint32_t bondout_mirror_access;             /* _BONDOUT_MIRROR_ACCESS_0,        0x158 */
-    uint32_t gate;                              /* _GATE_0,                         0x15c */
-    uint32_t wake2_mask;                        /* _WAKE2_MASK_0,                   0x160 */
-    uint32_t wake2_lvl;                         /* _WAKE2_LVL_0,                    0x164 */
-    uint32_t wake2_status;                      /* _WAKE2_STATUS_0,                 0x168 */
-    uint32_t sw_wake2_status;                   /* _SW_WAKE2_STATUS_0,              0x16c */
-    uint32_t auto_wake2_lvl_mask;               /* _AUTO_WAKE2_LVL_MASK_0,          0x170 */
-    uint32_t pg_mask_2;                         /* _PG_MASK_2_0,                    0x174 */
-    uint32_t pg_mask_ce1;                       /* _PG_MASK_CE1_0,                  0x178 */
-    uint32_t pg_mask_ce2;                       /* _PG_MASK_CE2_0,                  0x17c */
-    uint32_t pg_mask_ce3;                       /* _PG_MASK_CE3_0,                  0x180 */
-    uint32_t pwrgate_timer_ce_0;                /* _PWRGATE_TIMER_CE_0_0,           0x184 */
-    uint32_t pwrgate_timer_ce_1;                /* _PWRGATE_TIMER_CE_1_0,           0x188 */
-    uint32_t pwrgate_timer_ce_2;                /* _PWRGATE_TIMER_CE_2_0,           0x18c */
-    uint32_t pwrgate_timer_ce_3;                /* _PWRGATE_TIMER_CE_3_0,           0x190 */
-    uint32_t pwrgate_timer_ce_4;                /* _PWRGATE_TIMER_CE_4_0,           0x194 */
-    uint32_t pwrgate_timer_ce_5;                /* _PWRGATE_TIMER_CE_5_0,           0x198 */
-    uint32_t pwrgate_timer_ce_6;                /* _PWRGATE_TIMER_CE_6_0,           0x19c */
-    uint32_t pcx_edpd_cntrl;                    /* _PCX_EDPD_CNTRL_0,               0x1a0 */
-    uint32_t osc_edpd_over;                     /* _OSC_EDPD_OVER_0,                0x1a4 */
-    uint32_t clk_out_cntrl;                     /* _CLK_OUT_CNTRL_0,                0x1a8 */
-    uint32_t sata_pwrgt;                        /* _SATA_PWRGT_0,                   0x1ac */
-    uint32_t sensor_ctrl;                       /* _SENSOR_CTRL_0,                  0x1b0 */
-    uint32_t rst_status;                        /* _RST_STATUS_0,                   0x1b4 */
-    uint32_t io_dpd_req;                        /* _IO_DPD_REQ_0,                   0x1b8 */
-    uint32_t io_dpd_status;                     /* _IO_DPD_STATUS_0,                0x1bc */
-    uint32_t io_dpd2_req;                       /* _IO_DPD2_REQ_0,                  0x1c0 */
-    uint32_t io_dpd2_status;                    /* _IO_DPD2_STATUS_0,               0x1c4 */
-    uint32_t sel_dpd_tim;                       /* _SEL_DPD_TIM_0,                  0x1c8 */
-    uint32_t vddp_sel;                          /* _VDDP_SEL_0,                     0x1cc */
-    uint32_t ddr_cfg;                           /* _DDR_CFG_0,                      0x1d0 */
-    uint32_t _0x1d4[2];
-    uint32_t pllm_wb0_override_freq;            /* _PLLM_WB0_OVERRIDE_FREQ_0,       0x1dc */
-    uint32_t _0x1e0;
-    uint32_t pwrgate_timer_mult;                /* _PWRGATE_TIMER_MULT_0,           0x1e4 */
-    uint32_t dsi_sel_dpd;                       /* _DSI_SEL_DPD_0,                  0x1e8 */
-    uint32_t utmip_uhsic_triggers;              /* _UTMIP_UHSIC_TRIGGERS_0,         0x1ec */
-    uint32_t utmip_uhsic_saved_state;           /* _UTMIP_UHSIC_SAVED_STATE_0,      0x1f0 */
-    uint32_t _0x1f4;
-    uint32_t utmip_term_pad_cfg;                /* _UTMIP_TERM_PAD_CFG_0,           0x1f8 */
-    uint32_t utmip_uhsic_sleep_cfg;             /* _UTMIP_UHSIC_SLEEP_CFG_0,        0x1fc */
-    uint32_t utmip_uhsic_sleepwalk_cfg;         /* _UTMIP_UHSIC_SLEEPWALK_CFG_0,    0x200 */
-    uint32_t utmip_sleepwalk_p0;                /* _UTMIP_SLEEPWALK_P0_0,           0x204 */
-    uint32_t utmip_sleepwalk_p1;                /* _UTMIP_SLEEPWALK_P1_0,           0x208 */
-    uint32_t utmip_sleepwalk_p2;                /* _UTMIP_SLEEPWALK_P2_0,           0x20c */
-    uint32_t uhsic_sleepwalk_p0;                /* _UHSIC_SLEEPWALK_P0_0,           0x210 */
-    uint32_t utmip_uhsic_status;                /* _UTMIP_UHSIC_STATUS_0,           0x214 */
-    uint32_t utmip_uhsic_fake;                  /* _UTMIP_UHSIC_FAKE_0,             0x218 */
-    uint32_t bondout_mirror3;                   /* _BONDOUT_MIRROR3_0,              0x21c */
-    uint32_t bondout_mirror4;                   /* _BONDOUT_MIRROR4_0,              0x220 */
-    uint32_t secure_scratch6;                   /* _SECURE_SCRATCH6_0,              0x224 */
-    uint32_t secure_scratch7;                   /* _SECURE_SCRATCH7_0,              0x228 */
-    uint32_t scratch43;                         /* _SCRATCH43_0,                    0x22c */
-    uint32_t scratch44;                         /* _SCRATCH44_0,                    0x230 */
-    uint32_t scratch45;                         /* _SCRATCH45_0,                    0x234 */
-    uint32_t scratch46;                         /* _SCRATCH46_0,                    0x238 */
-    uint32_t scratch47;                         /* _SCRATCH47_0,                    0x23c */
-    uint32_t scratch48;                         /* _SCRATCH48_0,                    0x240 */
-    uint32_t scratch49;                         /* _SCRATCH49_0,                    0x244 */
-    uint32_t scratch50;                         /* _SCRATCH50_0,                    0x248 */
-    uint32_t scratch51;                         /* _SCRATCH51_0,                    0x24c */
-    uint32_t scratch52;                         /* _SCRATCH52_0,                    0x250 */
-    uint32_t scratch53;                         /* _SCRATCH53_0,                    0x254 */
-    uint32_t scratch54;                         /* _SCRATCH54_0,                    0x258 */
-    uint32_t scratch55;                         /* _SCRATCH55_0,                    0x25c */
-    uint32_t scratch0_eco;                      /* _SCRATCH0_ECO_0,                 0x260 */
-    uint32_t por_dpd_ctrl;                      /* _POR_DPD_CTRL_0,                 0x264 */
-    uint32_t scratch2_eco;                      /* _SCRATCH2_ECO_0,                 0x268 */
-    uint32_t utmip_uhsic_line_wakeup;           /* _UTMIP_UHSIC_LINE_WAKEUP_0,      0x26c */
-    uint32_t utmip_bias_master_cntrl;           /* _UTMIP_BIAS_MASTER_CNTRL_0,      0x270 */
-    uint32_t utmip_master_config;               /* _UTMIP_MASTER_CONFIG_0,          0x274 */
-    uint32_t td_pwrgate_inter_part_timer;       /* _TD_PWRGATE_INTER_PART_TIMER_0,  0x278 */
-    uint32_t utmip_uhsic2_triggers;             /* _UTMIP_UHSIC2_TRIGGERS_0,        0x27c */
-    uint32_t utmip_uhsic2_saved_state;          /* _UTMIP_UHSIC2_SAVED_STATE_0,     0x280 */
-    uint32_t utmip_uhsic2_sleep_cfg;            /* _UTMIP_UHSIC2_SLEEP_CFG_0,       0x284 */
-    uint32_t utmip_uhsic2_sleepwalk_cfg;        /* _UTMIP_UHSIC2_SLEEPWALK_CFG_0,   0x288 */
-    uint32_t uhsic2_sleepwalk_p1;               /* _UHSIC2_SLEEPWALK_P1_0,          0x28c */
-    uint32_t utmip_uhsic2_status;               /* _UTMIP_UHSIC2_STATUS_0,          0x290 */
-    uint32_t utmip_uhsic2_fake;                 /* _UTMIP_UHSIC2_FAKE_0,            0x294 */
-    uint32_t utmip_uhsic2_line_wakeup;          /* _UTMIP_UHSIC2_LINE_WAKEUP_0,     0x298 */
-    uint32_t utmip_master2_config;              /* _UTMIP_MASTER2_CONFIG_0,         0x29c */
-    uint32_t utmip_uhsic_rpd_cfg;               /* _UTMIP_UHSIC_RPD_CFG_0,          0x2a0 */
-    uint32_t pg_mask_ce0;                       /* _PG_MASK_CE0_0,                  0x2a4 */
-    uint32_t pg_mask_3;                         /* _PG_MASK_3_0,                    0x2a8 */
-    uint32_t pg_mask_4;                         /* _PG_MASK_4_0,                    0x2ac */
-    uint32_t pllm_wb0_override2;                /* _PLLM_WB0_OVERRIDE2_0,           0x2b0 */
-    uint32_t tsc_mult;                          /* _TSC_MULT_0,                     0x2b4 */
-    uint32_t cpu_vsense_override;               /* _CPU_VSENSE_OVERRIDE_0,          0x2b8 */
-    uint32_t glb_amap_cfg;                      /* _GLB_AMAP_CFG_0,                 0x2bc */
-    uint32_t sticky_bits;                       /* _STICKY_BITS_0,                  0x2c0 */
-    uint32_t sec_disable2;                      /* _SEC_DISABLE2_0,                 0x2c4 */
-    uint32_t weak_bias;                         /* _WEAK_BIAS_0,                    0x2c8 */
-    uint32_t reg_short;                         /* _REG_SHORT_0,                    0x2cc */
-    uint32_t pg_mask_andor;                     /* _PG_MASK_ANDOR_0,                0x2d0 */
-    uint32_t gpu_rg_cntrl;                      /* _GPU_RG_CNTRL_0,                 0x2d4 */
-    uint32_t sec_disable3;                      /* _SEC_DISABLE3_0,                 0x2d8 */
-    uint32_t pg_mask_5;                         /* _PG_MASK_5_0,                    0x2dc */
-    uint32_t pg_mask_6;                         /* _PG_MASK_6_0,                    0x2e0 */
-    uint32_t _0x2e4[7];
-    uint32_t secure_scratch8;                   /* _SECURE_SCRATCH8_0,              0x300 */
-    uint32_t secure_scratch9;                   /* _SECURE_SCRATCH9_0,              0x304 */
-    uint32_t secure_scratch10;                  /* _SECURE_SCRATCH10_0,             0x308 */
-    uint32_t secure_scratch11;                  /* _SECURE_SCRATCH11_0,             0x30c */
-    uint32_t secure_scratch12;                  /* _SECURE_SCRATCH12_0,             0x310 */
-    uint32_t secure_scratch13;                  /* _SECURE_SCRATCH13_0,             0x314 */
-    uint32_t secure_scratch14;                  /* _SECURE_SCRATCH14_0,             0x318 */
-    uint32_t secure_scratch15;                  /* _SECURE_SCRATCH15_0,             0x31c */
-    uint32_t secure_scratch16;                  /* _SECURE_SCRATCH16_0,             0x320 */
-    uint32_t secure_scratch17;                  /* _SECURE_SCRATCH17_0,             0x324 */
-    uint32_t secure_scratch18;                  /* _SECURE_SCRATCH18_0,             0x328 */
-    uint32_t secure_scratch19;                  /* _SECURE_SCRATCH19_0,             0x32c */
-    uint32_t secure_scratch20;                  /* _SECURE_SCRATCH20_0,             0x330 */
-    uint32_t secure_scratch21;                  /* _SECURE_SCRATCH21_0,             0x334 */
-    uint32_t secure_scratch22;                  /* _SECURE_SCRATCH22_0,             0x338 */
-    uint32_t secure_scratch23;                  /* _SECURE_SCRATCH23_0,             0x33c */
-    uint32_t secure_scratch24;                  /* _SECURE_SCRATCH24_0,             0x340 */
-    uint32_t secure_scratch25;                  /* _SECURE_SCRATCH25_0,             0x344 */
-    uint32_t secure_scratch26;                  /* _SECURE_SCRATCH26_0,             0x348 */
-    uint32_t secure_scratch27;                  /* _SECURE_SCRATCH27_0,             0x34c */
-    uint32_t secure_scratch28;                  /* _SECURE_SCRATCH28_0,             0x350 */
-    uint32_t secure_scratch29;                  /* _SECURE_SCRATCH29_0,             0x354 */
-    uint32_t secure_scratch30;                  /* _SECURE_SCRATCH30_0,             0x358 */
-    uint32_t secure_scratch31;                  /* _SECURE_SCRATCH31_0,             0x35c */
-    uint32_t secure_scratch32;                  /* _SECURE_SCRATCH32_0,             0x360 */
-    uint32_t secure_scratch33;                  /* _SECURE_SCRATCH33_0,             0x364 */
-    uint32_t secure_scratch34;                  /* _SECURE_SCRATCH34_0,             0x368 */
-    uint32_t secure_scratch35;                  /* _SECURE_SCRATCH35_0,             0x36c */
-    uint32_t secure_scratch36;                  /* _SECURE_SCRATCH36_0,             0x370 */
-    uint32_t secure_scratch37;                  /* _SECURE_SCRATCH37_0,             0x374 */
-    uint32_t secure_scratch38;                  /* _SECURE_SCRATCH38_0,             0x378 */
-    uint32_t secure_scratch39;                  /* _SECURE_SCRATCH39_0,             0x37c */
-    uint32_t secure_scratch40;                  /* _SECURE_SCRATCH40_0,             0x380 */
-    uint32_t secure_scratch41;                  /* _SECURE_SCRATCH41_0,             0x384 */
-    uint32_t secure_scratch42;                  /* _SECURE_SCRATCH42_0,             0x388 */
-    uint32_t secure_scratch43;                  /* _SECURE_SCRATCH43_0,             0x38c */
-    uint32_t secure_scratch44;                  /* _SECURE_SCRATCH44_0,             0x390 */
-    uint32_t secure_scratch45;                  /* _SECURE_SCRATCH45_0,             0x394 */
-    uint32_t secure_scratch46;                  /* _SECURE_SCRATCH46_0,             0x398 */
-    uint32_t secure_scratch47;                  /* _SECURE_SCRATCH47_0,             0x39c */
-    uint32_t secure_scratch48;                  /* _SECURE_SCRATCH48_0,             0x3a0 */
-    uint32_t secure_scratch49;                  /* _SECURE_SCRATCH49_0,             0x3a4 */
-    uint32_t secure_scratch50;                  /* _SECURE_SCRATCH50_0,             0x3a8 */
-    uint32_t secure_scratch51;                  /* _SECURE_SCRATCH51_0,             0x3ac */
-    uint32_t secure_scratch52;                  /* _SECURE_SCRATCH52_0,             0x3b0 */
-    uint32_t secure_scratch53;                  /* _SECURE_SCRATCH53_0,             0x3b4 */
-    uint32_t secure_scratch54;                  /* _SECURE_SCRATCH54_0,             0x3b8 */
-    uint32_t secure_scratch55;                  /* _SECURE_SCRATCH55_0,             0x3bc */
-    uint32_t secure_scratch56;                  /* _SECURE_SCRATCH56_0,             0x3c0 */
-    uint32_t secure_scratch57;                  /* _SECURE_SCRATCH57_0,             0x3c4 */
-    uint32_t secure_scratch58;                  /* _SECURE_SCRATCH58_0,             0x3c8 */
-    uint32_t secure_scratch59;                  /* _SECURE_SCRATCH59_0,             0x3cc */
-    uint32_t secure_scratch60;                  /* _SECURE_SCRATCH60_0,             0x3d0 */
-    uint32_t secure_scratch61;                  /* _SECURE_SCRATCH61_0,             0x3d4 */
-    uint32_t secure_scratch62;                  /* _SECURE_SCRATCH62_0,             0x3d8 */
-    uint32_t secure_scratch63;                  /* _SECURE_SCRATCH63_0,             0x3dc */
-    uint32_t secure_scratch64;                  /* _SECURE_SCRATCH64_0,             0x3e0 */
-    uint32_t secure_scratch65;                  /* _SECURE_SCRATCH65_0,             0x3e4 */
-    uint32_t secure_scratch66;                  /* _SECURE_SCRATCH66_0,             0x3e8 */
-    uint32_t secure_scratch67;                  /* _SECURE_SCRATCH67_0,             0x3ec */
-    uint32_t secure_scratch68;                  /* _SECURE_SCRATCH68_0,             0x3f0 */
-    uint32_t secure_scratch69;                  /* _SECURE_SCRATCH69_0,             0x3f4 */
-    uint32_t secure_scratch70;                  /* _SECURE_SCRATCH70_0,             0x3f8 */
-    uint32_t secure_scratch71;                  /* _SECURE_SCRATCH71_0,             0x3fc */
-    uint32_t secure_scratch72;                  /* _SECURE_SCRATCH72_0,             0x400 */
-    uint32_t secure_scratch73;                  /* _SECURE_SCRATCH73_0,             0x404 */
-    uint32_t secure_scratch74;                  /* _SECURE_SCRATCH74_0,             0x408 */
-    uint32_t secure_scratch75;                  /* _SECURE_SCRATCH75_0,             0x40c */
-    uint32_t secure_scratch76;                  /* _SECURE_SCRATCH76_0,             0x410 */
-    uint32_t secure_scratch77;                  /* _SECURE_SCRATCH77_0,             0x414 */
-    uint32_t secure_scratch78;                  /* _SECURE_SCRATCH78_0,             0x418 */
-    uint32_t secure_scratch79;                  /* _SECURE_SCRATCH79_0,             0x41c */
-    uint32_t _0x420[8];
-    uint32_t cntrl2;                            /* _CNTRL2_0,                       0x440 */
-    uint32_t io_dpd_off_mask;                   /* _IO_DPD_OFF_MASK_0,              0x444 */
-    uint32_t io_dpd2_off_mask;                  /* _IO_DPD2_OFF_MASK_0,             0x448 */
-    uint32_t event_counter;                     /* _EVENT_COUNTER_0,                0x44c */
-    uint32_t fuse_control;                      /* _FUSE_CONTROL_0,                 0x450 */
-    uint32_t scratch1_eco;                      /* _SCRATCH1_ECO_0,                 0x454 */
-    uint32_t _0x458;
-    uint32_t io_dpd3_req;                       /* _IO_DPD3_REQ_0,                  0x45c */
-    uint32_t io_dpd3_status;                    /* _IO_DPD3_STATUS_0,               0x460 */
-    uint32_t io_dpd4_req;                       /* _IO_DPD4_REQ_0,                  0x464 */
-    uint32_t io_dpd4_status;                    /* _IO_DPD4_STATUS_0,               0x468 */
-    uint32_t _0x46c[2];
-    uint32_t direct_thermtrip_cfg;              /* _DIRECT_THERMTRIP_CFG_0,         0x474 */
-    uint32_t tsosc_delay;                       /* _TSOSC_DELAY_0,                  0x478 */
-    uint32_t set_sw_clamp;                      /* _SET_SW_CLAMP_0,                 0x47c */
-    uint32_t debug_authentication;              /* _DEBUG_AUTHENTICATION_0,         0x480 */
-    uint32_t aotag_cfg;                         /* _AOTAG_CFG_0,                    0x484 */
-    uint32_t aotag_thresh1_cfg;                 /* _AOTAG_THRESH1_CFG_0,            0x488 */
-    uint32_t aotag_thresh2_cfg;                 /* _AOTAG_THRESH2_CFG_0,            0x48c */
-    uint32_t aotag_thresh3_cfg;                 /* _AOTAG_THRESH3_CFG_0,            0x490 */
-    uint32_t aotag_status;                      /* _AOTAG_STATUS_0,                 0x494 */
-    uint32_t aotag_security;                    /* _AOTAG_SECURITY_0,               0x498 */
-    uint32_t tsensor_config0;                   /* _TSENSOR_CONFIG0_0,              0x49c */
-    uint32_t tsensor_config1;                   /* _TSENSOR_CONFIG1_0,              0x4a0 */
-    uint32_t tsensor_config2;                   /* _TSENSOR_CONFIG2_0,              0x4a4 */
-    uint32_t tsensor_status0;                   /* _TSENSOR_STATUS0_0,              0x4a8 */
-    uint32_t tsensor_status1;                   /* _TSENSOR_STATUS1_0,              0x4ac */
-    uint32_t tsensor_status2;                   /* _TSENSOR_STATUS2_0,              0x4b0 */
-    uint32_t tsensor_pdiv;                      /* _TSENSOR_PDIV_0,                 0x4b4 */
-    uint32_t aotag_intr_en;                     /* _AOTAG_INTR_EN_0,                0x4b8 */
-    uint32_t aotag_intr_dis;                    /* _AOTAG_INTR_DIS_0,               0x4bc */
-    uint32_t utmip_pad_cfg0;                    /* _UTMIP_PAD_CFG0_0,               0x4c0 */
-    uint32_t utmip_pad_cfg1;                    /* _UTMIP_PAD_CFG1_0,               0x4c4 */
-    uint32_t utmip_pad_cfg2;                    /* _UTMIP_PAD_CFG2_0,               0x4c8 */
-    uint32_t utmip_pad_cfg3;                    /* _UTMIP_PAD_CFG3_0,               0x4cc */
-    uint32_t utmip_uhsic_sleep_cfg1;            /* _UTMIP_UHSIC_SLEEP_CFG1_0,       0x4d0 */
-    uint32_t cc4_hvc_control;                   /* _CC4_HVC_CONTROL_0,              0x4d4 */
-    uint32_t wake_debounce_en;                  /* _WAKE_DEBOUNCE_EN_0,             0x4d8 */
-    uint32_t ramdump_ctl_status;                /* _RAMDUMP_CTL_STATUS_0,           0x4dc */
-    uint32_t utmip_sleepwalk_p3;                /* _UTMIP_SLEEPWALK_P3_0,           0x4e0 */
-    uint32_t ddr_cntrl;                         /* _DDR_CNTRL_0,                    0x4e4 */
-    uint32_t _0x4e8[50];
-    uint32_t sec_disable4;                      /* _SEC_DISABLE4_0,                 0x5b0 */
-    uint32_t sec_disable5;                      /* _SEC_DISABLE5_0,                 0x5b4 */
-    uint32_t sec_disable6;                      /* _SEC_DISABLE6_0,                 0x5b8 */
-    uint32_t sec_disable7;                      /* _SEC_DISABLE7_0,                 0x5bc */
-    uint32_t sec_disable8;                      /* _SEC_DISABLE8_0,                 0x5c0 */
-    uint32_t sec_disable9;                      /* _SEC_DISABLE9_0,                 0x5c4 */
-    uint32_t sec_disable10;                     /* _SEC_DISABLE10_0,                0x5c8 */
-    uint32_t _0x5cc[13];
-    uint32_t scratch56;                         /* _SCRATCH56_0,                    0x600 */
-    uint32_t scratch57;                         /* _SCRATCH57_0,                    0x604 */
-    uint32_t scratch58;                         /* _SCRATCH58_0,                    0x608 */
-    uint32_t scratch59;                         /* _SCRATCH59_0,                    0x60c */
-    uint32_t scratch60;                         /* _SCRATCH60_0,                    0x610 */
-    uint32_t scratch61;                         /* _SCRATCH61_0,                    0x614 */
-    uint32_t scratch62;                         /* _SCRATCH62_0,                    0x618 */
-    uint32_t scratch63;                         /* _SCRATCH63_0,                    0x61c */
-    uint32_t scratch64;                         /* _SCRATCH64_0,                    0x620 */
-    uint32_t scratch65;                         /* _SCRATCH65_0,                    0x624 */
-    uint32_t scratch66;                         /* _SCRATCH66_0,                    0x628 */
-    uint32_t scratch67;                         /* _SCRATCH67_0,                    0x62c */
-    uint32_t scratch68;                         /* _SCRATCH68_0,                    0x630 */
-    uint32_t scratch69;                         /* _SCRATCH69_0,                    0x634 */
-    uint32_t scratch70;                         /* _SCRATCH70_0,                    0x638 */
-    uint32_t scratch71;                         /* _SCRATCH71_0,                    0x63c */
-    uint32_t scratch72;                         /* _SCRATCH72_0,                    0x640 */
-    uint32_t scratch73;                         /* _SCRATCH73_0,                    0x644 */
-    uint32_t scratch74;                         /* _SCRATCH74_0,                    0x648 */
-    uint32_t scratch75;                         /* _SCRATCH75_0,                    0x64c */
-    uint32_t scratch76;                         /* _SCRATCH76_0,                    0x650 */
-    uint32_t scratch77;                         /* _SCRATCH77_0,                    0x654 */
-    uint32_t scratch78;                         /* _SCRATCH78_0,                    0x658 */
-    uint32_t scratch79;                         /* _SCRATCH79_0,                    0x65c */
-    uint32_t scratch80;                         /* _SCRATCH80_0,                    0x660 */
-    uint32_t scratch81;                         /* _SCRATCH81_0,                    0x664 */
-    uint32_t scratch82;                         /* _SCRATCH82_0,                    0x668 */
-    uint32_t scratch83;                         /* _SCRATCH83_0,                    0x66c */
-    uint32_t scratch84;                         /* _SCRATCH84_0,                    0x670 */
-    uint32_t scratch85;                         /* _SCRATCH85_0,                    0x674 */
-    uint32_t scratch86;                         /* _SCRATCH86_0,                    0x678 */
-    uint32_t scratch87;                         /* _SCRATCH87_0,                    0x67c */
-    uint32_t scratch88;                         /* _SCRATCH88_0,                    0x680 */
-    uint32_t scratch89;                         /* _SCRATCH89_0,                    0x684 */
-    uint32_t scratch90;                         /* _SCRATCH90_0,                    0x688 */
-    uint32_t scratch91;                         /* _SCRATCH91_0,                    0x68c */
-    uint32_t scratch92;                         /* _SCRATCH92_0,                    0x690 */
-    uint32_t scratch93;                         /* _SCRATCH93_0,                    0x694 */
-    uint32_t scratch94;                         /* _SCRATCH94_0,                    0x698 */
-    uint32_t scratch95;                         /* _SCRATCH95_0,                    0x69c */
-    uint32_t scratch96;                         /* _SCRATCH96_0,                    0x6a0 */
-    uint32_t scratch97;                         /* _SCRATCH97_0,                    0x6a4 */
-    uint32_t scratch98;                         /* _SCRATCH98_0,                    0x6a8 */
-    uint32_t scratch99;                         /* _SCRATCH99_0,                    0x6ac */
-    uint32_t scratch100;                        /* _SCRATCH100_0,                   0x6b0 */
-    uint32_t scratch101;                        /* _SCRATCH101_0,                   0x6b4 */
-    uint32_t scratch102;                        /* _SCRATCH102_0,                   0x6b8 */
-    uint32_t scratch103;                        /* _SCRATCH103_0,                   0x6bc */
-    uint32_t scratch104;                        /* _SCRATCH104_0,                   0x6c0 */
-    uint32_t scratch105;                        /* _SCRATCH105_0,                   0x6c4 */
-    uint32_t scratch106;                        /* _SCRATCH106_0,                   0x6c8 */
-    uint32_t scratch107;                        /* _SCRATCH107_0,                   0x6cc */
-    uint32_t scratch108;                        /* _SCRATCH108_0,                   0x6d0 */
-    uint32_t scratch109;                        /* _SCRATCH109_0,                   0x6d4 */
-    uint32_t scratch110;                        /* _SCRATCH110_0,                   0x6d8 */
-    uint32_t scratch111;                        /* _SCRATCH111_0,                   0x6dc */
-    uint32_t scratch112;                        /* _SCRATCH112_0,                   0x6e0 */
-    uint32_t scratch113;                        /* _SCRATCH113_0,                   0x6e4 */
-    uint32_t scratch114;                        /* _SCRATCH114_0,                   0x6e8 */
-    uint32_t scratch115;                        /* _SCRATCH115_0,                   0x6ec */
-    uint32_t scratch116;                        /* _SCRATCH116_0,                   0x6f0 */
-    uint32_t scratch117;                        /* _SCRATCH117_0,                   0x6f4 */
-    uint32_t scratch118;                        /* _SCRATCH118_0,                   0x6f8 */
-    uint32_t scratch119;                        /* _SCRATCH119_0,                   0x6fc */
-    uint32_t scratch120;                        /* _SCRATCH120_0,                   0x700 */
-    uint32_t scratch121;                        /* _SCRATCH121_0,                   0x704 */
-    uint32_t scratch122;                        /* _SCRATCH122_0,                   0x708 */
-    uint32_t scratch123;                        /* _SCRATCH123_0,                   0x70c */
-    uint32_t scratch124;                        /* _SCRATCH124_0,                   0x710 */
-    uint32_t scratch125;                        /* _SCRATCH125_0,                   0x714 */
-    uint32_t scratch126;                        /* _SCRATCH126_0,                   0x718 */
-    uint32_t scratch127;                        /* _SCRATCH127_0,                   0x71c */
-    uint32_t scratch128;                        /* _SCRATCH128_0,                   0x720 */
-    uint32_t scratch129;                        /* _SCRATCH129_0,                   0x724 */
-    uint32_t scratch130;                        /* _SCRATCH130_0,                   0x728 */
-    uint32_t scratch131;                        /* _SCRATCH131_0,                   0x72c */
-    uint32_t scratch132;                        /* _SCRATCH132_0,                   0x730 */
-    uint32_t scratch133;                        /* _SCRATCH133_0,                   0x734 */
-    uint32_t scratch134;                        /* _SCRATCH134_0,                   0x738 */
-    uint32_t scratch135;                        /* _SCRATCH135_0,                   0x73c */
-    uint32_t scratch136;                        /* _SCRATCH136_0,                   0x740 */
-    uint32_t scratch137;                        /* _SCRATCH137_0,                   0x744 */
-    uint32_t scratch138;                        /* _SCRATCH138_0,                   0x748 */
-    uint32_t scratch139;                        /* _SCRATCH139_0,                   0x74c */
-    uint32_t scratch140;                        /* _SCRATCH140_0,                   0x750 */
-    uint32_t scratch141;                        /* _SCRATCH141_0,                   0x754 */
-    uint32_t scratch142;                        /* _SCRATCH142_0,                   0x758 */
-    uint32_t scratch143;                        /* _SCRATCH143_0,                   0x75c */
-    uint32_t scratch144;                        /* _SCRATCH144_0,                   0x760 */
-    uint32_t scratch145;                        /* _SCRATCH145_0,                   0x764 */
-    uint32_t scratch146;                        /* _SCRATCH146_0,                   0x768 */
-    uint32_t scratch147;                        /* _SCRATCH147_0,                   0x76c */
-    uint32_t scratch148;                        /* _SCRATCH148_0,                   0x770 */
-    uint32_t scratch149;                        /* _SCRATCH149_0,                   0x774 */
-    uint32_t scratch150;                        /* _SCRATCH150_0,                   0x778 */
-    uint32_t scratch151;                        /* _SCRATCH151_0,                   0x77c */
-    uint32_t scratch152;                        /* _SCRATCH152_0,                   0x780 */
-    uint32_t scratch153;                        /* _SCRATCH153_0,                   0x784 */
-    uint32_t scratch154;                        /* _SCRATCH154_0,                   0x788 */
-    uint32_t scratch155;                        /* _SCRATCH155_0,                   0x78c */
-    uint32_t scratch156;                        /* _SCRATCH156_0,                   0x790 */
-    uint32_t scratch157;                        /* _SCRATCH157_0,                   0x794 */
-    uint32_t scratch158;                        /* _SCRATCH158_0,                   0x798 */
-    uint32_t scratch159;                        /* _SCRATCH159_0,                   0x79c */
-    uint32_t scratch160;                        /* _SCRATCH160_0,                   0x7a0 */
-    uint32_t scratch161;                        /* _SCRATCH161_0,                   0x7a4 */
-    uint32_t scratch162;                        /* _SCRATCH162_0,                   0x7a8 */
-    uint32_t scratch163;                        /* _SCRATCH163_0,                   0x7ac */
-    uint32_t scratch164;                        /* _SCRATCH164_0,                   0x7b0 */
-    uint32_t scratch165;                        /* _SCRATCH165_0,                   0x7b4 */
-    uint32_t scratch166;                        /* _SCRATCH166_0,                   0x7b8 */
-    uint32_t scratch167;                        /* _SCRATCH167_0,                   0x7bc */
-    uint32_t scratch168;                        /* _SCRATCH168_0,                   0x7c0 */
-    uint32_t scratch169;                        /* _SCRATCH169_0,                   0x7c4 */
-    uint32_t scratch170;                        /* _SCRATCH170_0,                   0x7c8 */
-    uint32_t scratch171;                        /* _SCRATCH171_0,                   0x7cc */
-    uint32_t scratch172;                        /* _SCRATCH172_0,                   0x7d0 */
-    uint32_t scratch173;                        /* _SCRATCH173_0,                   0x7d4 */
-    uint32_t scratch174;                        /* _SCRATCH174_0,                   0x7d8 */
-    uint32_t scratch175;                        /* _SCRATCH175_0,                   0x7dc */
-    uint32_t scratch176;                        /* _SCRATCH176_0,                   0x7e0 */
-    uint32_t scratch177;                        /* _SCRATCH177_0,                   0x7e4 */
-    uint32_t scratch178;                        /* _SCRATCH178_0,                   0x7e8 */
-    uint32_t scratch179;                        /* _SCRATCH179_0,                   0x7ec */
-    uint32_t scratch180;                        /* _SCRATCH180_0,                   0x7f0 */
-    uint32_t scratch181;                        /* _SCRATCH181_0,                   0x7f4 */
-    uint32_t scratch182;                        /* _SCRATCH182_0,                   0x7f8 */
-    uint32_t scratch183;                        /* _SCRATCH183_0,                   0x7fc */
-    uint32_t scratch184;                        /* _SCRATCH184_0,                   0x800 */
-    uint32_t scratch185;                        /* _SCRATCH185_0,                   0x804 */
-    uint32_t scratch186;                        /* _SCRATCH186_0,                   0x808 */
-    uint32_t scratch187;                        /* _SCRATCH187_0,                   0x80c */
-    uint32_t scratch188;                        /* _SCRATCH188_0,                   0x810 */
-    uint32_t scratch189;                        /* _SCRATCH189_0,                   0x814 */
-    uint32_t scratch190;                        /* _SCRATCH190_0,                   0x818 */
-    uint32_t scratch191;                        /* _SCRATCH191_0,                   0x81c */
-    uint32_t scratch192;                        /* _SCRATCH192_0,                   0x820 */
-    uint32_t scratch193;                        /* _SCRATCH193_0,                   0x824 */
-    uint32_t scratch194;                        /* _SCRATCH194_0,                   0x828 */
-    uint32_t scratch195;                        /* _SCRATCH195_0,                   0x82c */
-    uint32_t scratch196;                        /* _SCRATCH196_0,                   0x830 */
-    uint32_t scratch197;                        /* _SCRATCH197_0,                   0x834 */
-    uint32_t scratch198;                        /* _SCRATCH198_0,                   0x838 */
-    uint32_t scratch199;                        /* _SCRATCH199_0,                   0x83c */
-    uint32_t scratch200;                        /* _SCRATCH200_0,                   0x840 */
-    uint32_t scratch201;                        /* _SCRATCH201_0,                   0x844 */
-    uint32_t scratch202;                        /* _SCRATCH202_0,                   0x848 */
-    uint32_t scratch203;                        /* _SCRATCH203_0,                   0x84c */
-    uint32_t scratch204;                        /* _SCRATCH204_0,                   0x850 */
-    uint32_t scratch205;                        /* _SCRATCH205_0,                   0x854 */
-    uint32_t scratch206;                        /* _SCRATCH206_0,                   0x858 */
-    uint32_t scratch207;                        /* _SCRATCH207_0,                   0x85c */
-    uint32_t scratch208;                        /* _SCRATCH208_0,                   0x860 */
-    uint32_t scratch209;                        /* _SCRATCH209_0,                   0x864 */
-    uint32_t scratch210;                        /* _SCRATCH210_0,                   0x868 */
-    uint32_t scratch211;                        /* _SCRATCH211_0,                   0x86c */
-    uint32_t scratch212;                        /* _SCRATCH212_0,                   0x870 */
-    uint32_t scratch213;                        /* _SCRATCH213_0,                   0x874 */
-    uint32_t scratch214;                        /* _SCRATCH214_0,                   0x878 */
-    uint32_t scratch215;                        /* _SCRATCH215_0,                   0x87c */
-    uint32_t scratch216;                        /* _SCRATCH216_0,                   0x880 */
-    uint32_t scratch217;                        /* _SCRATCH217_0,                   0x884 */
-    uint32_t scratch218;                        /* _SCRATCH218_0,                   0x888 */
-    uint32_t scratch219;                        /* _SCRATCH219_0,                   0x88c */
-    uint32_t scratch220;                        /* _SCRATCH220_0,                   0x890 */
-    uint32_t scratch221;                        /* _SCRATCH221_0,                   0x894 */
-    uint32_t scratch222;                        /* _SCRATCH222_0,                   0x898 */
-    uint32_t scratch223;                        /* _SCRATCH223_0,                   0x89c */
-    uint32_t scratch224;                        /* _SCRATCH224_0,                   0x8a0 */
-    uint32_t scratch225;                        /* _SCRATCH225_0,                   0x8a4 */
-    uint32_t scratch226;                        /* _SCRATCH226_0,                   0x8a8 */
-    uint32_t scratch227;                        /* _SCRATCH227_0,                   0x8ac */
-    uint32_t scratch228;                        /* _SCRATCH228_0,                   0x8b0 */
-    uint32_t scratch229;                        /* _SCRATCH229_0,                   0x8b4 */
-    uint32_t scratch230;                        /* _SCRATCH230_0,                   0x8b8 */
-    uint32_t scratch231;                        /* _SCRATCH231_0,                   0x8bc */
-    uint32_t scratch232;                        /* _SCRATCH232_0,                   0x8c0 */
-    uint32_t scratch233;                        /* _SCRATCH233_0,                   0x8c4 */
-    uint32_t scratch234;                        /* _SCRATCH234_0,                   0x8c8 */
-    uint32_t scratch235;                        /* _SCRATCH235_0,                   0x8cc */
-    uint32_t scratch236;                        /* _SCRATCH236_0,                   0x8d0 */
-    uint32_t scratch237;                        /* _SCRATCH237_0,                   0x8d4 */
-    uint32_t scratch238;                        /* _SCRATCH238_0,                   0x8d8 */
-    uint32_t scratch239;                        /* _SCRATCH239_0,                   0x8dc */
-    uint32_t scratch240;                        /* _SCRATCH240_0,                   0x8e0 */
-    uint32_t scratch241;                        /* _SCRATCH241_0,                   0x8e4 */
-    uint32_t scratch242;                        /* _SCRATCH242_0,                   0x8e8 */
-    uint32_t scratch243;                        /* _SCRATCH243_0,                   0x8ec */
-    uint32_t scratch244;                        /* _SCRATCH244_0,                   0x8f0 */
-    uint32_t scratch245;                        /* _SCRATCH245_0,                   0x8f4 */
-    uint32_t scratch246;                        /* _SCRATCH246_0,                   0x8f8 */
-    uint32_t scratch247;                        /* _SCRATCH247_0,                   0x8fc */
-    uint32_t scratch248;                        /* _SCRATCH248_0,                   0x900 */
-    uint32_t scratch249;                        /* _SCRATCH249_0,                   0x904 */
-    uint32_t scratch250;                        /* _SCRATCH250_0,                   0x908 */
-    uint32_t scratch251;                        /* _SCRATCH251_0,                   0x90c */
-    uint32_t scratch252;                        /* _SCRATCH252_0,                   0x910 */
-    uint32_t scratch253;                        /* _SCRATCH253_0,                   0x914 */
-    uint32_t scratch254;                        /* _SCRATCH254_0,                   0x918 */
-    uint32_t scratch255;                        /* _SCRATCH255_0,                   0x91c */
-    uint32_t scratch256;                        /* _SCRATCH256_0,                   0x920 */
-    uint32_t scratch257;                        /* _SCRATCH257_0,                   0x924 */
-    uint32_t scratch258;                        /* _SCRATCH258_0,                   0x928 */
-    uint32_t scratch259;                        /* _SCRATCH259_0,                   0x92c */
-    uint32_t scratch260;                        /* _SCRATCH260_0,                   0x930 */
-    uint32_t scratch261;                        /* _SCRATCH261_0,                   0x934 */
-    uint32_t scratch262;                        /* _SCRATCH262_0,                   0x938 */
-    uint32_t scratch263;                        /* _SCRATCH263_0,                   0x93c */
-    uint32_t scratch264;                        /* _SCRATCH264_0,                   0x940 */
-    uint32_t scratch265;                        /* _SCRATCH265_0,                   0x944 */
-    uint32_t scratch266;                        /* _SCRATCH266_0,                   0x948 */
-    uint32_t scratch267;                        /* _SCRATCH267_0,                   0x94c */
-    uint32_t scratch268;                        /* _SCRATCH268_0,                   0x950 */
-    uint32_t scratch269;                        /* _SCRATCH269_0,                   0x954 */
-    uint32_t scratch270;                        /* _SCRATCH270_0,                   0x958 */
-    uint32_t scratch271;                        /* _SCRATCH271_0,                   0x95c */
-    uint32_t scratch272;                        /* _SCRATCH272_0,                   0x960 */
-    uint32_t scratch273;                        /* _SCRATCH273_0,                   0x964 */
-    uint32_t scratch274;                        /* _SCRATCH274_0,                   0x968 */
-    uint32_t scratch275;                        /* _SCRATCH275_0,                   0x96c */
-    uint32_t scratch276;                        /* _SCRATCH276_0,                   0x970 */
-    uint32_t scratch277;                        /* _SCRATCH277_0,                   0x974 */
-    uint32_t scratch278;                        /* _SCRATCH278_0,                   0x978 */
-    uint32_t scratch279;                        /* _SCRATCH279_0,                   0x97c */
-    uint32_t scratch280;                        /* _SCRATCH280_0,                   0x980 */
-    uint32_t scratch281;                        /* _SCRATCH281_0,                   0x984 */
-    uint32_t scratch282;                        /* _SCRATCH282_0,                   0x988 */
-    uint32_t scratch283;                        /* _SCRATCH283_0,                   0x98c */
-    uint32_t scratch284;                        /* _SCRATCH284_0,                   0x990 */
-    uint32_t scratch285;                        /* _SCRATCH285_0,                   0x994 */
-    uint32_t scratch286;                        /* _SCRATCH286_0,                   0x998 */
-    uint32_t scratch287;                        /* _SCRATCH287_0,                   0x99c */
-    uint32_t scratch288;                        /* _SCRATCH288_0,                   0x9a0 */
-    uint32_t scratch289;                        /* _SCRATCH289_0,                   0x9a4 */
-    uint32_t scratch290;                        /* _SCRATCH290_0,                   0x9a8 */
-    uint32_t scratch291;                        /* _SCRATCH291_0,                   0x9ac */
-    uint32_t scratch292;                        /* _SCRATCH292_0,                   0x9b0 */
-    uint32_t scratch293;                        /* _SCRATCH293_0,                   0x9b4 */
-    uint32_t scratch294;                        /* _SCRATCH294_0,                   0x9b8 */
-    uint32_t scratch295;                        /* _SCRATCH295_0,                   0x9bc */
-    uint32_t scratch296;                        /* _SCRATCH296_0,                   0x9c0 */
-    uint32_t scratch297;                        /* _SCRATCH297_0,                   0x9c4 */
-    uint32_t scratch298;                        /* _SCRATCH298_0,                   0x9c8 */
-    uint32_t scratch299;                        /* _SCRATCH299_0,                   0x9cc */
-    uint32_t _0x9d0[50];
-    uint32_t secure_scratch80;                  /* _SECURE_SCRATCH80_0,             0xa98 */
-    uint32_t secure_scratch81;                  /* _SECURE_SCRATCH81_0,             0xa9c */
-    uint32_t secure_scratch82;                  /* _SECURE_SCRATCH82_0,             0xaa0 */
-    uint32_t secure_scratch83;                  /* _SECURE_SCRATCH83_0,             0xaa4 */
-    uint32_t secure_scratch84;                  /* _SECURE_SCRATCH84_0,             0xaa8 */
-    uint32_t secure_scratch85;                  /* _SECURE_SCRATCH85_0,             0xaac */
-    uint32_t secure_scratch86;                  /* _SECURE_SCRATCH86_0,             0xab0 */
-    uint32_t secure_scratch87;                  /* _SECURE_SCRATCH87_0,             0xab4 */
-    uint32_t secure_scratch88;                  /* _SECURE_SCRATCH88_0,             0xab8 */
-    uint32_t secure_scratch89;                  /* _SECURE_SCRATCH89_0,             0xabc */
-    uint32_t secure_scratch90;                  /* _SECURE_SCRATCH90_0,             0xac0 */
-    uint32_t secure_scratch91;                  /* _SECURE_SCRATCH91_0,             0xac4 */
-    uint32_t secure_scratch92;                  /* _SECURE_SCRATCH92_0,             0xac8 */
-    uint32_t secure_scratch93;                  /* _SECURE_SCRATCH93_0,             0xacc */
-    uint32_t secure_scratch94;                  /* _SECURE_SCRATCH94_0,             0xad0 */
-    uint32_t secure_scratch95;                  /* _SECURE_SCRATCH95_0,             0xad4 */
-    uint32_t secure_scratch96;                  /* _SECURE_SCRATCH96_0,             0xad8 */
-    uint32_t secure_scratch97;                  /* _SECURE_SCRATCH97_0,             0xadc */
-    uint32_t secure_scratch98;                  /* _SECURE_SCRATCH98_0,             0xae0 */
-    uint32_t secure_scratch99;                  /* _SECURE_SCRATCH99_0,             0xae4 */
-    uint32_t secure_scratch100;                 /* _SECURE_SCRATCH100_0,            0xae8 */
-    uint32_t secure_scratch101;                 /* _SECURE_SCRATCH101_0,            0xaec */
-    uint32_t secure_scratch102;                 /* _SECURE_SCRATCH102_0,            0xaf0 */
-    uint32_t secure_scratch103;                 /* _SECURE_SCRATCH103_0,            0xaf4 */
-    uint32_t secure_scratch104;                 /* _SECURE_SCRATCH104_0,            0xaf8 */
-    uint32_t secure_scratch105;                 /* _SECURE_SCRATCH105_0,            0xafc */
-    uint32_t secure_scratch106;                 /* _SECURE_SCRATCH106_0,            0xb00 */
-    uint32_t secure_scratch107;                 /* _SECURE_SCRATCH107_0,            0xb04 */
-    uint32_t secure_scratch108;                 /* _SECURE_SCRATCH108_0,            0xb08 */
-    uint32_t secure_scratch109;                 /* _SECURE_SCRATCH109_0,            0xb0c */
-    uint32_t secure_scratch110;                 /* _SECURE_SCRATCH110_0,            0xb10 */
-    uint32_t secure_scratch111;                 /* _SECURE_SCRATCH111_0,            0xb14 */
-    uint32_t secure_scratch112;                 /* _SECURE_SCRATCH112_0,            0xb18 */
-    uint32_t secure_scratch113;                 /* _SECURE_SCRATCH113_0,            0xb1c */
-    uint32_t secure_scratch114;                 /* _SECURE_SCRATCH114_0,            0xb20 */
-    uint32_t secure_scratch115;                 /* _SECURE_SCRATCH115_0,            0xb24 */
-    uint32_t secure_scratch116;                 /* _SECURE_SCRATCH116_0,            0xb28 */
-    uint32_t secure_scratch117;                 /* _SECURE_SCRATCH117_0,            0xb2c */
-    uint32_t secure_scratch118;                 /* _SECURE_SCRATCH118_0,            0xb30 */
-    uint32_t secure_scratch119;                 /* _SECURE_SCRATCH119_0,            0xb34 */
-    uint32_t secure_scratch120;                 /* _SECURE_SCRATCH120_0,            0xb38 */
-    uint32_t secure_scratch121;                 /* _SECURE_SCRATCH121_0,            0xb3c */
-    uint32_t secure_scratch122;                 /* _SECURE_SCRATCH122_0,            0xb40 */
-    uint32_t secure_scratch123;                 /* _SECURE_SCRATCH123_0,            0xb44 */
-    uint32_t led_breathing_ctrl;                /* _LED_BREATHING_CTRL_0,           0xb48 */
-    uint32_t led_breathing_counter0;            /* _LED_BREATHING_COUNTER0_0,       0xb4c */
-    uint32_t led_breathing_counter1;            /* _LED_BREATHING_COUNTER1_0,       0xb50 */
-    uint32_t led_breathing_counter2;            /* _LED_BREATHING_COUNTER2_0,       0xb54 */
-    uint32_t led_breathing_counter3;            /* _LED_BREATHING_COUNTER3_0,       0xb58 */
-    uint32_t led_breathing_status;              /* _LED_BREATHING_STATUS_0,         0xb5c */
-    uint32_t _0xb60[2];
-    uint32_t secure_scratch124;                 /* _SECURE_SCRATCH124_0,            0xb68 */
-    uint32_t secure_scratch125;                 /* _SECURE_SCRATCH125_0,            0xb6c */
-    uint32_t secure_scratch126;                 /* _SECURE_SCRATCH126_0,            0xb70 */
-    uint32_t secure_scratch127;                 /* _SECURE_SCRATCH127_0,            0xb74 */
-    uint32_t secure_scratch128;                 /* _SECURE_SCRATCH128_0,            0xb78 */
-    uint32_t secure_scratch129;                 /* _SECURE_SCRATCH129_0,            0xb7c */
-    uint32_t secure_scratch130;                 /* _SECURE_SCRATCH130_0,            0xb80 */
-    uint32_t secure_scratch131;                 /* _SECURE_SCRATCH131_0,            0xb84 */
-    uint32_t secure_scratch132;                 /* _SECURE_SCRATCH132_0,            0xb88 */
-    uint32_t secure_scratch133;                 /* _SECURE_SCRATCH133_0,            0xb8c */
-    uint32_t secure_scratch134;                 /* _SECURE_SCRATCH134_0,            0xb90 */
-    uint32_t secure_scratch135;                 /* _SECURE_SCRATCH135_0,            0xb94 */
-    uint32_t secure_scratch136;                 /* _SECURE_SCRATCH136_0,            0xb98 */
-    uint32_t secure_scratch137;                 /* _SECURE_SCRATCH137_0,            0xb9c */
-    uint32_t secure_scratch138;                 /* _SECURE_SCRATCH138_0,            0xba0 */
-    uint32_t secure_scratch139;                 /* _SECURE_SCRATCH139_0,            0xba4 */
-    uint32_t _0xba8[2];
-    uint32_t sec_disable_ns;                    /* _SEC_DISABLE_NS_0,               0xbb0 */
-    uint32_t sec_disable2_ns;                   /* _SEC_DISABLE2_NS_0,              0xbb4 */
-    uint32_t sec_disable3_ns;                   /* _SEC_DISABLE3_NS_0,              0xbb8 */
-    uint32_t sec_disable4_ns;                   /* _SEC_DISABLE4_NS_0,              0xbbc */
-    uint32_t sec_disable5_ns;                   /* _SEC_DISABLE5_NS_0,              0xbc0 */
-    uint32_t sec_disable6_ns;                   /* _SEC_DISABLE6_NS_0,              0xbc4 */
-    uint32_t sec_disable7_ns;                   /* _SEC_DISABLE7_NS_0,              0xbc8 */
-    uint32_t sec_disable8_ns;                   /* _SEC_DISABLE8_NS_0,              0xbcc */
-    uint32_t sec_disable9_ns;                   /* _SEC_DISABLE9_NS_0,              0xbd0 */
-    uint32_t sec_disable10_ns;                  /* _SEC_DISABLE10_NS_0,             0xbd4 */
-    uint32_t _0xbd8[4];
-    uint32_t tzram_pwr_cntrl;                   /* _TZRAM_PWR_CNTRL_0,              0xbe8 */
-    uint32_t tzram_sec_disable;                 /* _TZRAM_SEC_DISABLE_0,            0xbec */
-    uint32_t tzram_non_sec_disable;             /* _TZRAM_NON_SEC_DISABLE_0,        0xbf0 */
-} tegra_pmc_t;
-
-static inline volatile tegra_pmc_t *pmc_get_regs(void)
-{
-    return (volatile tegra_pmc_t *)PMC_BASE;
-}
-
-#endif

fusee/fusee-mtc/src/start.s

@@ -1,70 +0,0 @@
-/*
- * Copyright (c) 2018 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-.macro CLEAR_GPR_REG_ITER
-    mov r\@, #0
-.endm
-
-.section .text.start, "ax", %progbits
-.arm
-.align 5
-.global _start
-.type   _start, %function
-_start:
-    /* Switch to system mode, mask all interrupts, clear all flags */
-    msr cpsr_cxsf, #0xDF
-    
-    /* Backup current stack pointer. */
-    mov r12, sp
-    
-    /* Set the stack pointer */
-    ldr  sp, =__stack_top__
-    mov  fp, #0
-    
-    /* Save context */
-    push {r12, lr}
-    
-    /* Call init. */
-    bl  __program_init
-
-    /* Set r0 to r12 to 0 (for debugging) & call main */
-    .rept 13
-    CLEAR_GPR_REG_ITER
-    .endr
-    ldr r0, =__program_argc
-    ldr r1, =__program_argv
-    ldr r0, [r0]
-    ldr r1, [r1]
-    bl   main
-    
-    /* Save result. */
-    push {r0}
-    
-    /* Exit manually. */
-    bl  __program_exit
-    
-    /* Restore result. */
-    pop {r0}
-
-    /* Restore context */
-    pop {r12}
-    pop {lr}
-    
-    /* Restore previous stack pointer. */
-    mov sp, r12
-    
-    /* Return */
-    bx lr

fusee/fusee-mtc/src/timers.h

@@ -1,94 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_TIMERS_H
-#define FUSEE_TIMERS_H
-
-#include "utils.h"
-
-#define TIMERS_BASE 0x60005000
-#define MAKE_TIMERS_REG(n) MAKE_REG32(TIMERS_BASE + n)
-
-#define TIMERUS_CNTR_1US_0 MAKE_TIMERS_REG(0x10)
-#define TIMERUS_USEC_CFG_0 MAKE_TIMERS_REG(0x14)
-#define SHARED_INTR_STATUS_0 MAKE_TIMERS_REG(0x1A0)
-#define SHARED_TIMER_SECURE_CFG_0 MAKE_TIMERS_REG(0x1A4)
-
-#define RTC_BASE 0x7000E000
-#define MAKE_RTC_REG(n) MAKE_REG32(RTC_BASE + n)
-
-#define RTC_SECONDS MAKE_RTC_REG(0x08)
-#define RTC_SHADOW_SECONDS MAKE_RTC_REG(0x0C)
-#define RTC_MILLI_SECONDS MAKE_RTC_REG(0x10)
-
-typedef struct {
-    uint32_t CONFIG;
-    uint32_t STATUS;
-    uint32_t COMMAND;
-    uint32_t PATTERN;
-} watchdog_timers_t;
-
-#define GET_WDT(n) ((volatile watchdog_timers_t *)(TIMERS_BASE + 0x100 + 0x20 * n))
-#define WDT_REBOOT_PATTERN 0xC45A
-#define GET_WDT_REBOOT_CFG_REG(n) MAKE_REG32(TIMERS_BASE + 0x60 + 0x8 * n)
-
-void wait(uint32_t microseconds);
-
-static inline uint32_t get_time_s(void) {
-    return RTC_SECONDS;
-}
-
-static inline uint32_t get_time_ms(void) {
-    return (RTC_MILLI_SECONDS | (RTC_SHADOW_SECONDS << 10));
-}
-
-static inline uint32_t get_time_us(void) {
-    return TIMERUS_CNTR_1US_0;
-}
-
-/**
- * Returns the time in microseconds.
- */
-static inline uint32_t get_time(void) {
-    return get_time_us();
-}
-
-/**
- * Returns the number of microseconds that have passed since a given get_time().
- */
-static inline uint32_t get_time_since(uint32_t base) {
-    return get_time_us() - base;
-}
-
-/**
- * Delays for a given number of microseconds.
- */
-static inline void udelay(uint32_t usecs) {
-    uint32_t start = get_time_us();
-    while (get_time_us() - start < usecs);
-}
-
-/**
- * Delays for a given number of milliseconds.
- */
-static inline void mdelay(uint32_t msecs) {
-    uint32_t start = get_time_ms();
-    while (get_time_ms() - start < msecs);
-}
-
-__attribute__ ((noreturn)) void watchdog_reboot(void);
-
-#endif

fusee/fusee-mtc/src/utils.c

@@ -1,49 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#include <stdbool.h>
-#include <stdarg.h>
-#include "utils.h"
-#include "../../../fusee/common/display/video_fb.h"
-#include "../../../fusee/common/log.h"
-
-__attribute__ ((noreturn)) void generic_panic(void) {
-    while (true) {
-        /* Lock. */
-    }
-}
-
-__attribute__((noreturn)) void fatal_error(const char *fmt, ...) {
-    /* Forcefully initialize the screen if logging is disabled. */
-    if (log_get_log_level() == SCREEN_LOG_LEVEL_NONE) {
-        /* Zero-fill the framebuffer and register it as printk provider. */
-        video_init((void *)0xC0000000);
-        
-        /* Override the global logging level. */
-        log_set_log_level(SCREEN_LOG_LEVEL_ERROR);
-    }
-    
-    /* Display fatal error. */
-    va_list args;
-    print(SCREEN_LOG_LEVEL_ERROR, "Fatal error: ");
-    va_start(args, fmt);
-    vprint(SCREEN_LOG_LEVEL_ERROR, fmt, args);
-    va_end(args);
-    
-    while (true) {
-        /* Lock. */
-    }
-}

fusee/fusee-mtc/src/utils.h

@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2018-2020 Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
- 
-#ifndef FUSEE_UTILS_H
-#define FUSEE_UTILS_H
-
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <string.h>
-
-#define BIT(n)      (1u   << (n))
-#define BITL(n)     (1ull << (n))
-#define MASK(n)     (BIT(n) - 1)
-#define MASKL(n)    (BITL(n) - 1)
-#define MASK2(a,b)  (MASK(a) & ~MASK(b))
-#define MASK2L(a,b) (MASKL(a) & ~MASKL(b))
-
-#define MAKE_REG32(a)   (*(volatile uint32_t *)(a))
-
-#define ALIGN(m)        __attribute__((aligned(m)))
-#define PACKED          __attribute__((packed))
-
-#define ALINLINE        __attribute__((always_inline))
-#define NOINLINE        __attribute__((noinline))
-
-__attribute__((noreturn)) void generic_panic(void);
-__attribute__((noreturn)) void fatal_error(const char *fmt, ...);
-
-#endif