4 Commits

Author	SHA1	Message	Date
TuxSH	6be5b0a52f	Implement flush_dcache_all_tzram_pa and invalidate_icache_all_inner_shareable_tzram_pa for the crt0s	2018-02-28 19:06:41 +01:00
Michael Scire	c18af9f3d2	Finish smcCpuOff	2018-02-27 16:35:35 -08:00
Michael Scire	7a9e031bff	Uncomment more sleep/suspend code	2018-02-27 16:10:51 -08:00
TuxSH	602507ee8f	Rename cache.s/.h to arm.s/.h	2018-02-27 22:29:47 +01:00