git subrepo pull emummc
subrepo: subdir: "emummc" merged: "25075973" upstream: origin: "https://github.com/m4xw/emuMMC" branch: "develop" commit: "25075973" git-subrepo: version: "0.4.1" origin: "???" commit: "???"
This commit is contained in:
Michael Scire
@@ -1,5 +1,6 @@
|
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2020 CTCaer
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*
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||||
* This program is free software; you can redistribute it and/or modify it
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||||
* under the terms and conditions of the GNU General Public License,
|
||||
@@ -410,7 +411,7 @@ void clock_sdmmc_get_card_clock_div(u32 *pclock, u16 *pdivisor, u32 type)
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*pclock = 40800;
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*pdivisor = 1;
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break;
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case SDHCI_TIMING_MMC_DDR52: // Actual IO Freq: 49.92 MHz.
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case SDHCI_TIMING_MMC_HS102: // Actual IO Freq: 99.84 MHz.
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*pclock = 200000;
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*pdivisor = 2;
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break;
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@@ -1,5 +1,6 @@
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/*
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||||
* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2020 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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||||
* under the terms and conditions of the GNU General Public License,
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||||
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||||
@@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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||||
* under the terms and conditions of the GNU General Public License,
|
||||
@@ -17,78 +18,151 @@
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#include "../soc/gpio.h"
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#include "../soc/t210.h"
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static const u16 _gpio_cnf[31] = {
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0x000, 0x004, 0x008, 0x00C,
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0x100, 0x104, 0x108, 0x10C,
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0x200, 0x204, 0x208, 0x20C,
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0x300, 0x304, 0x308, 0x30C,
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0x400, 0x404, 0x408, 0x40C,
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0x500, 0x504, 0x508, 0x50C,
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0x600, 0x604, 0x608, 0x60C,
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0x700, 0x704, 0x708
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};
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#define GPIO_BANK_IDX(port) ((port) >> 2)
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static const u16 _gpio_oe[31] = {
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0x010, 0x014, 0x018, 0x01C,
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0x110, 0x114, 0x118, 0x11C,
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0x210, 0x214, 0x218, 0x21C,
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0x310, 0x314, 0x318, 0x31C,
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0x410, 0x414, 0x418, 0x41C,
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0x510, 0x514, 0x518, 0x51C,
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0x610, 0x614, 0x618, 0x61C,
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0x710, 0x714, 0x718
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};
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#define GPIO_CNF_OFFSET(port) (0x00 + (((port) >> 2) << 8) + (((port) % 4) << 2))
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#define GPIO_OE_OFFSET(port) (0x10 + (((port) >> 2) << 8) + (((port) % 4) << 2))
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#define GPIO_OUT_OFFSET(port) (0x20 + (((port) >> 2) << 8) + (((port) % 4) << 2))
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#define GPIO_IN_OFFSET(port) (0x30 + (((port) >> 2) << 8) + (((port) % 4) << 2))
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#define GPIO_INT_STA_OFFSET(port) (0x40 + (((port) >> 2) << 8) + (((port) % 4) << 2))
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#define GPIO_INT_ENB_OFFSET(port) (0x50 + (((port) >> 2) << 8) + (((port) % 4) << 2))
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#define GPIO_INT_LVL_OFFSET(port) (0x60 + (((port) >> 2) << 8) + (((port) % 4) << 2))
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#define GPIO_INT_CLR_OFFSET(port) (0x70 + (((port) >> 2) << 8) + (((port) % 4) << 2))
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static const u16 _gpio_out[31] = {
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0x020, 0x024, 0x028, 0x02C,
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0x120, 0x124, 0x128, 0x12C,
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0x220, 0x224, 0x228, 0x22C,
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0x320, 0x324, 0x328, 0x32C,
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0x420, 0x424, 0x428, 0x42C,
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0x520, 0x524, 0x528, 0x52C,
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0x620, 0x624, 0x628, 0x62C,
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0x720, 0x724, 0x728
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};
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#define GPIO_CNF_MASKED_OFFSET(port) (0x80 + (((port) >> 2) << 8) + (((port) % 4) << 2))
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#define GPIO_OE_MASKED_OFFSET(port) (0x90 + (((port) >> 2) << 8) + (((port) % 4) << 2))
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#define GPIO_OUT_MASKED_OFFSET(port) (0xA0 + (((port) >> 2) << 8) + (((port) % 4) << 2))
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#define GPIO_INT_STA_MASKED_OFFSET(port) (0xC0 + (((port) >> 2) << 8) + (((port) % 4) << 2))
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#define GPIO_INT_ENB_MASKED_OFFSET(port) (0xD0 + (((port) >> 2) << 8) + (((port) % 4) << 2))
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#define GPIO_INT_LVL_MASKED_OFFSET(port) (0xE0 + (((port) >> 2) << 8) + (((port) % 4) << 2))
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static const u16 _gpio_in[31] = {
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0x030, 0x034, 0x038, 0x03C,
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0x130, 0x134, 0x138, 0x13C,
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0x230, 0x234, 0x238, 0x23C,
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0x330, 0x334, 0x338, 0x33C,
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0x430, 0x434, 0x438, 0x43C,
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0x530, 0x534, 0x538, 0x53C,
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0x630, 0x634, 0x638, 0x63C,
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0x730, 0x734, 0x738
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#define GPIO_IRQ_BANK1 32
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#define GPIO_IRQ_BANK2 33
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#define GPIO_IRQ_BANK3 34
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#define GPIO_IRQ_BANK4 35
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#define GPIO_IRQ_BANK5 55
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#define GPIO_IRQ_BANK6 87
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#define GPIO_IRQ_BANK7 89
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#define GPIO_IRQ_BANK8 125
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static u8 gpio_bank_irq_ids[8] = {
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GPIO_IRQ_BANK1, GPIO_IRQ_BANK2, GPIO_IRQ_BANK3, GPIO_IRQ_BANK4,
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GPIO_IRQ_BANK5, GPIO_IRQ_BANK6, GPIO_IRQ_BANK7, GPIO_IRQ_BANK8
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};
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void gpio_config(u32 port, u32 pins, int mode)
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{
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u32 offset = GPIO_CNF_OFFSET(port);
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if (mode)
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GPIO(_gpio_cnf[port]) |= pins;
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GPIO(offset) |= pins;
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else
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GPIO(_gpio_cnf[port]) &= ~pins;
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(void)GPIO(_gpio_cnf[port]);
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GPIO(offset) &= ~pins;
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(void)GPIO(offset); // Commit the write.
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}
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void gpio_output_enable(u32 port, u32 pins, int enable)
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{
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u32 port_offset = GPIO_OE_OFFSET(port);
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if (enable)
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GPIO(_gpio_oe[port]) |= pins;
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GPIO(port_offset) |= pins;
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else
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GPIO(_gpio_oe[port]) &= ~pins;
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(void)GPIO(_gpio_oe[port]);
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GPIO(port_offset) &= ~pins;
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(void)GPIO(port_offset); // Commit the write.
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}
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void gpio_write(u32 port, u32 pins, int high)
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{
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u32 port_offset = GPIO_OUT_OFFSET(port);
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if (high)
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GPIO(_gpio_out[port]) |= pins;
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GPIO(port_offset) |= pins;
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else
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GPIO(_gpio_out[port]) &= ~pins;
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(void)GPIO(_gpio_out[port]);
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GPIO(port_offset) &= ~pins;
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(void)GPIO(port_offset); // Commit the write.
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}
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int gpio_read(u32 port, u32 pins)
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{
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return (GPIO(_gpio_in[port]) & pins) ? 1 : 0;
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u32 port_offset = GPIO_IN_OFFSET(port);
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return (GPIO(port_offset) & pins) ? 1 : 0;
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}
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static void _gpio_interrupt_clear(u32 port, u32 pins)
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{
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u32 port_offset = GPIO_INT_CLR_OFFSET(port);
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GPIO(port_offset) |= pins;
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(void)GPIO(port_offset); // Commit the write.
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}
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int gpio_interrupt_status(u32 port, u32 pins)
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{
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u32 port_offset = GPIO_INT_STA_OFFSET(port);
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u32 enabled = GPIO(GPIO_INT_ENB_OFFSET(port)) & pins;
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int status = ((GPIO(port_offset) & pins) && enabled) ? 1 : 0;
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// Clear the interrupt status.
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if (status)
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_gpio_interrupt_clear(port, pins);
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return status;
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}
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void gpio_interrupt_enable(u32 port, u32 pins, int enable)
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{
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u32 port_offset = GPIO_INT_ENB_OFFSET(port);
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// Clear any possible stray interrupt.
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_gpio_interrupt_clear(port, pins);
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if (enable)
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GPIO(port_offset) |= pins;
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else
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GPIO(port_offset) &= ~pins;
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(void)GPIO(port_offset); // Commit the write.
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}
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void gpio_interrupt_level(u32 port, u32 pins, int high, int edge, int delta)
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{
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u32 port_offset = GPIO_INT_LVL_OFFSET(port);
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u32 val = GPIO(port_offset);
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if (high)
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val |= pins;
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else
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val &= ~pins;
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if (edge)
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val |= pins << 8;
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else
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val &= ~(pins << 8);
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if (delta)
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val |= pins << 16;
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else
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val &= ~(pins << 16);
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GPIO(port_offset) = val;
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(void)GPIO(port_offset); // Commit the write.
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// Clear any possible stray interrupt.
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_gpio_interrupt_clear(port, pins);
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}
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u32 gpio_get_bank_irq_id(u32 port)
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{
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u32 bank_idx = GPIO_BANK_IDX(port);
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return gpio_bank_irq_ids[bank_idx];
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}
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@@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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||||
* under the terms and conditions of the GNU General Public License,
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@@ -21,10 +22,23 @@
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#define GPIO_MODE_SPIO 0
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#define GPIO_MODE_GPIO 1
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#define GPIO_OUTPUT_DISABLE 0
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#define GPIO_OUTPUT_ENABLE 1
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#define GPIO_IRQ_DISABLE 0
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#define GPIO_IRQ_ENABLE 1
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#define GPIO_LOW 0
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#define GPIO_HIGH 1
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#define GPIO_FALLING 0
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#define GPIO_RISING 1
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#define GPIO_LEVEL 0
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#define GPIO_EDGE 1
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#define GPIO_CONFIGURED_EDGE 0
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#define GPIO_ANY_EDGE_CHANGE 1
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/*! GPIO pins (0-7 for each port). */
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#define GPIO_PIN_0 (1 << 0)
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@@ -72,6 +86,10 @@
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void gpio_config(u32 port, u32 pins, int mode);
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void gpio_output_enable(u32 port, u32 pins, int enable);
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void gpio_write(u32 port, u32 pins, int high);
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int gpio_read(u32 port, u32 pins);
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int gpio_read(u32 port, u32 pins);
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int gpio_interrupt_status(u32 port, u32 pins);
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void gpio_interrupt_enable(u32 port, u32 pins, int enable);
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void gpio_interrupt_level(u32 port, u32 pins, int high, int edge, int delta);
|
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u32 gpio_get_bank_irq_id(u32 port);
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#endif
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@@ -1,5 +1,6 @@
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/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018-2020 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
@@ -20,25 +21,88 @@
|
||||
#include "../utils/util.h"
|
||||
#include "t210.h"
|
||||
|
||||
// TODO: not hardcode I2C_5
|
||||
static u64 i2c_addrs[] = {
|
||||
0x7000C000, 0x7000C400, 0x7000C500,
|
||||
0x7000C700, 0x7000D000, 0x7000D100
|
||||
#define I2C_PACKET_PROT_I2C (1 << 4)
|
||||
#define I2C_HEADER_CONT_XFER (1 << 15)
|
||||
#define I2C_HEADER_REP_START (1 << 16)
|
||||
#define I2C_HEADER_IE_ENABLE (1 << 17)
|
||||
#define I2C_HEADER_READ (1 << 19)
|
||||
|
||||
#define I2C_CNFG (0x00 / 4)
|
||||
#define CMD1_WRITE (0 << 6)
|
||||
#define CMD1_READ (1 << 6)
|
||||
#define NORMAL_MODE_GO (1 << 9)
|
||||
#define PACKET_MODE_GO (1 << 10)
|
||||
#define NEW_MASTER_FSM (1 << 11)
|
||||
#define DEBOUNCE_CNT_4T (2 << 12)
|
||||
|
||||
#define I2C_CMD_ADDR0 (0x04 / 4)
|
||||
#define ADDR0_WRITE 0
|
||||
#define ADDR0_READ 1
|
||||
|
||||
#define I2C_CMD_DATA1 (0x0C / 4)
|
||||
#define I2C_CMD_DATA2 (0x10 / 4)
|
||||
|
||||
#define I2C_STATUS (0x1C / 4)
|
||||
#define I2C_STATUS_NOACK (0xF << 0)
|
||||
#define I2C_STATUS_BUSY (1 << 8)
|
||||
|
||||
#define I2C_TX_FIFO (0x50 / 4)
|
||||
#define I2C_RX_FIFO (0x54 / 4)
|
||||
|
||||
#define I2C_FIFO_CONTROL (0x5C / 4)
|
||||
#define RX_FIFO_FLUSH (1 << 0)
|
||||
#define TX_FIFO_FLUSH (1 << 1)
|
||||
|
||||
#define I2C_FIFO_STATUS (0x60 / 4)
|
||||
#define RX_FIFO_FULL_CNT (0xF << 0)
|
||||
#define TX_FIFO_EMPTY_CNT (0xF << 4)
|
||||
|
||||
#define I2C_INT_EN (0x64 / 4)
|
||||
#define I2C_INT_STATUS (0x68 / 4)
|
||||
#define I2C_INT_SOURCE (0x70 / 4)
|
||||
#define RX_FIFO_DATA_REQ (1 << 0)
|
||||
#define TX_FIFO_DATA_REQ (1 << 1)
|
||||
#define ARB_LOST (1 << 2)
|
||||
#define NO_ACK (1 << 3)
|
||||
#define RX_FIFO_UNDER (1 << 4)
|
||||
#define TX_FIFO_OVER (1 << 5)
|
||||
#define ALL_PACKETS_COMPLETE (1 << 6)
|
||||
#define PACKET_COMPLETE (1 << 7)
|
||||
#define BUS_CLEAR_DONE (1 << 11)
|
||||
|
||||
#define I2C_CLK_DIVISOR (0x6C / 4)
|
||||
|
||||
#define I2C_BUS_CLEAR_CONFIG (0x84 / 4)
|
||||
#define BC_ENABLE (1 << 0)
|
||||
#define BC_TERMINATE (1 << 1)
|
||||
|
||||
#define I2C_BUS_CLEAR_STATUS (0x88 / 4)
|
||||
|
||||
#define I2C_CONFIG_LOAD (0x8C / 4)
|
||||
#define MSTR_CONFIG_LOAD (1 << 0)
|
||||
#define TIMEOUT_CONFIG_LOAD (1 << 2)
|
||||
|
||||
static const u64 i2c_addrs[] = {
|
||||
0x7000C000, // I2C_1.
|
||||
0x7000C400, // I2C_2.
|
||||
0x7000C500, // I2C_3.
|
||||
0x7000C700, // I2C_4.
|
||||
0x7000D000, // I2C_5.
|
||||
0x7000D100 // I2C_6.
|
||||
};
|
||||
|
||||
static void _i2c_wait(vu32 *base)
|
||||
static void _i2c_load_cfg_wait(vu32 *base)
|
||||
{
|
||||
base[I2C_CONFIG_LOAD] = 0x25;
|
||||
|
||||
base[I2C_CONFIG_LOAD] = (1 << 5) | TIMEOUT_CONFIG_LOAD | MSTR_CONFIG_LOAD;
|
||||
for (u32 i = 0; i < 20; i++)
|
||||
{
|
||||
usleep(1);
|
||||
if (!(base[I2C_CONFIG_LOAD] & 1))
|
||||
if (!(base[I2C_CONFIG_LOAD] & MSTR_CONFIG_LOAD))
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int _i2c_send_pkt(u32 idx, u32 x, u8 *buf, u32 size)
|
||||
static int _i2c_send_single(u32 i2c_idx, u32 dev_addr, u8 *buf, u32 size)
|
||||
{
|
||||
if (size > 4)
|
||||
return 0;
|
||||
@@ -47,46 +111,58 @@ static int _i2c_send_pkt(u32 idx, u32 x, u8 *buf, u32 size)
|
||||
memcpy(&tmp, buf, size);
|
||||
|
||||
vu32 *base = (vu32 *)QueryIoMapping(i2c_addrs[I2C_5], 0x1000);
|
||||
base[I2C_CMD_ADDR0] = x << 1; //Set x (send mode).
|
||||
|
||||
// Set device address and send mode.
|
||||
base[I2C_CMD_ADDR0] = dev_addr << 1 | ADDR0_WRITE;
|
||||
base[I2C_CMD_DATA1] = tmp; //Set value.
|
||||
base[I2C_CNFG] = ((size - 1) << 1) | 0x2800; //Set size and send mode.
|
||||
_i2c_wait(base); //Kick transaction.
|
||||
// Set size and send mode.
|
||||
base[I2C_CNFG] = ((size - 1) << 1) | DEBOUNCE_CNT_4T | NEW_MASTER_FSM | CMD1_WRITE;
|
||||
|
||||
base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFFDFF) | 0x200;
|
||||
// Load configuration.
|
||||
_i2c_load_cfg_wait(base);
|
||||
|
||||
u32 timeout = get_tmr_ms() + 1500;
|
||||
while (base[I2C_STATUS] & 0x100)
|
||||
// Initiate transaction on normal mode.
|
||||
base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFF9FF) | NORMAL_MODE_GO;
|
||||
|
||||
u64 timeout = get_tmr_ms() + 100;
|
||||
while (base[I2C_STATUS] & I2C_STATUS_BUSY)
|
||||
{
|
||||
if (get_tmr_ms() > timeout)
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (base[I2C_STATUS] << 28)
|
||||
if (base[I2C_STATUS] & I2C_STATUS_NOACK)
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int _i2c_recv_pkt(u32 idx, u8 *buf, u32 size, u32 x)
|
||||
static int _i2c_recv_single(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr)
|
||||
{
|
||||
if (size > 8)
|
||||
if (size > 4)
|
||||
return 0;
|
||||
|
||||
vu32 *base = (vu32 *)QueryIoMapping(i2c_addrs[I2C_5], 0x1000);
|
||||
base[I2C_CMD_ADDR0] = (x << 1) | 1; // Set x (recv mode).
|
||||
base[I2C_CNFG] = ((size - 1) << 1) | 0x2840; // Set size and recv mode.
|
||||
_i2c_wait(base); // Kick transaction.
|
||||
// Set device address and recv mode.
|
||||
base[I2C_CMD_ADDR0] = (dev_addr << 1) | ADDR0_READ;
|
||||
|
||||
base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFFDFF) | 0x200;
|
||||
// Set size and recv mode.
|
||||
base[I2C_CNFG] = ((size - 1) << 1) | DEBOUNCE_CNT_4T | NEW_MASTER_FSM | CMD1_READ;
|
||||
|
||||
u32 timeout = get_tmr_ms() + 1500;
|
||||
while (base[I2C_STATUS] & 0x100)
|
||||
// Load configuration.
|
||||
_i2c_load_cfg_wait(base);
|
||||
|
||||
// Initiate transaction on normal mode.
|
||||
base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFF9FF) | NORMAL_MODE_GO;
|
||||
|
||||
u64 timeout = get_tmr_ms() + 100;
|
||||
while (base[I2C_STATUS] & I2C_STATUS_BUSY)
|
||||
{
|
||||
if (get_tmr_ms() > timeout)
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (base[I2C_STATUS] << 28)
|
||||
if (base[I2C_STATUS] & I2C_STATUS_NOACK)
|
||||
return 0;
|
||||
|
||||
u32 tmp = base[I2C_CMD_DATA1]; // Get LS value.
|
||||
@@ -106,50 +182,52 @@ void i2c_init()
|
||||
{
|
||||
vu32 *base = (vu32 *)QueryIoMapping(i2c_addrs[I2C_5], 0x1000);
|
||||
|
||||
base[I2C_CLK_DIVISOR_REGISTER] = 0x50001;
|
||||
base[I2C_BUS_CLEAR_CONFIG] = 0x90003;
|
||||
_i2c_wait(base);
|
||||
base[I2C_CLK_DIVISOR] = (5 << 16) | 1; // SF mode Div: 6, HS mode div: 2.
|
||||
base[I2C_BUS_CLEAR_CONFIG] = (9 << 16) | BC_TERMINATE | BC_ENABLE;
|
||||
|
||||
// Load configuration.
|
||||
_i2c_load_cfg_wait(base);
|
||||
|
||||
for (u32 i = 0; i < 10; i++)
|
||||
{
|
||||
if (base[INTERRUPT_STATUS_REGISTER] & 0x800)
|
||||
if (base[I2C_INT_STATUS] & BUS_CLEAR_DONE)
|
||||
break;
|
||||
}
|
||||
|
||||
(vu32)base[I2C_BUS_CLEAR_STATUS];
|
||||
base[INTERRUPT_STATUS_REGISTER] = base[INTERRUPT_STATUS_REGISTER];
|
||||
base[I2C_INT_STATUS] = base[I2C_INT_STATUS];
|
||||
}
|
||||
|
||||
int i2c_send_buf_small(u32 idx, u32 x, u32 y, u8 *buf, u32 size)
|
||||
int i2c_send_buf_small(u32 i2c_idx, u32 dev_addr, u32 reg, u8 *buf, u32 size)
|
||||
{
|
||||
u8 tmp[4];
|
||||
|
||||
if (size > 3)
|
||||
return 0;
|
||||
|
||||
tmp[0] = y;
|
||||
tmp[0] = reg;
|
||||
memcpy(tmp + 1, buf, size);
|
||||
|
||||
return _i2c_send_pkt(idx, x, tmp, size + 1);
|
||||
return _i2c_send_single(i2c_idx, dev_addr, tmp, size + 1);
|
||||
}
|
||||
|
||||
int i2c_recv_buf_small(u8 *buf, u32 size, u32 idx, u32 x, u32 y)
|
||||
int i2c_recv_buf_small(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr, u32 reg)
|
||||
{
|
||||
int res = _i2c_send_pkt(idx, x, (u8 *)&y, 1);
|
||||
int res = _i2c_send_single(i2c_idx, dev_addr, (u8 *)®, 1);
|
||||
if (res)
|
||||
res = _i2c_recv_pkt(idx, buf, size, x);
|
||||
res = _i2c_recv_single(i2c_idx, buf, size, dev_addr);
|
||||
return res;
|
||||
}
|
||||
|
||||
int i2c_send_byte(u32 idx, u32 x, u32 y, u8 b)
|
||||
int i2c_send_byte(u32 i2c_idx, u32 dev_addr, u32 reg, u8 val)
|
||||
{
|
||||
return i2c_send_buf_small(idx, x, y, &b, 1);
|
||||
return i2c_send_buf_small(i2c_idx, dev_addr, reg, &val, 1);
|
||||
}
|
||||
|
||||
u8 i2c_recv_byte(u32 idx, u32 x, u32 y)
|
||||
u8 i2c_recv_byte(u32 i2c_idx, u32 dev_addr, u32 reg)
|
||||
{
|
||||
u8 tmp = 0;
|
||||
i2c_recv_buf_small(&tmp, 1, idx, x, y);
|
||||
i2c_recv_buf_small(&tmp, 1, i2c_idx, dev_addr, reg);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
|
||||
@@ -1,5 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2020 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
@@ -26,21 +27,10 @@
|
||||
#define I2C_5 4
|
||||
#define I2C_6 5
|
||||
|
||||
#define I2C_CNFG 0x00
|
||||
#define I2C_CMD_ADDR0 0x01
|
||||
#define I2C_CMD_DATA1 0x03
|
||||
#define I2C_CMD_DATA2 0x04
|
||||
#define I2C_STATUS 0x07
|
||||
#define INTERRUPT_STATUS_REGISTER 0x1A
|
||||
#define I2C_CLK_DIVISOR_REGISTER 0x1B
|
||||
#define I2C_BUS_CLEAR_CONFIG 0x21
|
||||
#define I2C_BUS_CLEAR_STATUS 0x22
|
||||
#define I2C_CONFIG_LOAD 0x23
|
||||
|
||||
void i2c_init();
|
||||
int i2c_send_buf_small(u32 idx, u32 x, u32 y, u8 *buf, u32 size);
|
||||
int i2c_recv_buf_small(u8 *buf, u32 size, u32 idx, u32 x, u32 y);
|
||||
int i2c_send_byte(u32 idx, u32 x, u32 y, u8 b);
|
||||
u8 i2c_recv_byte(u32 idx, u32 x, u32 y);
|
||||
int i2c_send_buf_small(u32 i2c_idx, u32 dev_addr, u32 reg, u8 *buf, u32 size);
|
||||
int i2c_recv_buf_small(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr, u32 reg);
|
||||
int i2c_send_byte(u32 i2c_idx, u32 dev_addr, u32 reg, u8 val);
|
||||
u8 i2c_recv_byte(u32 i2c_idx, u32 dev_addr, u32 reg);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -51,6 +51,18 @@
|
||||
#define PINMUX_AUX_GPIO_PE6 0x248
|
||||
#define PINMUX_AUX_GPIO_PH6 0x250
|
||||
#define PINMUX_AUX_GPIO_PZ1 0x280
|
||||
/* Only in T210B01 */
|
||||
#define PINMUX_AUX_SDMMC2_DAT0 0x294
|
||||
#define PINMUX_AUX_SDMMC2_DAT1 0x298
|
||||
#define PINMUX_AUX_SDMMC2_DAT2 0x29C
|
||||
#define PINMUX_AUX_SDMMC2_DAT3 0x2A0
|
||||
#define PINMUX_AUX_SDMMC2_DAT4 0x2A4
|
||||
#define PINMUX_AUX_SDMMC2_DAT5 0x2A8
|
||||
#define PINMUX_AUX_SDMMC2_DAT6 0x2AC
|
||||
#define PINMUX_AUX_SDMMC2_DAT7 0x2B0
|
||||
#define PINMUX_AUX_SDMMC2_CLK 0x2B4
|
||||
#define PINMUX_AUX_SDMMC2_CMD 0x2BC
|
||||
|
||||
/*! 0:UART-A, 1:UART-B, 3:UART-C, 3:UART-D */
|
||||
#define PINMUX_AUX_UARTX_TX(x) (0xE4 + 0x10 * (x))
|
||||
#define PINMUX_AUX_UARTX_RX(x) (0xE8 + 0x10 * (x))
|
||||
@@ -78,7 +90,8 @@
|
||||
#define PINMUX_OPEN_DRAIN (1 << 11)
|
||||
#define PINMUX_SCHMT (1 << 12)
|
||||
|
||||
#define PINMUX_DRIVE_1X (0 << 13)
|
||||
#define PINMUX_DRIVE_MASK (3 << 13)
|
||||
#define PINMUX_DRIVE_1X (0 << 13)
|
||||
#define PINMUX_DRIVE_2X (1 << 13)
|
||||
#define PINMUX_DRIVE_3X (2 << 13)
|
||||
#define PINMUX_DRIVE_4X (3 << 13)
|
||||
|
||||
Reference in New Issue
Block a user