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thermosphere: introduce "ENSURE"

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This commit is contained in:
TuxSH
2020-01-25 17:20:43 +00:00
parent d0821a3f50
commit e3961f225c
6 changed files with 47 additions and 51 deletions
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24
thermosphere/src/sysreg_traps.c
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@@ -178,11 +178,13 @@ void handleMcrMrcCP15Trap(ExceptionStackFrame *frame, ExceptionSyndromeRegister
bool isRead = (iss & 1) != 0;
u32 instructionLength = esr.il == 0 ? 2 : 4;
if (LIKELY(opc1 == 0 && CRn == 14 && CRm == 2 && opc2 <= 1)) {
iss = opc2 == 0 ? ENCODE_SYSREG_ISS(CNTP_TVAL_EL0) : ENCODE_SYSREG_ISS(CNTP_CTL_EL0);
} else {
PANIC("handleMcrMrcTrap: unexpected cp15 register, instruction: %s p15, #%u, r%u, c%u, c%u, #%u\n", isRead ? "mrc" : "mcr", opc1, Rt, CRn, CRm, opc2);
}
ENSURE2(
opc1 == 0 && CRn == 14 && CRm == 2 && opc2 <= 1,
"unexpected cp15 register, instruction: %s p15, #%u, r%u, c%u, c%u, #%u\n",
isRead ? "mrc" : "mcr", opc1, Rt, CRn, CRm, opc2
);
iss = opc2 == 0 ? ENCODE_SYSREG_ISS(CNTP_TVAL_EL0) : ENCODE_SYSREG_ISS(CNTP_CTL_EL0);
if (isRead) {
doMrc(frame, iss, instructionLength, Rt);
@@ -209,11 +211,13 @@ void handleMcrrMrrcCP15Trap(ExceptionStackFrame *frame, ExceptionSyndromeRegiste
bool isRead = (iss & 1) != 0;
u32 instructionLength = esr.il == 0 ? 2 : 4;
if (LIKELY(CRm == 14 && (opc1 == 0 || opc1 == 2))) {
iss = opc1 == 0 ? ENCODE_SYSREG_ISS(CNTPCT_EL0) : ENCODE_SYSREG_ISS(CNTP_CVAL_EL0);
} else {
PANIC("handleMcrrMrrcTrap: unexpected cp15 register, instruction: %s p15, #%u, r%u, r%u, c%u\n", isRead ? "mrrc" : "mcrr", opc1, Rt, Rt, CRm);
}
ENSURE2(
CRm == 14 && (opc1 == 0 || opc1 == 2),
"handleMcrrMrrcTrap: unexpected cp15 register, instruction: %s p15, #%u, r%u, r%u, c%u\n",
isRead ? "mrrc" : "mcrr", opc1, Rt, Rt, CRm
);
iss = opc1 == 0 ? ENCODE_SYSREG_ISS(CNTPCT_EL0) : ENCODE_SYSREG_ISS(CNTP_CVAL_EL0);
if (isRead) {
doMrrc(frame, iss, instructionLength, Rt, Rt2);