exo2: implement through boot config load/validate
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@@ -26,7 +26,7 @@ namespace ams::secmon {
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/* Set library register addresses. */
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/* actmon::SetRegisterAddress(MemoryRegionVirtualDeviceActivityMonitor.GetAddress()); */
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clkrst::SetRegisterAddress(MemoryRegionVirtualDeviceClkRst.GetAddress());
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/* flowctrl::SetRegisterAddress(); */
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flow::SetRegisterAddress(MemoryRegionVirtualDeviceFlowController.GetAddress());
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fuse::SetRegisterAddress(MemoryRegionVirtualDeviceFuses.GetAddress());
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gic::SetRegisterAddress(MemoryRegionVirtualDeviceGicDistributor.GetAddress(), MemoryRegionVirtualDeviceGicCpuInterface.GetAddress());
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i2c::SetRegisterAddress(i2c::Port_1, MemoryRegionVirtualDeviceI2c1.GetAddress());
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@@ -69,6 +69,26 @@ namespace ams::secmon {
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/* Initialize the random cache. */
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secmon::smc::FillRandomCache();
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}
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/* Wait for NX Bootloader to finish loading the BootConfig. */
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secmon::boot::WaitForNxBootloader(secmon_params, pkg1::BootloaderState_LoadedBootConfig);
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hw::DataSynchronizationBarrierInnerShareable();
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/* Load the bootconfig. */
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secmon::boot::LoadBootConfig(MemoryRegionPhysicalIramBootConfig.GetPointer());
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/* Verify or clear the boot config. */
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secmon::boot::VerifyOrClearBootConfig();
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/* Get the boot config. */
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const auto &bc = secmon::GetBootConfig();
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/* Set the tsc value by the boot config. */
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{
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constexpr u64 TscMask = (static_cast<u64>(1) << 55) - 1;
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secmon::boot::EnableTsc(bc.data.GetInitialTscValue() & TscMask);
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}
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}
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}
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