OmniNX/Atmosphere
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fusee: SDMMC driver re-design:

Browse Source 
- Based on hekate's, linux's and u-boot's source code;
- Full support for SD and MMC;
- Fixes multiple issues;
- Deployed first in fusee-primary.

fusee: Code cleanup and style fixes.
This commit is contained in:
hexkyz
2018-07-04 21:55:27 +01:00
parent 83c9747e5f
commit ddbbb0b758
30 changed files with 5077 additions and 4709 deletions
Download Patch File Download Diff File Expand all files Collapse all files

149
fusee/fusee-primary/src/gpio.h
View File

@@ -1,19 +1,14 @@
/*
* Struct defintiions lifted from NVIDIA sample code.
* (C) Copyright 2013-2015 NVIDIA Corporation <www.nvidia.com>
*
* adapted for Fusée by Kate Temkin <k@ktemkin.com.
*/
#ifndef FUSEE_GPIO_H
#define FUSEE_GPIO_H
#ifndef __FUSEE_GPIO_H__
#define __FUSEE_GPIO_H__
#include <stdbool.h>
#include <stdint.h>
#include "utils.h"
enum tegra_gpio_port {
#define TEGRA_GPIO_PORTS 4
#define TEGRA_GPIO_BANKS 8
#define GPIO_BANK_SHIFT 5
#define GPIO_PORT_SHIFT 3
#define GPIO_PORT_MASK 0x03
#define GPIO_PIN_MASK 0x07
typedef enum {
TEGRA_GPIO_PORT_A = 0,
TEGRA_GPIO_PORT_B = 1,
TEGRA_GPIO_PORT_C = 2,
@@ -46,25 +41,9 @@ enum tegra_gpio_port {
TEGRA_GPIO_PORT_DD = 29,
TEGRA_GPIO_PORT_EE = 30,
TEGRA_GPIO_PORT_FF = 31,
};
} tegra_gpio_port;
/**
* Convenince macro for computing a GPIO port number.
*/
#define TEGRA_GPIO(port, offset) \
((TEGRA_GPIO_PORT_##port * 8) + offset)
/*
* The Tegra210 GPIO controller has 256 GPIOS in 8 banks of 4 ports,
* each with 8 GPIOs.
*/
enum {
TEGRA_GPIO_PORTS = 4, /* number of ports per bank */
TEGRA_GPIO_BANKS = 8, /* number of banks */
};
/* GPIO Controller registers for a single bank */
struct tegra_gpio_bank {
typedef struct {
uint32_t config[TEGRA_GPIO_PORTS];
uint32_t direction[TEGRA_GPIO_PORTS];
uint32_t out[TEGRA_GPIO_PORTS];
@@ -81,94 +60,40 @@ struct tegra_gpio_bank {
uint32_t masked_int_enable[TEGRA_GPIO_PORTS];
uint32_t masked_int_level[TEGRA_GPIO_PORTS];
uint32_t masked_int_clear[TEGRA_GPIO_PORTS];
};
} tegra_gpio_bank_t;
typedef struct {
tegra_gpio_bank_t bank[TEGRA_GPIO_BANKS];
} tegra_gpio_t;
/**
* Representation of Tegra GPIO controllers.
*/
struct tegra_gpio {
struct tegra_gpio_bank bank[TEGRA_GPIO_BANKS];
};
/**
* GPIO pins that have a more detailed functional name,
* specialized for the Switch.
*/
enum tegra_named_gpio {
GPIO_MICROSD_CARD_DETECT = TEGRA_GPIO(Z, 1),
GPIO_MICROSD_WRITE_PROTECT = TEGRA_GPIO(Z, 4),
GPIO_MICROSD_SUPPLY_ENABLE = TEGRA_GPIO(E, 4),
};
/**
* Mode select for GPIO or SFIO.
*/
enum tegra_gpio_mode {
GPIO_MODE_GPIO = 0,
GPIO_MODE_SFIO = 1
};
/**
* GPIO direction values
*/
enum tegra_gpio_direction {
GPIO_DIRECTION_INPUT = 0,
GPIO_DIRECTION_OUTPUT = 1
};
/**
* Active-high GPIO logic
*/
enum tegra_gpio_value {
GPIO_LEVEL_LOW = 0,
GPIO_LEVEL_HIGH = 1
};
/**
* Utility function that grabs the Tegra pinmux registers.
*/
static inline struct tegra_gpio *gpio_get_regs(void)
static inline volatile tegra_gpio_t *gpio_get_regs(void)
{
return (struct tegra_gpio *)0x6000d000;
return (volatile tegra_gpio_t *)0x6000D000;
}
/**
* Configures a given pin as either GPIO or SFIO.
*
* @param pin The GPIO pin to work with, as created with TEGRA_GPIO, or a named GPIO.
* @param mode The relevant mode.
*/
void gpio_configure_mode(enum tegra_named_gpio pin, enum tegra_gpio_mode mode);
#define TEGRA_GPIO(port, offset) \
((TEGRA_GPIO_PORT_##port * 8) + offset)
/* Mode select */
#define GPIO_MODE_GPIO 0
#define GPIO_MODE_SFIO 1
/**
* Configures a given pin as either INPUT or OUPUT.
*
* @param pin The GPIO pin to work with, as created with TEGRA_GPIO, or a named GPIO.
* @param direction The relevant direction.
*/
void gpio_configure_direction(enum tegra_named_gpio pin, enum tegra_gpio_direction dir);
/* Direction */
#define GPIO_DIRECTION_INPUT 0
#define GPIO_DIRECTION_OUTPUT 1
/* Level */
#define GPIO_LEVEL_LOW 0
#define GPIO_LEVEL_HIGH 1
/**
* Drives a relevant GPIO pin as either HIGH or LOW.
*
* @param pin The GPIO pin to work with, as created with TEGRA_GPIO, or a named GPIO.
* @param mode The relevant value.
*/
void gpio_write(enum tegra_named_gpio pin, enum tegra_gpio_value value);
/* Named GPIOs */
#define GPIO_MICROSD_CARD_DETECT TEGRA_GPIO(Z, 1)
#define GPIO_MICROSD_WRITE_PROTECT TEGRA_GPIO(Z, 4)
#define GPIO_MICROSD_SUPPLY_ENABLE TEGRA_GPIO(E, 4)
/**
* Drives a relevant GPIO pin as either HIGH or LOW.
*
* @param pin The GPIO pin to work with, as created with TEGRA_GPIO, or a named GPIO.
* @param mode The relevant mode.
*/
enum tegra_gpio_value gpio_read(enum tegra_named_gpio pin);
void gpio_configure_mode(uint32_t pin, uint32_t mode);
void gpio_configure_direction(uint32_t pin, uint32_t dir);
void gpio_write(uint32_t pin, uint32_t value);
uint32_t gpio_read(uint32_t pin);
#endif