Rewrite the memory map-related code...
...other style fixes, etc.
This commit is contained in:
TuxSH
@@ -2,87 +2,64 @@
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#define EXOSPHERE_MEMORY_MAP_H
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#include "mmu.h"
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#include "preprocessor.h"
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#define ATTRIB_MEMTYPE_NORMAL MMU_PTE_BLOCK_MEMTYPE(0)
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#define ATTRIB_MEMTYPE_DEVICE MMU_PTE_BLOCK_MEMTYPE(1)
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static const struct {
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uintptr_t address;
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uint64_t size;
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uint64_t attributes;
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bool is_block_range;
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} g_identity_mappings[] = {
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{ 0x40020000, 0x20000, 0, false }, /* iRAM-C+D (contains the secmon's coldboot crt0) */
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{ 0x7C010000, 0x10000, 0, false }, /* TZRAM (contains the secmon's warmboot crt0) */
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{ 0x80000000, 4u << 30, MMU_PTE_BLOCK_XN | MMU_PTE_BLOCK_NS, true }, /* DRAM (4GB) */
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};
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/* Identity mappings (addr, size, additional attributes, is block range) */
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#define _MMAPID0 ( 0x40020000ull, 0x20000ull, 0ull, false ) /* iRAM-C+D (contains the secmon's coldboot crt0) */
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#define _MMAPID1 ( 0x7C010000ull, 0x10000ull, 0ull, false ) /* TZRAM (contains the secmon's warmboot crt0) */
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#define _MMAPID2 ( 0x80000000ull, 4ull << 30, MMU_PTE_BLOCK_XN | MMU_PTE_BLOCK_NS, true ) /* DRAM (4GB) */
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static const struct {
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uintptr_t pa;
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size_t size;
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bool is_secure;
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} g_devices[] = {
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{ 0x50041000, 0x1000, true }, /* ARM Interrupt Distributor */
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{ 0x50042000, 0x2000, true }, /* Interrupt Controller Physical CPU interface */
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{ 0x70006000, 0x1000, false }, /* UART-A */
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{ 0x60006000, 0x1000, false }, /* Clock and Reset */
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{ 0x7000E000, 0x1000, true }, /* RTC, PMC */
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{ 0x60005000, 0x1000, true }, /* TMRs, WDTs */
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{ 0x6000C000, 0x1000, true }, /* System Registers */
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{ 0x70012000, 0x2000, true }, /* SE */
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{ 0x700F0000, 0x1000, true }, /* SYSCTR0 */
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{ 0x70019000, 0x1000, true }, /* MC */
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{ 0x7000F000, 0x1000, true }, /* FUSE (0x7000F800) */
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{ 0x70000000, 0x4000, true }, /* MISC */
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{ 0x60007000, 0x1000, true }, /* Flow Controller */
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{ 0x40002000, 0x1000, true }, /* NX bootloader mailbox page */
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{ 0x7000D000, 0x1000, true }, /* I2C-5,6 - SPI 2B-1 to 4 */
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{ 0x6000D000, 0x1000, true }, /* GPIO-1 - GPIO-8 */
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{ 0x7000C000, 0x1000, true }, /* I2C-I2C4 */
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{ 0x6000F000, 0x1000, true }, /* Exception vectors */
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};
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/* MMIO (addr, size, is secure) */
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#define _MMAPDEV0 ( 0x50041000ull, 0x1000ull, true ) /* ARM Interrupt Distributor */
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#define _MMAPDEV1 ( 0x50042000ull, 0x2000ull, true ) /* Interrupt Controller Physical CPU interface */
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#define _MMAPDEV2 ( 0x70006000ull, 0x1000ull, false ) /* UART-A */
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#define _MMAPDEV3 ( 0x60006000ull, 0x1000ull, false ) /* Clock and Reset */
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#define _MMAPDEV4 ( 0x7000E000ull, 0x1000ull, true ) /* RTC, PMC */
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#define _MMAPDEV5 ( 0x60005000ull, 0x1000ull, true ) /* TMRs, WDTs */
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#define _MMAPDEV6 ( 0x6000C000ull, 0x1000ull, true ) /* System Registers */
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#define _MMAPDEV7 ( 0x70012000ull, 0x2000ull, true ) /* SE */
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#define _MMAPDEV8 ( 0x700F0000ull, 0x1000ull, true ) /* SYSCTR0 */
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#define _MMAPDEV9 ( 0x70019000ull, 0x1000ull, true ) /* MC */
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#define _MMAPDEV10 ( 0x7000F000ull, 0x1000ull, true ) /* FUSE (0x7000F800) */
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#define _MMAPDEV11 ( 0x70000000ull, 0x4000ull, true ) /* MISC */
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#define _MMAPDEV12 ( 0x60007000ull, 0x1000ull, true ) /* Flow Controller */
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#define _MMAPDEV13 ( 0x40002000ull, 0x1000ull, true ) /* NX bootloader mailbox page */
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#define _MMAPDEV14 ( 0x7000D000ull, 0x1000ull, true ) /* I2C-5,6 - SPI 2B-1 to 4 */
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#define _MMAPDEV15 ( 0x6000D000ull, 0x1000ull, true ) /* GPIO-1 - GPIO-8 */
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#define _MMAPDEV16 ( 0x7000C000ull, 0x1000ull, true ) /* I2C-I2C4 */
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#define _MMAPDEV17 ( 0x6000F000ull, 0x1000ull, true ) /* Exception vectors */
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static const struct {
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uintptr_t pa;
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size_t size;
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uint64_t attributes;
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} g_lp0_entry_ram_segments[] = {
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{ 0x40020000, 0x10000, MMU_PTE_BLOCK_NS | ATTRIB_MEMTYPE_DEVICE }, /* Encrypted TZRAM */
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{ 0x40003000, 0x01000, MMU_PTE_BLOCK_NS | ATTRIB_MEMTYPE_DEVICE }, /* LP0 entry code */
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{ 0x7C010000, 0x10000, MMU_AP_PRIV_RO | ATTRIB_MEMTYPE_NORMAL }, /* TZRAM to encrypt */
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};
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/* LP0 entry ram segments (addr, size, additional attributes) */
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#define _MMAPLP0ES0 ( 0x40020000ull, 0x10000ull, MMU_PTE_BLOCK_NS | ATTRIB_MEMTYPE_DEVICE ) /* Encrypted TZRAM */
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#define _MMAPLP0ES1 ( 0x40003000ull, 0x01000ull, MMU_PTE_BLOCK_NS | ATTRIB_MEMTYPE_DEVICE ) /* LP0 entry code */
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#define _MMAPLP0ES2 ( 0x7C010000ull, 0x10000ull, MMU_AP_PRIV_RO | ATTRIB_MEMTYPE_NORMAL ) /* TZRAM to encrypt */
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static const struct {
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uintptr_t pa;
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size_t size;
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uint64_t attributes;
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} g_warmboot_ram_segments[] = {
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{ 0x8000F000, 0x01000, MMU_PTE_BLOCK_NS | ATTRIB_MEMTYPE_DEVICE }, /* Encrypted SE state for bootROM */
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{ 0x80010000, 0x10000, MMU_PTE_BLOCK_NS | ATTRIB_MEMTYPE_DEVICE }, /* Encrypted TZRAM for warmboot.bin */
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};
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/* Warmboot data ram segments (addr, size, additional attributes) */
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#define _MMAPWBS0 ( 0x8000F000ull, 0x01000ull, MMU_PTE_BLOCK_NS | ATTRIB_MEMTYPE_DEVICE ) /* Encrypted SE state for bootROM */
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#define _MMAPWBS1 ( 0x80010000ull, 0x10000ull, MMU_PTE_BLOCK_NS | ATTRIB_MEMTYPE_DEVICE ) /* Encrypted TZRAM for warmboot.bin */
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static const struct {
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size_t tzram_offset;
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size_t map_size;
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size_t increment; /* for alignment, guard pages, etc. */
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bool is_code_segment; /* note: code is RWX */
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} g_tzram_segments[] = {
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{ 0x3000, 0x10000 - 0x2000 - 0x3000, 0x10000, true }, /* Warmboot crt0 sections and main code segment */
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{ 0x10000 - 0x2000, 0x2000, 0x04000, true }, /* pk2ldr segment */
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{ 0, 0, 0x02000, false }, /* SPL .bss buffer, NOT mapped at startup */
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{ 0x10000 - 0x2000, 0x1000, 0x02000, false }, /* Core 0,1,2 stack */
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{ 0x10000 - 0x1000, 0x1000, 0x02000, false }, /* Core 3 stack */
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{ 0, 0x1000, 0x02000, true }, /* Secure Monitor exception vectors, some init stacks */
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{ 0x1000, 0x1000, 0x02000, false }, /* L2 translation table */
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{ 0x2000, 0x1000, 0x02000, false }, /* L3 translation table */
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};
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/* TZRAM segments (offset, size, VA increment, is executable) */
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#define _MMAPTZS0 ( 0x3000ull, 0x10000 - 0x2000 - 0x3000ull, 0x10000ull, true ) /* Warmboot crt0 sections and main code segment */
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#define _MMAPTZS1 ( 0x10000 - 0x2000ull, 0x2000ull, 0x04000ull, true ) /* pk2ldr segment */
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#define _MMAPTZS2 ( 0ull, 0ull, 0x02000ull, false ) /* SPL .bss buffer, NOT mapped at startup */
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#define _MMAPTZS3 ( 0x10000 - 0x2000ull, 0x1000ull, 0x02000ull, false ) /* Core 0ull1,2 stack */
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#define _MMAPTZS4 ( 0x10000 - 0x1000ull, 0x1000ull, 0x02000ull, false ) /* Core 3 stack */
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#define _MMAPTZS5 ( 0ull, 0x1000ull, 0x02000ull, true ) /* Secure Monitor exception vectors, some init stacks */
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#define _MMAPTZS6 ( 0x1000ull, 0x1000ull, 0x02000ull, false ) /* L2 translation table */
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#define _MMAPTZS7 ( 0x2000ull, 0x1000ull, 0x02000ull, false ) /* L3 translation table */
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#define MMIO_BASE 0x1F0080000ull
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#define LP0_ENTRY_RAM_SEGMENT_BASE (MMIO_BASE + 0x000100000)
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#define WARMBOOT_RAM_SEGMENT_BASE (LP0_ENTRY_RAM_SEGMENT_BASE + 0x000047000) /* increment seems to be arbitrary ? */
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#define TZRAM_SEGMENT_BASE (MMIO_BASE + 0x0001E0000)
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#define LP0_ENTRY_RAM_SEGMENT_BASE (MMIO_BASE + 0x000100000ull)
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#define WARMBOOT_RAM_SEGMENT_BASE (LP0_ENTRY_RAM_SEGMENT_BASE + 0x000047000ull) /* increment seems to be arbitrary ? */
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#define TZRAM_SEGMENT_BASE (MMIO_BASE + 0x0001E0000ull)
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#define IDENTIY_MAPPING_ID_MAX 3
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#define IDENTITY_MAPPING_IRAM_CD 0
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#define IDENTITY_MAPPING_TZRAM 1
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#define IDENTITY_MAPPING_DRAM 2
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#define IDENTIY_MAPPING_ID_MAX 3
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#define MMIO_DEVID_GICD 0
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#define MMIO_DEVID_GICC 1
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@@ -123,194 +100,70 @@ static const struct {
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#define TZRAM_SEGMENT_ID_L3_TRANSLATION_TABLE 7
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#define TZRAM_SEGMENT_ID_MAX 8
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/**********************************************************************************************/
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#define IDENTITY_GET_MAPPING_ADDRESS(mapping_id) (TUPLE_ELEM_0(CAT(_MMAPID, EVAL(mapping_id))))
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#define IDENTITY_GET_MAPPING_SIZE(mapping_id) (TUPLE_ELEM_1(CAT(_MMAPID, EVAL(mapping_id))))
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#define IDENTITY_GET_MAPPING_ATTRIBS(mapping_id) (TUPLE_ELEM_2(CAT(_MMAPID, EVAL(mapping_id))))
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#define IDENTITY_IS_MAPPING_BLOCK_RANGE(mapping_id) (TUPLE_ELEM_3(CAT(_MMAPID, EVAL(mapping_id))))
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INLINE_UNROLL static inline void identity_map_all_mappings(uintptr_t *mmu_l1_tbl, uintptr_t *mmu_l3_tbl) {
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static uint64_t base_attributes = MMU_PTE_BLOCK_INNER_SHAREBLE | ATTRIB_MEMTYPE_NORMAL;
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for(size_t i = 0; i < IDENTIY_MAPPING_ID_MAX; i++) {
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uint64_t attributes = base_attributes | g_identity_mappings[i].attributes;
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if(g_identity_mappings[i].is_block_range) {
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mmu_map_block_range(1, mmu_l1_tbl, g_identity_mappings[i].address, g_identity_mappings[i].address,
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g_identity_mappings[i].size, attributes);
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}
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else {
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mmu_map_page_range(mmu_l3_tbl, g_identity_mappings[i].address, g_identity_mappings[i].address,
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g_identity_mappings[i].size, attributes);
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}
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}
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}
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#define MMIO_GET_DEVICE_PA(device_id) (TUPLE_ELEM_0(CAT(_MMAPDEV, EVAL(device_id))))
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#define MMIO_GET_DEVICE_ADDRESS(device_id)\
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(\
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(TUPLE_FOLD_LEFT_1(EVAL(device_id), _MMAPDEV, PLUS) EVAL(MMIO_BASE)) +\
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0x1000ull * (device_id)\
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)
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#define MMIO_GET_DEVICE_SIZE(device_id) (TUPLE_ELEM_1(CAT(_MMAPDEV, EVAL(device_id))))
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#define MMIO_IS_DEVICE_SECURE(device_id) (TUPLE_ELEM_2(CAT(_MMAPDEV, EVAL(device_id))))
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INLINE_UNROLL static inline void identity_unmap_all_mappings(uintptr_t *mmu_l1_tbl, uintptr_t *mmu_l3_tbl) {
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for(size_t i = 0; i < IDENTIY_MAPPING_ID_MAX; i++) {
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if(g_identity_mappings[i].is_block_range) {
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mmu_unmap_range(1, mmu_l1_tbl, g_identity_mappings[i].address, g_identity_mappings[i].size);
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}
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else {
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mmu_unmap_range(3, mmu_l3_tbl, g_identity_mappings[i].address, g_identity_mappings[i].size);
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}
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}
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}
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#define LP0_ENTRY_GET_RAM_SEGMENT_PA(segment_id) (TUPLE_ELEM_0(CAT(_MMAPLP0ES, EVAL(segment_id))))
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#define LP0_ENTRY_GET_RAM_SEGMENT_ADDRESS(segment_id) (EVAL(LP0_ENTRY_RAM_SEGMENT_BASE) + 0x10000ull * (segment_id))
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#define LP0_ENTRY_GET_RAM_SEGMENT_SIZE(segment_id) (TUPLE_ELEM_1(CAT(_MMAPLP0ES, EVAL(segment_id))))
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#define LP0_ENTRY_GET_RAM_SEGMENT_ATTRIBS(segment_id) (TUPLE_ELEM_2(CAT(_MMAPLP0ES, EVAL(segment_id))))
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#define WARMBOOT_GET_RAM_SEGMENT_PA(segment_id) (TUPLE_ELEM_0(CAT(_MMAPWBS, EVAL(segment_id))))
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#define WARMBOOT_GET_RAM_SEGMENT_ADDRESS(segment_id) (TUPLE_FOLD_LEFT_1(EVAL(segment_id), _MMAPWBS, PLUS) EVAL(WARMBOOT_RAM_SEGMENT_BASE))
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#define WARMBOOT_GET_RAM_SEGMENT_SIZE(segment_id) (TUPLE_ELEM_1(CAT(_MMAPWBS, EVAL(segment_id))))
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#define WARMBOOT_GET_RAM_SEGMENT_ATTRIBS(segment_id) (TUPLE_ELEM_2(CAT(_MMAPWBS, EVAL(segment_id))))
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#define TZRAM_GET_SEGMENT_PA(segment_id) (0x7C010000ull + (TUPLE_ELEM_0(CAT(_MMAPTZS, EVAL(segment_id)))))
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#define TZRAM_GET_SEGMENT_ADDRESS(segment_id) (TUPLE_FOLD_LEFT_2(EVAL(segment_id), _MMAPTZS, PLUS) EVAL(TZRAM_SEGMENT_BASE))
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#define TZRAM_GET_SEGMENT_SIZE(segment_id) (TUPLE_ELEM_1(CAT(_MMAPTZS, EVAL(segment_id))))
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#define TZRAM_IS_SEGMENT_EXECUTABLE(segment_id) (TUPLE_ELEM_3(CAT(_MMAPTZS, EVAL(segment_id))))
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/**********************************************************************************************/
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/* We don't need unmapping functions */
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INLINE_UNROLL static inline uintptr_t mmio_get_device_pa(unsigned int device_id) {
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return g_devices[device_id].pa;
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}
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#ifndef MEMORY_MAP_USE_IDENTIY_MAPPING
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INLINE_UNROLL static inline uintptr_t mmio_get_device_address(unsigned int device_id) {
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size_t offset = 0;
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for(unsigned int i = 0; i < device_id; i++) {
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offset += g_devices[i].size;
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offset += 0x1000; /* guard page */
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ALINLINE static inline void identity_map_mapping(uintptr_t *mmu_l1_tbl, uintptr_t *mmu_l3_tbl, uintptr_t addr, size_t size, uint64_t attribs, bool is_block_range) {
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if (is_block_range) {
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mmu_map_block_range(1, mmu_l1_tbl, addr, addr, size, attribs | MMU_PTE_BLOCK_INNER_SHAREBLE | ATTRIB_MEMTYPE_NORMAL);
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}
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else {
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mmu_map_page_range(mmu_l3_tbl, addr, addr, size, attribs | MMU_PTE_BLOCK_INNER_SHAREBLE | ATTRIB_MEMTYPE_NORMAL);
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}
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return MMIO_BASE + offset;
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}
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#else
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INLINE_UNROLL static inline uintptr_t mmio_get_device_address(unsigned int device_id) {
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return mmio_get_device_pa(device_id);
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}
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#endif
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INLINE_UNROLL static inline void mmio_map_all_devices(uintptr_t *mmu_l3_tbl) {
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ALINLINE static inline void mmio_map_device(uintptr_t *mmu_l3_tbl, uintptr_t addr, uintptr_t pa, size_t size, bool is_secure) {
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static const uint64_t secure_device_attributes = MMU_PTE_BLOCK_XN | MMU_PTE_BLOCK_INNER_SHAREBLE | ATTRIB_MEMTYPE_DEVICE;
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static const uint64_t device_attributes = MMU_PTE_BLOCK_NS | secure_device_attributes;
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for(size_t i = 0, offset = 0; i < MMIO_DEVID_MAX; i++) {
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uint64_t attributes = g_devices[i].is_secure ? secure_device_attributes : device_attributes;
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mmu_map_page_range(mmu_l3_tbl, MMIO_BASE + offset, g_devices[i].pa, g_devices[i].size, attributes);
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offset += g_devices[i].size;
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offset += 0x1000; /* insert guard page */
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}
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uint64_t attributes = is_secure ? secure_device_attributes : device_attributes;
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mmu_map_page_range(mmu_l3_tbl, addr, pa, size, attributes);
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}
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INLINE_UNROLL static inline void mmio_unmap_all_devices(uintptr_t *mmu_l3_tbl) {
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for(size_t i = 0, offset = 0; i < MMIO_DEVID_MAX; i++) {
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mmu_unmap_range(3, mmu_l3_tbl, MMIO_BASE + offset, g_devices[i].size);
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ALINLINE static inline void lp0_entry_map_ram_segment(uintptr_t *mmu_l3_tbl, uintptr_t addr, uintptr_t pa, size_t size, uint64_t attribs) {
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uint64_t attributes = MMU_PTE_BLOCK_XN | MMU_PTE_BLOCK_INNER_SHAREBLE | attribs;
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offset += g_devices[i].size;
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offset += 0x1000; /* insert guard page */
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}
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mmu_map_page_range(mmu_l3_tbl, addr, pa, size, attributes);
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}
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/**********************************************************************************************/
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ALINLINE static inline void warmboot_map_ram_segment(uintptr_t *mmu_l3_tbl, uintptr_t addr, uintptr_t pa, size_t size, uint64_t attribs) {
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uint64_t attributes = MMU_PTE_BLOCK_XN | MMU_PTE_BLOCK_INNER_SHAREBLE | attribs;
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INLINE_UNROLL static inline uintptr_t lp0_get_plaintext_ram_segment_pa(unsigned int segment_id) {
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return g_lp0_entry_ram_segments[segment_id].pa;
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mmu_map_page_range(mmu_l3_tbl, addr, pa, size, attributes);
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}
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#ifndef MEMORY_MAP_USE_IDENTIY_MAPPING
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INLINE_UNROLL static inline uintptr_t lp0_get_plaintext_ram_segment_address(unsigned int segment_id) {
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return LP0_ENTRY_RAM_SEGMENT_BASE + 0x10000 * segment_id;
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}
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#else
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INLINE_UNROLL static inline uintptr_t lp0_get_plaintext_ram_segment_address(unsigned int segment_id) {
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return lp0_get_plaintext_ram_segment_pa(segment_id);
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}
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#endif
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ALINLINE static inline void tzram_map_segment(uintptr_t *mmu_l3_tbl, uintptr_t addr, uintptr_t pa, size_t size, bool is_executable) {
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uint64_t attributes = (is_executable ? 0 : MMU_PTE_BLOCK_XN) | MMU_PTE_BLOCK_INNER_SHAREBLE | ATTRIB_MEMTYPE_NORMAL;
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INLINE_UNROLL static inline void lp0_map_all_plaintext_ram_segments(uintptr_t *mmu_l3_tbl) {
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for(size_t i = 0, offset = 0; i < LP0_ENTRY_RAM_SEGMENT_ID_MAX; i++) {
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uint64_t attributes = MMU_PTE_BLOCK_XN | MMU_PTE_BLOCK_INNER_SHAREBLE | g_lp0_entry_ram_segments[i].attributes;
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mmu_map_page_range(mmu_l3_tbl, LP0_ENTRY_RAM_SEGMENT_BASE + offset, g_lp0_entry_ram_segments[i].pa,
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g_lp0_entry_ram_segments[i].size, attributes);
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offset += 0x10000;
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}
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}
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|
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INLINE_UNROLL static inline void lp0_unmap_all_plaintext_ram_segments(uintptr_t *mmu_l3_tbl) {
|
||||
for(size_t i = 0, offset = 0; i < LP0_ENTRY_RAM_SEGMENT_ID_MAX; i++) {
|
||||
mmu_unmap_range(3, mmu_l3_tbl, LP0_ENTRY_RAM_SEGMENT_BASE + offset, g_lp0_entry_ram_segments[i].size);
|
||||
|
||||
offset += 0x10000;
|
||||
}
|
||||
}
|
||||
|
||||
/**********************************************************************************************/
|
||||
|
||||
INLINE_UNROLL static inline uintptr_t warmboot_get_ram_segment_pa(unsigned int segment_id) {
|
||||
return g_warmboot_ram_segments[segment_id].pa;
|
||||
}
|
||||
|
||||
#ifndef MEMORY_MAP_USE_IDENTIY_MAPPING
|
||||
INLINE_UNROLL static inline uintptr_t warmboot_get_ram_segment_address(unsigned int segment_id) {
|
||||
size_t offset = 0;
|
||||
for(unsigned int i = 0; i < segment_id; i++) {
|
||||
offset += g_warmboot_ram_segments[i].size;
|
||||
}
|
||||
|
||||
return WARMBOOT_RAM_SEGMENT_BASE + offset;
|
||||
}
|
||||
#else
|
||||
INLINE_UNROLL static inline uintptr_t warmboot_get_ram_segment_address(unsigned int segment_id) {
|
||||
return warmboot_get_ram_segment_pa(segment_id);
|
||||
}
|
||||
#endif
|
||||
|
||||
INLINE_UNROLL static inline void warmboot_map_all_ram_segments(uintptr_t *mmu_l3_tbl) {
|
||||
for(size_t i = 0, offset = 0; i < WARMBOOT_RAM_SEGMENT_ID_MAX; i++) {
|
||||
uint64_t attributes = MMU_PTE_BLOCK_XN | MMU_PTE_BLOCK_INNER_SHAREBLE | g_warmboot_ram_segments[i].attributes;
|
||||
mmu_map_page_range(mmu_l3_tbl, WARMBOOT_RAM_SEGMENT_BASE + offset, g_warmboot_ram_segments[i].pa,
|
||||
g_warmboot_ram_segments[i].size, attributes);
|
||||
offset += g_warmboot_ram_segments[i].size;
|
||||
}
|
||||
}
|
||||
|
||||
INLINE_UNROLL static inline void warmboot_unmap_all_ram_segments(uintptr_t *mmu_l3_tbl) {
|
||||
for(size_t i = 0, offset = 0; i < WARMBOOT_RAM_SEGMENT_ID_MAX; i++) {
|
||||
mmu_unmap_range(3, mmu_l3_tbl, WARMBOOT_RAM_SEGMENT_BASE + offset, g_warmboot_ram_segments[i].size);
|
||||
|
||||
offset += g_warmboot_ram_segments[i].size;
|
||||
}
|
||||
}
|
||||
|
||||
/**********************************************************************************************/
|
||||
|
||||
INLINE_UNROLL static inline uintptr_t tzram_get_segment_pa(unsigned int segment_id) {
|
||||
return 0x7C010000 + g_tzram_segments[segment_id].tzram_offset;
|
||||
}
|
||||
|
||||
#ifndef MEMORY_MAP_USE_IDENTIY_MAPPING
|
||||
INLINE_UNROLL static inline uintptr_t tzram_get_segment_address(unsigned int segment_id) {
|
||||
size_t offset = 0;
|
||||
for(unsigned int i = 0; i < segment_id; i++) {
|
||||
offset += g_tzram_segments[i].increment;
|
||||
}
|
||||
|
||||
return TZRAM_SEGMENT_BASE + offset;
|
||||
}
|
||||
#else
|
||||
INLINE_UNROLL static inline uintptr_t tzram_get_segment_address(unsigned int segment_id) {
|
||||
return tzram_get_segment_pa(segment_id);
|
||||
}
|
||||
#endif
|
||||
|
||||
INLINE_UNROLL static inline void tzram_map_all_segments(uintptr_t *mmu_l3_tbl) {
|
||||
/* Except the SPL userpage */
|
||||
for(size_t i = 0, offset = 0; i < TZRAM_SEGMENT_ID_MAX; i++) {
|
||||
uint64_t attributes = (g_tzram_segments[i].is_code_segment ? 0 : MMU_PTE_BLOCK_XN) | MMU_PTE_BLOCK_INNER_SHAREBLE | ATTRIB_MEMTYPE_NORMAL;
|
||||
if(g_tzram_segments[i].map_size == 0) {
|
||||
continue;
|
||||
}
|
||||
mmu_map_page_range(mmu_l3_tbl, TZRAM_SEGMENT_BASE + offset, 0x7C010000 + g_tzram_segments[i].tzram_offset,
|
||||
g_tzram_segments[i].map_size, attributes);
|
||||
offset += g_tzram_segments[i].increment;
|
||||
}
|
||||
}
|
||||
|
||||
INLINE_UNROLL static inline void tzram_unmap_all_segments(uintptr_t *mmu_l3_tbl) {
|
||||
/* Except the SPL userpage */
|
||||
for(size_t i = 0, offset = 0; i < TZRAM_SEGMENT_ID_MAX; i++) {
|
||||
if(g_tzram_segments[i].map_size == 0) {
|
||||
continue;
|
||||
}
|
||||
mmu_unmap_range(3, mmu_l3_tbl, TZRAM_SEGMENT_BASE + offset, g_tzram_segments[i].map_size);
|
||||
|
||||
offset += g_tzram_segments[i].increment;
|
||||
}
|
||||
mmu_map_page_range(mmu_l3_tbl, addr, pa, size, attributes);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user