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fusee: restore DRAM to 204MHz before starting main cpu on Mariko (closes #1600).

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Nintendo's Mariko tables result in trained frequency of 1599999 instead of 1600000.

PCV checks for rate == 1600000 exactly, when doing EMC init.

Thus EMC init does not succeed if we are trained to 1600000.

PCV has a fudge factor of 1000 used in SetEmcDvfsFreq, but this is not used in InitEmcDvfs.

This failure means that PCV cannot change rate back to 204MHz before sleep, and then after
wake extremely degraded performance is observed.

Restoring DRAM to 204MHz before boot causes EMC init to succeed/fixes performance degradation.
This commit is contained in:
Michael Scire
2021-08-30 07:19:28 -07:00
parent 1f065e3bac
commit c5edb031fa
31 changed files with 10747 additions and 15632 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
fusee/fusee-secondary/src/car.h
View File

@@ -51,7 +51,7 @@ typedef enum {
CARDEVICE_USB2 = ((1 << 5) | 0x1A),
CARDEVICE_CORESIGHT = ((2 << 5) | 0x9),
CARDEVICE_TSEC = ((2 << 5) | 0x13),
CARDEVICE_MSELECT = ((3 << 5) | 0x3),
CARDEVICE_MSELECT = ((3 << 5) | 0x8),
CARDEVICE_ACTMON = ((3 << 5) | 0x17),
CARDEVICE_TZRAM = ((3 << 5) | 0x1E),
CARDEVICE_SE = ((3 << 5) | 0x1F),
@@ -490,6 +490,15 @@ typedef struct {
uint32_t sdmmc4_pllc4_out1_shaper_ctrl; /* _SDMMC4_PLLC4_OUT1_SHAPER_CTRL_0, 0x73c */
uint32_t sdmmc4_pllc4_out2_shaper_ctrl; /* _SDMMC4_PLLC4_OUT2_SHAPER_CTRL_0, 0x740 */
uint32_t sdmmc4_div_clk_shaper_ctrl; /* _SDMMC4_DIV_CLK_SHAPER_CTRL_0, 0x744 */
uint32_t _0x748[(0x774-0x748) / sizeof(uint32_t)]; // TODO
uint32_t pllm_ss_cfg; /* _PLLM_SS_CFG_0, 0x744 */
uint32_t pllm_ss_ctrl1; /* _PLLM_SS_CTRL1_0, 0x778 */
uint32_t pllm_ss_ctrl2; /* _PLLM_SS_CTRL2_0, 0x77C */
uint32_t pllmb_ss_cfg; /* _PLLMB_SS_CFG_0, 0x780 */
uint32_t pllmb_ss_ctrl1; /* _PLLMB_SS_CTRL1_0, 0x784 */
uint32_t pllmb_ss_ctrl2; /* _PLLMB_SS_CTRL2_0, 0x788 */
} tegra_car_t;
static inline volatile tegra_car_t *car_get_regs(void) {

11
fusee/fusee-secondary/src/emc.h
View File

@@ -19,7 +19,7 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*
*/
#ifndef FUSEE_EMC_H_
#define FUSEE_EMC_H_
@@ -393,6 +393,7 @@
#define EMC_CFG_DIG_DLL_PERIOD 0x2c0
#define EMC_DIG_DLL_STATUS 0x2c4
#define EMC_DIG_DLL_STATUS_DLL_LOCK (1 << 15)
#define EMC_DIG_DLL_STATUS_DLL_LOCK_B01 (1 << 2)
#define EMC_DIG_DLL_STATUS_DLL_PRIV_UPDATED (1 << 17)
#define EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT 0
#define EMC_DIG_DLL_STATUS_DLL_OUT_MASK \
@@ -1065,6 +1066,10 @@
#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC (1 << 16)
#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC (1 << 24)
#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF_B01 (1 << 10)
#define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xc68
#define EMC_PMACRO_BRICK_MAPPING_0 0xc80
#define EMC_PMACRO_BRICK_MAPPING_1 0xc84
@@ -1126,4 +1131,8 @@
#define EMC_PMACRO_DSR_VTTGEN_CTRL_0 0xc6c
// B01
#define EMC_PMACRO_DLL_CFG_0 0x5E4
#define EMC_PMACRO_DLL_CFG_1 0x5E8
#endif

11
fusee/fusee-secondary/src/main.c
View File

@@ -34,6 +34,9 @@
#include "../../../fusee/common/display/video_fb.h"
#include "../../../fusee/common/sdmmc/sdmmc.h"
#include "../../../fusee/common/log.h"
#include "fuse.h"
#include "mtc/mtc.h"
#include "mtc/mtc_b01.h"
extern void (*__program_exit_callback)(int rc);
@@ -107,6 +110,9 @@ int main(int argc, void **argv) {
/* Initialize the boot environment. */
setup_env();
/* Train dram. */
train_dram();
print(SCREEN_LOG_LEVEL_DEBUG | SCREEN_LOG_LEVEL_NO_PREFIX, u8"Welcome to Atmosphère Fusée Stage 2!\n");
print(SCREEN_LOG_LEVEL_DEBUG, "Stage 2 executing from: %s\n", (const char *)argv[STAGE2_ARGV_PROGRAM_PATH]);
@@ -134,6 +140,11 @@ int main(int argc, void **argv) {
/* Terminate the boot environment. */
cleanup_env();
/* Restore dram if mariko. */
if (fuse_get_soc_type() == 1) {
restore_dram_mariko();
}
/* Finish boot. */
nxboot_finish(boot_memaddr);
} else {

3750
fusee/fusee-secondary/src/mtc/mtc.c Normal file
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File diff suppressed because it is too large Load Diff

759
fusee/fusee-secondary/src/mtc/mtc.h Normal file
View File

@@ -0,0 +1,759 @@
/*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018 CTCaer <ctcaer@gmail.com>
* Copyright (c) 2018-2020 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef FUSEE_MTC_H_
#define FUSEE_MTC_H_
#include <stdint.h>
#include <stdbool.h>
#include "../emc.h"
#include "../mc.h"
#define MTC_TABLES_MAX_ENTRIES 10
#define MAX_PLL_CFGS 14
#define DVFS_FGCG_HIGH_SPEED_THRESHOLD 1000
#define IOBRICK_DCC_THRESHOLD 2400
#define DVFS_FGCG_MID_SPEED_THRESHOLD 600
#define TEGRA21_MAX_TABLE_ID_LEN 50
#define TEGRA_EMC_ISO_USE_FREQ_MAX_NUM 12
#define PLL_C_DIRECT_FLOOR 333500000
#define EMC_STATUS_UPDATE_TIMEOUT 2000
#define TEGRA_EMC_DEFAULT_CLK_LATENCY_US 2000
#define TEGRA_EMC_MODE_REG_17 0x00110000
#define TEGRA_EMC_MRW_DEV_SHIFT 30
#define TEGRA_EMC_MRW_DEV1 2
#define TEGRA_EMC_MRW_DEV2 1
#define EMC_CLK_EMC_2X_CLK_SRC_SHIFT 29
#define EMC_CLK_EMC_2X_CLK_SRC_MASK \
(0x7 << EMC_CLK_EMC_2X_CLK_SRC_SHIFT)
#define EMC_CLK_EMC_2X_CLK_DIVISOR_SHIFT 0
#define EMC_CLK_EMC_2X_CLK_DIVISOR_MASK \
(0xff << EMC_CLK_EMC_2X_CLK_DIVISOR_SHIFT)
enum {
REG_MC,
REG_EMC,
REG_EMC0,
REG_EMC1,
};
#define BURST_REGS_PER_CH_LIST \
{ \
DEFINE_REG(REG_EMC0, EMC_MRW10), \
DEFINE_REG(REG_EMC1, EMC_MRW10), \
DEFINE_REG(REG_EMC0, EMC_MRW11), \
DEFINE_REG(REG_EMC1, EMC_MRW11), \
DEFINE_REG(REG_EMC0, EMC_MRW12), \
DEFINE_REG(REG_EMC1, EMC_MRW12), \
DEFINE_REG(REG_EMC0, EMC_MRW13), \
DEFINE_REG(REG_EMC1, EMC_MRW13), \
}
#define BURST_REGS_LIST \
{ \
DEFINE_REG(REG_EMC, EMC_RC), \
DEFINE_REG(REG_EMC, EMC_RFC), \
DEFINE_REG(REG_EMC, EMC_RFCPB), \
DEFINE_REG(REG_EMC, EMC_REFCTRL2), \
DEFINE_REG(REG_EMC, EMC_RFC_SLR), \
DEFINE_REG(REG_EMC, EMC_RAS), \
DEFINE_REG(REG_EMC, EMC_RP), \
DEFINE_REG(REG_EMC, EMC_R2W), \
DEFINE_REG(REG_EMC, EMC_W2R), \
DEFINE_REG(REG_EMC, EMC_R2P), \
DEFINE_REG(REG_EMC, EMC_W2P), \
DEFINE_REG(REG_EMC, EMC_R2R), \
DEFINE_REG(REG_EMC, EMC_TPPD), \
DEFINE_REG(REG_EMC, EMC_CCDMW), \
DEFINE_REG(REG_EMC, EMC_RD_RCD), \
DEFINE_REG(REG_EMC, EMC_WR_RCD), \
DEFINE_REG(REG_EMC, EMC_RRD), \
DEFINE_REG(REG_EMC, EMC_REXT), \
DEFINE_REG(REG_EMC, EMC_WEXT), \
DEFINE_REG(REG_EMC, EMC_WDV_CHK), \
DEFINE_REG(REG_EMC, EMC_WDV), \
DEFINE_REG(REG_EMC, EMC_WSV), \
DEFINE_REG(REG_EMC, EMC_WEV), \
DEFINE_REG(REG_EMC, EMC_WDV_MASK), \
DEFINE_REG(REG_EMC, EMC_WS_DURATION), \
DEFINE_REG(REG_EMC, EMC_WE_DURATION), \
DEFINE_REG(REG_EMC, EMC_QUSE), \
DEFINE_REG(REG_EMC, EMC_QUSE_WIDTH), \
DEFINE_REG(REG_EMC, EMC_IBDLY), \
DEFINE_REG(REG_EMC, EMC_OBDLY), \
DEFINE_REG(REG_EMC, EMC_EINPUT), \
DEFINE_REG(REG_EMC, EMC_MRW6), \
DEFINE_REG(REG_EMC, EMC_EINPUT_DURATION), \
DEFINE_REG(REG_EMC, EMC_PUTERM_EXTRA), \
DEFINE_REG(REG_EMC, EMC_PUTERM_WIDTH), \
DEFINE_REG(REG_EMC, EMC_QRST), \
DEFINE_REG(REG_EMC, EMC_QSAFE), \
DEFINE_REG(REG_EMC, EMC_RDV), \
DEFINE_REG(REG_EMC, EMC_RDV_MASK), \
DEFINE_REG(REG_EMC, EMC_RDV_EARLY), \
DEFINE_REG(REG_EMC, EMC_RDV_EARLY_MASK), \
DEFINE_REG(REG_EMC, EMC_REFRESH), \
DEFINE_REG(REG_EMC, EMC_BURST_REFRESH_NUM), \
DEFINE_REG(REG_EMC, EMC_PRE_REFRESH_REQ_CNT), \
DEFINE_REG(REG_EMC, EMC_PDEX2WR), \
DEFINE_REG(REG_EMC, EMC_PDEX2RD), \
DEFINE_REG(REG_EMC, EMC_PCHG2PDEN), \
DEFINE_REG(REG_EMC, EMC_ACT2PDEN), \
DEFINE_REG(REG_EMC, EMC_AR2PDEN), \
DEFINE_REG(REG_EMC, EMC_RW2PDEN), \
DEFINE_REG(REG_EMC, EMC_CKE2PDEN), \
DEFINE_REG(REG_EMC, EMC_PDEX2CKE), \
DEFINE_REG(REG_EMC, EMC_PDEX2MRR), \
DEFINE_REG(REG_EMC, EMC_TXSR), \
DEFINE_REG(REG_EMC, EMC_TXSRDLL), \
DEFINE_REG(REG_EMC, EMC_TCKE), \
DEFINE_REG(REG_EMC, EMC_TCKESR), \
DEFINE_REG(REG_EMC, EMC_TPD), \
DEFINE_REG(REG_EMC, EMC_TFAW), \
DEFINE_REG(REG_EMC, EMC_TRPAB), \
DEFINE_REG(REG_EMC, EMC_TCLKSTABLE), \
DEFINE_REG(REG_EMC, EMC_TCLKSTOP), \
DEFINE_REG(REG_EMC, EMC_MRW7), \
DEFINE_REG(REG_EMC, EMC_TREFBW), \
DEFINE_REG(REG_EMC, EMC_ODT_WRITE), \
DEFINE_REG(REG_EMC, EMC_FBIO_CFG5), \
DEFINE_REG(REG_EMC, EMC_FBIO_CFG7), \
DEFINE_REG(REG_EMC, EMC_CFG_DIG_DLL), \
DEFINE_REG(REG_EMC, EMC_CFG_DIG_DLL_PERIOD), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_RXRT), \
DEFINE_REG(REG_EMC, EMC_CFG_PIPE_1), \
DEFINE_REG(REG_EMC, EMC_CFG_PIPE_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK0_4), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK0_5), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK1_4), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK1_5), \
DEFINE_REG(REG_EMC, EMC_MRW8), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_LONG_CMD_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_LONG_CMD_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_LONG_CMD_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_LONG_CMD_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_LONG_CMD_4), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_SHORT_CMD_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_SHORT_CMD_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_SHORT_CMD_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3), \
DEFINE_REG(REG_EMC, EMC_TXDSRVTTGEN), \
DEFINE_REG(REG_EMC, EMC_FDPD_CTRL_DQ), \
DEFINE_REG(REG_EMC, EMC_FDPD_CTRL_CMD), \
DEFINE_REG(REG_EMC, EMC_FBIO_SPARE), \
DEFINE_REG(REG_EMC, EMC_ZCAL_INTERVAL), \
DEFINE_REG(REG_EMC, EMC_ZCAL_WAIT_CNT), \
DEFINE_REG(REG_EMC, EMC_MRS_WAIT_CNT), \
DEFINE_REG(REG_EMC, EMC_MRS_WAIT_CNT2), \
DEFINE_REG(REG_EMC, EMC_AUTO_CAL_CHANNEL), \
DEFINE_REG(REG_EMC, EMC_DLL_CFG_0), \
DEFINE_REG(REG_EMC, EMC_DLL_CFG_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_AUTOCAL_CFG_COMMON), \
DEFINE_REG(REG_EMC, EMC_PMACRO_ZCTRL), \
DEFINE_REG(REG_EMC, EMC_CFG), \
DEFINE_REG(REG_EMC, EMC_CFG_PIPE), \
DEFINE_REG(REG_EMC, EMC_DYN_SELF_REF_CONTROL), \
DEFINE_REG(REG_EMC, EMC_QPOP), \
DEFINE_REG(REG_EMC, EMC_DQS_BRLSHFT_0), \
DEFINE_REG(REG_EMC, EMC_DQS_BRLSHFT_1), \
DEFINE_REG(REG_EMC, EMC_CMD_BRLSHFT_2), \
DEFINE_REG(REG_EMC, EMC_CMD_BRLSHFT_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_PAD_CFG_CTRL), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DATA_PAD_RX_CTRL), \
DEFINE_REG(REG_EMC, EMC_PMACRO_CMD_PAD_RX_CTRL), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DATA_RX_TERM_MODE), \
DEFINE_REG(REG_EMC, EMC_PMACRO_CMD_RX_TERM_MODE), \
DEFINE_REG(REG_EMC, EMC_PMACRO_CMD_PAD_TX_CTRL), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DATA_PAD_TX_CTRL), \
DEFINE_REG(REG_EMC, EMC_PMACRO_COMMON_PAD_TX_CTRL), \
DEFINE_REG(REG_EMC, EMC_PMACRO_VTTGEN_CTRL_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_VTTGEN_CTRL_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_VTTGEN_CTRL_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_BRICK_CTRL_RFU1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_CMD_BRICK_CTRL_FDPD), \
DEFINE_REG(REG_EMC, EMC_PMACRO_BRICK_CTRL_RFU2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DATA_BRICK_CTRL_FDPD), \
DEFINE_REG(REG_EMC, EMC_PMACRO_BG_BIAS_CTRL_0), \
DEFINE_REG(REG_EMC, EMC_CFG_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_PWRD_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_PWRD_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_PWRD_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_PWRD_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_PWRD_4), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_PWRD_5), \
DEFINE_REG(REG_EMC, EMC_CONFIG_SAMPLE_DELAY), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_SEL_CLK_SRC_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_SEL_CLK_SRC_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_SEL_CLK_SRC_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_SEL_CLK_SRC_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_SEL_CLK_SRC_4), \
DEFINE_REG(REG_EMC, EMC_PMACRO_TX_SEL_CLK_SRC_5), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_BYPASS), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_PWRD_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_PWRD_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_DDLL_PWRD_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_CMD_CTRL_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_CMD_CTRL_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_CMD_CTRL_2), \
DEFINE_REG(REG_EMC, EMC_TR_TIMING_0), \
DEFINE_REG(REG_EMC, EMC_TR_DVFS), \
DEFINE_REG(REG_EMC, EMC_TR_CTRL_1), \
DEFINE_REG(REG_EMC, EMC_TR_RDV), \
DEFINE_REG(REG_EMC, EMC_TR_QPOP), \
DEFINE_REG(REG_EMC, EMC_TR_RDV_MASK), \
DEFINE_REG(REG_EMC, EMC_MRW14), \
DEFINE_REG(REG_EMC, EMC_TR_QSAFE), \
DEFINE_REG(REG_EMC, EMC_TR_QRST), \
DEFINE_REG(REG_EMC, EMC_TRAINING_CTRL), \
DEFINE_REG(REG_EMC, EMC_TRAINING_SETTLE), \
DEFINE_REG(REG_EMC, EMC_TRAINING_VREF_SETTLE), \
DEFINE_REG(REG_EMC, EMC_TRAINING_CA_FINE_CTRL), \
DEFINE_REG(REG_EMC, EMC_TRAINING_CA_CTRL_MISC), \
DEFINE_REG(REG_EMC, EMC_TRAINING_CA_CTRL_MISC1), \
DEFINE_REG(REG_EMC, EMC_TRAINING_CA_VREF_CTRL), \
DEFINE_REG(REG_EMC, EMC_TRAINING_QUSE_CORS_CTRL), \
DEFINE_REG(REG_EMC, EMC_TRAINING_QUSE_FINE_CTRL), \
DEFINE_REG(REG_EMC, EMC_TRAINING_QUSE_CTRL_MISC), \
DEFINE_REG(REG_EMC, EMC_TRAINING_QUSE_VREF_CTRL), \
DEFINE_REG(REG_EMC, EMC_TRAINING_READ_FINE_CTRL), \
DEFINE_REG(REG_EMC, EMC_TRAINING_READ_CTRL_MISC), \
DEFINE_REG(REG_EMC, EMC_TRAINING_READ_VREF_CTRL), \
DEFINE_REG(REG_EMC, EMC_TRAINING_WRITE_FINE_CTRL), \
DEFINE_REG(REG_EMC, EMC_TRAINING_WRITE_CTRL_MISC), \
DEFINE_REG(REG_EMC, EMC_TRAINING_WRITE_VREF_CTRL), \
DEFINE_REG(REG_EMC, EMC_TRAINING_MPC), \
DEFINE_REG(REG_EMC, EMC_MRW15), \
}
#define TRIM_REGS_PER_CH_LIST \
{ \
DEFINE_REG(REG_EMC0, EMC_CMD_BRLSHFT_0), \
DEFINE_REG(REG_EMC1, EMC_CMD_BRLSHFT_1), \
DEFINE_REG(REG_EMC0, EMC_DATA_BRLSHFT_0), \
DEFINE_REG(REG_EMC1, EMC_DATA_BRLSHFT_0), \
DEFINE_REG(REG_EMC0, EMC_DATA_BRLSHFT_1), \
DEFINE_REG(REG_EMC1, EMC_DATA_BRLSHFT_1), \
DEFINE_REG(REG_EMC0, EMC_QUSE_BRLSHFT_0), \
DEFINE_REG(REG_EMC1, EMC_QUSE_BRLSHFT_1), \
DEFINE_REG(REG_EMC0, EMC_QUSE_BRLSHFT_2), \
DEFINE_REG(REG_EMC1, EMC_QUSE_BRLSHFT_3), \
}
#define TRIM_REGS_LIST \
{ \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_VREF_DQS_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_VREF_DQS_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_VREF_DQ_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_IB_VREF_DQ_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK0_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK0_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK0_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK0_3), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK1_0), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK1_1), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK1_2), \
DEFINE_REG(REG_EMC, EMC_PMACRO_QUSE_DDLL_RANK1_3), \
}
#define VREF_REGS_PER_CH_LIST \
{ \
DEFINE_REG(REG_EMC0, EMC_TRAINING_OPT_DQS_IB_VREF_RANK0), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_OPT_DQS_IB_VREF_RANK0), \
DEFINE_REG(REG_EMC0, EMC_TRAINING_OPT_DQS_IB_VREF_RANK1), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_OPT_DQS_IB_VREF_RANK1), \
}
#define TRAINING_MOD_REGS_PER_CH_LIST \
{ \
DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_IB_BYTE0), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_IB_BYTE0), \
DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_IB_BYTE1), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_IB_BYTE1), \
DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_IB_BYTE2), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_IB_BYTE2), \
DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_IB_BYTE3), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_IB_BYTE3), \
DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_IB_MISC), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_IB_MISC), \
DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_OB_BYTE0), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_OB_BYTE0), \
DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_OB_BYTE1), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_OB_BYTE1), \
DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_OB_BYTE2), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_OB_BYTE2), \
DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_OB_BYTE3), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_OB_BYTE3), \
DEFINE_REG(REG_EMC0, EMC_TRAINING_RW_OFFSET_OB_MISC), \
DEFINE_REG(REG_EMC1, EMC_TRAINING_RW_OFFSET_OB_MISC), \
}
#define BURST_MC_REGS_LIST \
{ \
DEFINE_REG(REG_MC, MC_EMEM_ARB_CFG), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_OUTSTANDING_REQ), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_REFPB_HP_CTRL), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_REFPB_BANK_CTRL), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_RCD), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_RP), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_RC), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_RAS), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_FAW), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_RRD), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_RAP2PRE), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_WAP2PRE), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_R2R), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_W2W), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_R2W), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_CCDMW), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_W2R), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_TIMING_RFCPB), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DA_TURNS), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DA_COVERS), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_MISC0), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_MISC1), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_MISC2), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_RING1_THROTTLE), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_CTRL), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6), \
DEFINE_REG(REG_MC, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7), \
}
#define BURST_UP_DOWN_REGS_LIST \
{ \
DEFINE_REG(REG_MC, MC_MLL_MPCORER_PTSA_RATE), \
DEFINE_REG(REG_MC, MC_FTOP_PTSA_RATE), \
DEFINE_REG(REG_MC, MC_PTSA_GRANT_DECREMENT), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_XUSB_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_XUSB_1), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_TSEC_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_SDMMCA_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_SDMMCAA_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_SDMMC_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_SDMMCAB_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_PPCS_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_PPCS_1), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_MPCORE_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_HC_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_HC_1), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_AVPC_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_GPU_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_GPU2_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_NVENC_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_NVDEC_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_VIC_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_VI2_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_ISP2_0), \
DEFINE_REG(REG_MC, MC_LATENCY_ALLOWANCE_ISP2_1), \
}
#define DEFINE_REG(type, reg) reg##_INDEX
enum BURST_REGS_LIST;
enum TRIM_REGS_LIST;
enum BURST_MC_REGS_LIST;
enum BURST_UP_DOWN_REGS_LIST;
#undef DEFINE_REG
#define DEFINE_REG(type, reg) type##_##reg##_INDEX
enum BURST_REGS_PER_CH_LIST;
enum TRIM_REGS_PER_CH_LIST;
enum VREF_REGS_PER_CH_LIST;
enum TRAINING_MOD_REGS_PER_CH_LIST;
#undef DEFINE_REG
typedef struct {
uint32_t rev;
char dvfs_ver[60];
uint32_t rate;
uint32_t min_volt;
uint32_t gpu_min_volt;
char clock_src[32];
uint32_t clk_src_emc;
uint32_t needs_training;
uint32_t training_pattern;
uint32_t trained;
uint32_t periodic_training;
uint32_t trained_dram_clktree_c0d0u0;
uint32_t trained_dram_clktree_c0d0u1;
uint32_t trained_dram_clktree_c0d1u0;
uint32_t trained_dram_clktree_c0d1u1;
uint32_t trained_dram_clktree_c1d0u0;
uint32_t trained_dram_clktree_c1d0u1;
uint32_t trained_dram_clktree_c1d1u0;
uint32_t trained_dram_clktree_c1d1u1;
uint32_t current_dram_clktree_c0d0u0;
uint32_t current_dram_clktree_c0d0u1;
uint32_t current_dram_clktree_c0d1u0;
uint32_t current_dram_clktree_c0d1u1;
uint32_t current_dram_clktree_c1d0u0;
uint32_t current_dram_clktree_c1d0u1;
uint32_t current_dram_clktree_c1d1u0;
uint32_t current_dram_clktree_c1d1u1;
uint32_t run_clocks;
uint32_t tree_margin;
uint32_t num_burst;
uint32_t num_burst_per_ch;
uint32_t num_trim;
uint32_t num_trim_per_ch;
uint32_t num_mc_regs;
uint32_t num_up_down;
uint32_t vref_num;
uint32_t training_mod_num;
uint32_t dram_timing_num;
uint32_t ptfv_list[12];
uint32_t burst_regs[221];
uint32_t burst_reg_per_ch[8];
uint32_t shadow_regs_ca_train[221];
uint32_t shadow_regs_quse_train[221];
uint32_t shadow_regs_rdwr_train[221];
uint32_t trim_regs[138];
uint32_t trim_perch_regs[10];
uint32_t vref_perch_regs[4];
uint32_t dram_timings[5];
uint32_t training_mod_regs[20];
uint32_t save_restore_mod_regs[12];
uint32_t burst_mc_regs[33];
uint32_t la_scale_regs[24];
uint32_t min_mrs_wait;
uint32_t emc_mrw;
uint32_t emc_mrw2;
uint32_t emc_mrw3;
uint32_t emc_mrw4;
uint32_t emc_mrw9;
uint32_t emc_mrs;
uint32_t emc_emrs;
uint32_t emc_emrs2;
uint32_t emc_auto_cal_config;
uint32_t emc_auto_cal_config2;
uint32_t emc_auto_cal_config3;
uint32_t emc_auto_cal_config4;
uint32_t emc_auto_cal_config5;
uint32_t emc_auto_cal_config6;
uint32_t emc_auto_cal_config7;
uint32_t emc_auto_cal_config8;
uint32_t emc_cfg_2;
uint32_t emc_sel_dpd_ctrl;
uint32_t emc_fdpd_ctrl_cmd_no_ramp;
uint32_t dll_clk_src;
uint32_t clk_out_enb_x_0_clk_enb_emc_dll;
uint32_t latency;
} tegra_emc_timing_t;
typedef struct {
uint32_t osc_freq;
uint32_t out_freq;
uint32_t feedback_div;
uint32_t input_div;
uint32_t post_div;
} pll_cfg_t;
typedef enum {
OP_SWITCH = 0,
OP_TRAIN = 1,
OP_TRAIN_SWITCH = 2
} TrainMode;
typedef enum {
TEGRA_EMC_SRC_PLLM,
TEGRA_EMC_SRC_PLLC,
TEGRA_EMC_SRC_PLLP,
TEGRA_EMC_SRC_CLKM,
TEGRA_EMC_SRC_PLLM_UD,
TEGRA_EMC_SRC_PLLMB_UD,
TEGRA_EMC_SRC_PLLMB,
TEGRA_EMC_SRC_PLLP_UD,
TEGRA_EMC_SRC_COUNT,
} EmcSource;
enum {
DRAM_TYPE_DDR3 = 0,
DRAM_TYPE_LPDDR4 = 1,
DRAM_TYPE_LPDDR2 = 2,
DRAM_TYPE_DDR2 = 3,
};
enum {
DLL_CHANGE_NONE = 0,
DLL_CHANGE_ON,
DLL_CHANGE_OFF,
};
enum {
DLL_OFF,
DLL_ON
};
enum {
AUTO_PD = 0,
MAN_SR = 2
};
enum {
ASSEMBLY = 0,
ACTIVE
};
enum {
T_RP = 0,
T_FC_LPDDR4,
T_RFC,
T_PDEX,
RL
};
enum {
ONE_RANK = 1,
TWO_RANK = 2
};
enum {
SINGLE_CHANNEL = 0,
DUAL_CHANNEL
};
enum {
DRAM_DEV_SEL_ALL = 0,
DRAM_DEV_SEL_0 = (2 << 30),
DRAM_DEV_SEL_1 = (1 << 30),
};
enum {
EMC_CFG5_QUSE_MODE_NORMAL = 0,
EMC_CFG5_QUSE_MODE_ALWAYS_ON,
EMC_CFG5_QUSE_MODE_INTERNAL_LPBK,
EMC_CFG5_QUSE_MODE_PULSE_INTERN,
EMC_CFG5_QUSE_MODE_PULSE_EXTERN,
EMC_CFG5_QUSE_MODE_DIRECT_QUSE,
};
enum {
DVFS_SEQUENCE = 1,
WRITE_TRAINING_SEQUENCE = 2,
PERIODIC_TRAINING_SEQUENCE = 3,
DVFS_PT1 = 10,
DVFS_UPDATE = 11,
TRAINING_PT1 = 12,
TRAINING_UPDATE = 13,
PERIODIC_TRAINING_UPDATE = 14
};
enum {
TEGRA_DRAM_OVER_TEMP_NONE = 0,
TEGRA_DRAM_OVER_TEMP_REFRESH_X2,
TEGRA_DRAM_OVER_TEMP_REFRESH_X4,
TEGRA_DRAM_OVER_TEMP_THROTTLE,
TEGRA_DRAM_OVER_TEMP_MAX,
};
/* Train all possible DRAM sequences. */
void train_dram(void);
#endif

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/*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018 CTCaer <ctcaer@gmail.com>
* Copyright (c) 2018-2020 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef FUSEE_MTC_B01_H_
#define FUSEE_MTC_B01_H_
#include "mtc.h"
typedef struct {
uint32_t ptfv_dqsosc_movavg_c0d0u0;
uint32_t ptfv_dqsosc_movavg_c0d0u1;
uint32_t ptfv_dqsosc_movavg_c0d1u0;
uint32_t ptfv_dqsosc_movavg_c0d1u1;
uint32_t ptfv_dqsosc_movavg_c1d0u0;
uint32_t ptfv_dqsosc_movavg_c1d0u1;
uint32_t ptfv_dqsosc_movavg_c1d1u0;
uint32_t ptfv_dqsosc_movavg_c1d1u1;
uint32_t ptfv_write_samples;
uint32_t ptfv_dvfs_samples;
uint32_t ptfv_movavg_weight;
uint32_t ptfv_config_ctrl;
} t210_emc_ptfv_list_table;
typedef struct {
uint32_t emc_rc;
uint32_t emc_rfc;
uint32_t emc_rfcpb;
uint32_t emc_refctrl2;
uint32_t emc_rfc_slr;
uint32_t emc_ras;
uint32_t emc_rp;
uint32_t emc_r2w;
uint32_t emc_w2r;
uint32_t emc_r2p;
uint32_t emc_w2p;
uint32_t emc_r2r;
uint32_t emc_tppd;
uint32_t emc_trtm;
uint32_t emc_twtm;
uint32_t emc_tratm;
uint32_t emc_twatm;
uint32_t emc_tr2ref;
uint32_t emc_ccdmw;
uint32_t emc_rd_rcd;
uint32_t emc_wr_rcd;
uint32_t emc_rrd;
uint32_t emc_rext;
uint32_t emc_wext;
uint32_t emc_wdv_chk;
uint32_t emc_wdv;
uint32_t emc_wsv;
uint32_t emc_wev;
uint32_t emc_wdv_mask;
uint32_t emc_ws_duration;
uint32_t emc_we_duration;
uint32_t emc_quse;
uint32_t emc_quse_width;
uint32_t emc_ibdly;
uint32_t emc_obdly;
uint32_t emc_einput;
uint32_t emc_mrw6;
uint32_t emc_einput_duration;
uint32_t emc_puterm_extra;
uint32_t emc_puterm_width;
uint32_t emc_qrst;
uint32_t emc_qsafe;
uint32_t emc_rdv;
uint32_t emc_rdv_mask;
uint32_t emc_rdv_early;
uint32_t emc_rdv_early_mask;
uint32_t emc_refresh;
uint32_t emc_burst_refresh_num;
uint32_t emc_pre_refresh_req_cnt;
uint32_t emc_pdex2wr;
uint32_t emc_pdex2rd;
uint32_t emc_pchg2pden;
uint32_t emc_act2pden;
uint32_t emc_ar2pden;
uint32_t emc_rw2pden;
uint32_t emc_cke2pden;
uint32_t emc_pdex2cke;
uint32_t emc_pdex2mrr;
uint32_t emc_txsr;
uint32_t emc_txsrdll;
uint32_t emc_tcke;
uint32_t emc_tckesr;
uint32_t emc_tpd;
uint32_t emc_tfaw;
uint32_t emc_trpab;
uint32_t emc_tclkstable;
uint32_t emc_tclkstop;
uint32_t emc_mrw7;
uint32_t emc_trefbw;
uint32_t emc_odt_write;
uint32_t emc_fbio_cfg5;
uint32_t emc_fbio_cfg7;
uint32_t emc_cfg_dig_dll;
uint32_t emc_cfg_dig_dll_period;
uint32_t emc_pmacro_ib_rxrt;
uint32_t emc_cfg_pipe_1;
uint32_t emc_cfg_pipe_2;
uint32_t emc_pmacro_quse_ddll_rank0_4;
uint32_t emc_pmacro_quse_ddll_rank0_5;
uint32_t emc_pmacro_quse_ddll_rank1_4;
uint32_t emc_pmacro_quse_ddll_rank1_5;
uint32_t emc_mrw8;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4;
uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5;
uint32_t emc_pmacro_ddll_long_cmd_0;
uint32_t emc_pmacro_ddll_long_cmd_1;
uint32_t emc_pmacro_ddll_long_cmd_2;
uint32_t emc_pmacro_ddll_long_cmd_3;
uint32_t emc_pmacro_ddll_long_cmd_4;
uint32_t emc_pmacro_ddll_short_cmd_0;
uint32_t emc_pmacro_ddll_short_cmd_1;
uint32_t emc_pmacro_ddll_short_cmd_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3;
uint32_t emc_txdsrvttgen;
uint32_t emc_fdpd_ctrl_dq;
uint32_t emc_fdpd_ctrl_cmd;
uint32_t emc_fbio_spare;
uint32_t emc_zcal_interval;
uint32_t emc_zcal_wait_cnt;
uint32_t emc_mrs_wait_cnt;
uint32_t emc_mrs_wait_cnt2;
uint32_t emc_auto_cal_channel;
uint32_t emc_pmacro_dll_cfg_0;
uint32_t emc_pmacro_dll_cfg_1;
uint32_t emc_pmacro_dll_cfg_2;
uint32_t emc_pmacro_autocal_cfg_common;
uint32_t emc_pmacro_zctrl;
uint32_t emc_cfg;
uint32_t emc_cfg_pipe;
uint32_t emc_dyn_self_ref_control;
uint32_t emc_qpop;
uint32_t emc_dqs_brlshft_0;
uint32_t emc_dqs_brlshft_1;
uint32_t emc_cmd_brlshft_2;
uint32_t emc_cmd_brlshft_3;
uint32_t emc_pmacro_pad_cfg_ctrl;
uint32_t emc_pmacro_data_pad_rx_ctrl;
uint32_t emc_pmacro_cmd_pad_rx_ctrl;
uint32_t emc_pmacro_data_rx_term_mode;
uint32_t emc_pmacro_cmd_rx_term_mode;
uint32_t emc_pmacro_cmd_pad_tx_ctrl;
uint32_t emc_pmacro_data_pad_tx_ctrl;
uint32_t emc_pmacro_vttgen_ctrl_0;
uint32_t emc_pmacro_vttgen_ctrl_1;
uint32_t emc_pmacro_vttgen_ctrl_2;
uint32_t emc_pmacro_brick_ctrl_rfu1;
uint32_t emc_pmacro_cmd_brick_ctrl_fdpd;
uint32_t emc_pmacro_brick_ctrl_rfu2;
uint32_t emc_pmacro_data_brick_ctrl_fdpd;
uint32_t emc_pmacro_bg_bias_ctrl_0;
uint32_t emc_cfg_3;
uint32_t emc_pmacro_tx_pwrd_0;
uint32_t emc_pmacro_tx_pwrd_1;
uint32_t emc_pmacro_tx_pwrd_2;
uint32_t emc_pmacro_tx_pwrd_3;
uint32_t emc_pmacro_tx_pwrd_4;
uint32_t emc_pmacro_tx_pwrd_5;
uint32_t emc_config_sample_delay;
uint32_t emc_pmacro_tx_sel_clk_src_0;
uint32_t emc_pmacro_tx_sel_clk_src_1;
uint32_t emc_pmacro_tx_sel_clk_src_2;
uint32_t emc_pmacro_tx_sel_clk_src_3;
uint32_t emc_pmacro_tx_sel_clk_src_4;
uint32_t emc_pmacro_tx_sel_clk_src_5;
uint32_t emc_pmacro_ddll_bypass;
uint32_t emc_pmacro_ddll_pwrd_0;
uint32_t emc_pmacro_ddll_pwrd_1;
uint32_t emc_pmacro_ddll_pwrd_2;
uint32_t emc_pmacro_cmd_ctrl_0;
uint32_t emc_pmacro_cmd_ctrl_1;
uint32_t emc_pmacro_cmd_ctrl_2;
uint32_t emc_pmacro_data_pi_ctrl;
uint32_t emc_pmacro_cmd_pi_ctrl;
uint32_t emc_tr_timing_0;
uint32_t emc_tr_dvfs;
uint32_t emc_tr_ctrl_1;
uint32_t emc_tr_rdv;
uint32_t emc_tr_qpop;
uint32_t emc_tr_rdv_mask;
uint32_t emc_mrw14;
uint32_t emc_tr_qsafe;
uint32_t emc_tr_qrst;
uint32_t emc_training_ctrl;
uint32_t emc_training_settle;
uint32_t emc_training_vref_settle;
uint32_t emc_training_ca_fine_ctrl;
uint32_t emc_training_ca_ctrl_misc;
uint32_t emc_training_ca_ctrl_misc1;
uint32_t emc_training_ca_vref_ctrl;
uint32_t emc_training_quse_cors_ctrl;
uint32_t emc_training_quse_fine_ctrl;
uint32_t emc_training_quse_ctrl_misc;
uint32_t emc_training_quse_vref_ctrl;
uint32_t emc_training_read_fine_ctrl;
uint32_t emc_training_read_ctrl_misc;
uint32_t emc_training_read_vref_ctrl;
uint32_t emc_training_write_fine_ctrl;
uint32_t emc_training_write_ctrl_misc;
uint32_t emc_training_write_vref_ctrl;
uint32_t emc_training_mpc;
uint32_t emc_mrw15;
} t210b01_emc_burst_regs;
typedef struct {
uint32_t emc0_mrw10;
uint32_t emc1_mrw10;
uint32_t emc0_mrw11;
uint32_t emc1_mrw11;
uint32_t emc0_mrw12;
uint32_t emc1_mrw12;
uint32_t emc0_mrw13;
uint32_t emc1_mrw13;
} t210_emc_burst_reg_per_ch;
typedef struct {
uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_0;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_1;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_2;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_3;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_0;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_1;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_2;
uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_3;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_2;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_0;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_1;
uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_2;
uint32_t emc_pmacro_ib_vref_dqs_0;
uint32_t emc_pmacro_ib_vref_dqs_1;
uint32_t emc_pmacro_ib_vref_dq_0;
uint32_t emc_pmacro_ib_vref_dq_1;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_0;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_1;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_2;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_3;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_4;
uint32_t emc_pmacro_ob_ddll_long_dq_rank0_5;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_0;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_1;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_2;
uint32_t emc_pmacro_ob_ddll_long_dq_rank1_3;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_2;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_0;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_1;
uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_2;
uint32_t emc_pmacro_quse_ddll_rank0_0;
uint32_t emc_pmacro_quse_ddll_rank0_1;
uint32_t emc_pmacro_quse_ddll_rank0_2;
uint32_t emc_pmacro_quse_ddll_rank0_3;
uint32_t emc_pmacro_quse_ddll_rank1_0;
uint32_t emc_pmacro_quse_ddll_rank1_1;
uint32_t emc_pmacro_quse_ddll_rank1_2;
uint32_t emc_pmacro_quse_ddll_rank1_3;
} t210_emc_trim_regs;
typedef struct {
uint32_t emc_cmd_brlshft_0;
uint32_t emc_cmd_brlshft_1;
uint32_t emc0_data_brlshft_0;
uint32_t emc1_data_brlshft_0;
uint32_t emc0_data_brlshft_1;
uint32_t emc1_data_brlshft_1;
uint32_t emc_quse_brlshft_0;
uint32_t emc_quse_brlshft_1;
uint32_t emc_quse_brlshft_2;
uint32_t emc_quse_brlshft_3;
} t210_emc_trim_perch_regs;
typedef struct {
uint32_t emc0_training_opt_dqs_ib_vref_rank0;
uint32_t emc1_training_opt_dqs_ib_vref_rank0;
uint32_t emc0_training_opt_dqs_ib_vref_rank1;
uint32_t emc1_training_opt_dqs_ib_vref_rank1;
} t210_emc_vref_perch_regs;
typedef struct {
uint32_t t_rp;
uint32_t t_fc_lpddr4;
uint32_t t_rfc;
uint32_t t_pdex;
uint32_t rl;
} t210_emc_dram_timings;
typedef struct {
uint32_t emc0_training_rw_offset_ib_byte0;
uint32_t emc1_training_rw_offset_ib_byte0;
uint32_t emc0_training_rw_offset_ib_byte1;
uint32_t emc1_training_rw_offset_ib_byte1;
uint32_t emc0_training_rw_offset_ib_byte2;
uint32_t emc1_training_rw_offset_ib_byte2;
uint32_t emc0_training_rw_offset_ib_byte3;
uint32_t emc1_training_rw_offset_ib_byte3;
uint32_t emc0_training_rw_offset_ib_misc;
uint32_t emc1_training_rw_offset_ib_misc;
uint32_t emc0_training_rw_offset_ob_byte0;
uint32_t emc1_training_rw_offset_ob_byte0;
uint32_t emc0_training_rw_offset_ob_byte1;
uint32_t emc1_training_rw_offset_ob_byte1;
uint32_t emc0_training_rw_offset_ob_byte2;
uint32_t emc1_training_rw_offset_ob_byte2;
uint32_t emc0_training_rw_offset_ob_byte3;
uint32_t emc1_training_rw_offset_ob_byte3;
uint32_t emc0_training_rw_offset_ob_misc;
uint32_t emc1_training_rw_offset_ob_misc;
} t210_emc_training_mod_regs;
typedef struct {
uint32_t mc_emem_arb_cfg;
uint32_t mc_emem_arb_outstanding_req;
uint32_t mc_emem_arb_refpb_hp_ctrl;
uint32_t mc_emem_arb_refpb_bank_ctrl;
uint32_t mc_emem_arb_timing_rcd;
uint32_t mc_emem_arb_timing_rp;
uint32_t mc_emem_arb_timing_rc;
uint32_t mc_emem_arb_timing_ras;
uint32_t mc_emem_arb_timing_faw;
uint32_t mc_emem_arb_timing_rrd;
uint32_t mc_emem_arb_timing_rap2pre;
uint32_t mc_emem_arb_timing_wap2pre;
uint32_t mc_emem_arb_timing_r2r;
uint32_t mc_emem_arb_timing_w2w;
uint32_t mc_emem_arb_timing_r2w;
uint32_t mc_emem_arb_timing_ccdmw;
uint32_t mc_emem_arb_timing_w2r;
uint32_t mc_emem_arb_timing_rfcpb;
uint32_t mc_emem_arb_da_turns;
uint32_t mc_emem_arb_da_covers;
uint32_t mc_emem_arb_misc0;
uint32_t mc_emem_arb_misc1;
uint32_t mc_emem_arb_misc2;
uint32_t mc_emem_arb_ring1_throttle;
uint32_t mc_emem_arb_dhyst_ctrl;
uint32_t mc_emem_arb_dhyst_timeout_util_0;
uint32_t mc_emem_arb_dhyst_timeout_util_1;
uint32_t mc_emem_arb_dhyst_timeout_util_2;
uint32_t mc_emem_arb_dhyst_timeout_util_3;
uint32_t mc_emem_arb_dhyst_timeout_util_4;
uint32_t mc_emem_arb_dhyst_timeout_util_5;
uint32_t mc_emem_arb_dhyst_timeout_util_6;
uint32_t mc_emem_arb_dhyst_timeout_util_7;
} t210_emc_burst_mc_regs;
typedef struct {
uint32_t mc_mll_mpcorer_ptsa_rate;
uint32_t mc_ftop_ptsa_rate;
uint32_t mc_ptsa_grant_decrement;
uint32_t mc_latency_allowance_xusb_0;
uint32_t mc_latency_allowance_xusb_1;
uint32_t mc_latency_allowance_tsec_0;
uint32_t mc_latency_allowance_sdmmca_0;
uint32_t mc_latency_allowance_sdmmcaa_0;
uint32_t mc_latency_allowance_sdmmc_0;
uint32_t mc_latency_allowance_sdmmcab_0;
uint32_t mc_latency_allowance_ppcs_0;
uint32_t mc_latency_allowance_ppcs_1;
uint32_t mc_latency_allowance_mpcore_0;
uint32_t mc_latency_allowance_hc_0;
uint32_t mc_latency_allowance_hc_1;
uint32_t mc_latency_allowance_avpc_0;
uint32_t mc_latency_allowance_gpu_0;
uint32_t mc_latency_allowance_gpu2_0;
uint32_t mc_latency_allowance_nvenc_0;
uint32_t mc_latency_allowance_nvdec_0;
uint32_t mc_latency_allowance_vic_0;
uint32_t mc_latency_allowance_vi2_0;
uint32_t mc_latency_allowance_isp2_0;
uint32_t mc_latency_allowance_isp2_1;
} t210_emc_la_scale_regs;
typedef struct {
uint32_t rev;
char dvfs_ver[60];
uint32_t rate_khz;
uint32_t min_volt;
uint32_t gpu_min_volt;
char clock_src[32];
uint32_t clk_src_emc;
uint32_t pll_en_ssc;
uint32_t needs_training;
uint32_t training_pattern;
uint32_t trained;
uint32_t periodic_training;
uint32_t trained_dram_clktree_c0d0u0;
uint32_t trained_dram_clktree_c0d0u1;
uint32_t trained_dram_clktree_c0d1u0;
uint32_t trained_dram_clktree_c0d1u1;
uint32_t trained_dram_clktree_c1d0u0;
uint32_t trained_dram_clktree_c1d0u1;
uint32_t trained_dram_clktree_c1d1u0;
uint32_t trained_dram_clktree_c1d1u1;
uint32_t current_dram_clktree_c0d0u0;
uint32_t current_dram_clktree_c0d0u1;
uint32_t current_dram_clktree_c0d1u0;
uint32_t current_dram_clktree_c0d1u1;
uint32_t current_dram_clktree_c1d0u0;
uint32_t current_dram_clktree_c1d0u1;
uint32_t current_dram_clktree_c1d1u0;
uint32_t current_dram_clktree_c1d1u1;
uint32_t emc_fbio_cfg7;
uint32_t run_clocks;
uint32_t tree_margin;
uint32_t num_burst;
uint32_t num_burst_per_ch;
uint32_t num_trim;
uint32_t num_trim_per_ch;
uint32_t num_mc_regs;
uint32_t num_up_down;
uint32_t vref_num;
uint32_t training_mod_num;
uint32_t dram_timing_num;
t210_emc_ptfv_list_table ptfv_list;
union {
t210b01_emc_burst_regs burst_regs;
uint32_t burst_regs_arr[sizeof(t210b01_emc_burst_regs) / sizeof(uint32_t)];
};
union {
t210_emc_burst_reg_per_ch burst_reg_per_ch;
uint32_t burst_reg_per_ch_arr[sizeof(t210_emc_burst_reg_per_ch) / sizeof(uint32_t)];
};
union {
t210b01_emc_burst_regs shadow_regs_ca_train;
uint32_t shadow_regs_ca_train_arr[sizeof(t210b01_emc_burst_regs) / sizeof(uint32_t)];
};
union {
t210b01_emc_burst_regs shadow_regs_rdwr_train;
uint32_t shadow_regs_rdwr_train_arr[sizeof(t210b01_emc_burst_regs) / sizeof(uint32_t)];
};
union {
t210_emc_trim_regs trim_regs;
uint32_t trim_regs_arr[sizeof(t210_emc_trim_regs) / sizeof(uint32_t)];
};
union {
t210_emc_trim_perch_regs trim_perch_regs;
uint32_t trim_perch_regs_arr[sizeof(t210_emc_trim_perch_regs) / sizeof(uint32_t)];
};
union {
t210_emc_vref_perch_regs vref_perch_regs;
uint32_t vref_perch_regs_arr[sizeof(t210_emc_vref_perch_regs) / sizeof(uint32_t)];
};
t210_emc_dram_timings dram_timings;
uint32_t zq_op_cc_long_zcal;
uint32_t zq_op_cc_short_zcal;
uint32_t zcal_wait_time_ps_cc_long_zcal;
uint32_t zcal_wait_time_ps_cc_short_zcal;
uint32_t tZQCAL_lpddr4;
uint32_t zqcal_before_cc_cutoff;
uint32_t opt_cc_short_zcal;
uint32_t opt_short_zcal;
uint32_t opt_do_sw_qrst;
uint32_t save_restore_clkstop_pd;
uint32_t opt_E90;
uint32_t cya_allow_ref_cc;
uint32_t ref_b4_sref_en;
uint32_t cya_issue_pc_ref;
union {
t210_emc_training_mod_regs training_mod_regs;
uint32_t training_mod_regs_arr[sizeof(t210_emc_training_mod_regs) / sizeof(uint32_t)];
};
uint32_t save_restore_mod_regs[12];
union {
t210_emc_burst_mc_regs burst_mc_regs;
uint32_t burst_mc_regs_arr[sizeof(t210_emc_burst_mc_regs) / sizeof(uint32_t)];
};
union {
t210_emc_la_scale_regs la_scale_regs;
uint32_t la_scale_regs_arr[sizeof(t210_emc_la_scale_regs) / sizeof(uint32_t)];
};
uint32_t unk_0;
uint32_t vtt_vdda_ctrl_0;
uint32_t src_clock_div;
uint32_t vtt_vdda_dual_channel;
uint32_t vtt_vdda_ctrl_1;
uint32_t vtt_vdda_ctrl_2;
uint32_t vtt_vdda_ctrl_3;
uint32_t vtt_vdda_ctrl_4;
uint32_t misc_cfg_0;
uint32_t misc_cfg_1;
uint32_t misc_cfg_2;
uint32_t unk_1;
uint32_t unk_2;
uint32_t pipe_clk_delay;
uint32_t clkchange_delay;
uint32_t pllm_ss_cfg;
uint32_t pllm_ss_ctrl1;
uint32_t pllm_ss_ctrl2;
uint32_t pllmb_ss_cfg;
uint32_t pllmb_ss_ctrl1;
uint32_t pllmb_ss_ctrl2;
uint32_t pllmb_divm;
uint32_t pllmb_divn;
uint32_t pllmb_divp;
uint32_t min_mrs_wait;
uint32_t ramp_wait;
uint32_t emc_mrw;
uint32_t emc_mrw2;
uint32_t emc_mrw3;
uint32_t emc_mrw4;
uint32_t emc_mrw9;
uint32_t emc_mrs;
uint32_t emc_emrs;
uint32_t emc_emrs2;
uint32_t emc_auto_cal_config;
uint32_t emc_auto_cal_config2;
uint32_t emc_auto_cal_config3;
uint32_t emc_auto_cal_config4;
uint32_t emc_auto_cal_config5;
uint32_t emc_auto_cal_config6;
uint32_t emc_auto_cal_config7;
uint32_t emc_auto_cal_config8;
uint32_t emc_cfg_2;
uint32_t emc_sel_dpd_ctrl;
uint32_t emc_fdpd_ctrl_cmd_no_ramp;
uint32_t emc_tr_ctrl_0;
uint32_t dll_clk_src;
uint32_t clk_out_enb_x_0_clk_enb_emc_dll;
uint32_t latency;
uint32_t pllm_misc1_0_pllm_clamp_ph90;
} tegra_b01_emc_timing_t;
_Static_assert(sizeof(tegra_b01_emc_timing_t) == 0x10CC);
void train_dram_mariko(void);
void restore_dram_mariko(void);
#endif

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fusee/fusee-secondary/src/mtc/mtc_tables_b01.h Normal file
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