Exosphere: Change physical segment maps depending on firmware version
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@@ -18,7 +18,8 @@ extern const uint8_t __start_cold[];
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/* warboot_init.c */
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extern unsigned int g_exosphere_target_firmware_for_init;
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void init_dma_controllers(unsigned int target_firmware);
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void set_memory_registers_enable_mmu(void);
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void set_memory_registers_enable_mmu_1x_ttbr0(void);
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void set_memory_registers_enable_mmu_5x_ttbr0(void);
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static void identity_map_all_mappings(uintptr_t *mmu_l1_tbl, uintptr_t *mmu_l3_tbl) {
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static const uintptr_t addrs[] = { TUPLE_FOLD_LEFT_0(EVAL(IDENTIY_MAPPING_ID_MAX), _MMAPID, COMMA) };
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@@ -65,22 +66,34 @@ static void warmboot_map_all_ram_segments(uintptr_t *mmu_l3_tbl) {
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}
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}
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static void tzram_map_all_segments(uintptr_t *mmu_l3_tbl) {
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static void tzram_map_all_segments(uintptr_t *mmu_l3_tbl, unsigned int target_firmware) {
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static const uintptr_t offs[] = { TUPLE_FOLD_LEFT_0(EVAL(TZRAM_SEGMENT_ID_MAX), _MMAPTZS, COMMA) };
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static const size_t sizes[] = { TUPLE_FOLD_LEFT_1(EVAL(TZRAM_SEGMENT_ID_MAX), _MMAPTZS, COMMA) };
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static const size_t increments[] = { TUPLE_FOLD_LEFT_2(EVAL(TZRAM_SEGMENT_ID_MAX), _MMAPTZS, COMMA) };
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static const bool is_executable[] = { TUPLE_FOLD_LEFT_3(EVAL(TZRAM_SEGMENT_ID_MAX), _MMAPTZS, COMMA) };
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static const uintptr_t offs_5x[] = { TUPLE_FOLD_LEFT_0(EVAL(TZRAM_SEGMENT_ID_MAX), _MMAPTZ5XS, COMMA) };
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for(size_t i = 0, offset = 0; i < TZRAM_SEGMENT_ID_MAX; i++) {
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tzram_map_segment(mmu_l3_tbl, TZRAM_SEGMENT_BASE + offset, 0x7C010000ull + offs[i], sizes[i], is_executable[i]);
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uintptr_t off = (target_firmware < EXOSPHERE_TARGET_FIRMWARE_500) ? offs[i] : offs_5x[i];
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tzram_map_segment(mmu_l3_tbl, TZRAM_SEGMENT_BASE + offset, 0x7C010000ull + off, sizes[i], is_executable[i]);
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offset += increments[i];
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}
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}
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static void configure_ttbls(void) {
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uintptr_t *mmu_l1_tbl = (uintptr_t *)(TZRAM_GET_SEGMENT_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64);
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uintptr_t *mmu_l2_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_L2_TRANSLATION_TABLE);
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uintptr_t *mmu_l3_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_L3_TRANSLATION_TABLE);
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static void configure_ttbls(unsigned int target_firmware) {
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uintptr_t *mmu_l1_tbl;
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uintptr_t *mmu_l2_tbl;
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uintptr_t *mmu_l3_tbl;
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if (target_firmware < EXOSPHERE_TARGET_FIRMWARE_500) {
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mmu_l1_tbl = (uintptr_t *)(TZRAM_GET_SEGMENT_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64);
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mmu_l2_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_L2_TRANSLATION_TABLE);
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mmu_l3_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_L3_TRANSLATION_TABLE);
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} else {
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mmu_l1_tbl = (uintptr_t *)(TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800 - 64);
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mmu_l2_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGMENT_ID_L2_TRANSLATION_TABLE);
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mmu_l3_tbl = (uintptr_t *)TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGMENT_ID_L3_TRANSLATION_TABLE);
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}
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mmu_init_table(mmu_l1_tbl, 64); /* 33-bit address space */
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mmu_init_table(mmu_l2_tbl, 4096);
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@@ -101,7 +114,7 @@ static void configure_ttbls(void) {
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mmio_map_all_devices(mmu_l3_tbl);
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lp0_entry_map_all_ram_segments(mmu_l3_tbl);
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warmboot_map_all_ram_segments(mmu_l3_tbl);
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tzram_map_all_segments(mmu_l3_tbl);
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tzram_map_all_segments(mmu_l3_tbl, target_firmware);
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}
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static void do_relocation(const coldboot_crt0_reloc_list_t *reloc_list, size_t index) {
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@@ -117,8 +130,17 @@ static void do_relocation(const coldboot_crt0_reloc_list_t *reloc_list, size_t i
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}
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}
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uintptr_t get_coldboot_crt0_temp_stack_address(void) {
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return TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x800;
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}
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uintptr_t get_coldboot_crt0_stack_address(void) {
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return TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x800;
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if (exosphere_get_target_firmware_for_init() < EXOSPHERE_TARGET_FIRMWARE_500) {
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return TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x800;
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} else {
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return TZRAM_GET_SEGMENT_5X_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x800;
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}
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}
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void coldboot_init(coldboot_crt0_reloc_list_t *reloc_list, uintptr_t start_cold) {
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@@ -154,8 +176,12 @@ void coldboot_init(coldboot_crt0_reloc_list_t *reloc_list, uintptr_t start_cold)
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/* TZRAM accesses should work normally after this point. */
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init_dma_controllers(g_exosphere_target_firmware_for_init);
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configure_ttbls();
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set_memory_registers_enable_mmu();
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configure_ttbls(g_exosphere_target_firmware_for_init);
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if (g_exosphere_target_firmware_for_init < EXOSPHERE_TARGET_FIRMWARE_500) {
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set_memory_registers_enable_mmu_1x_ttbr0();
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} else {
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set_memory_registers_enable_mmu_5x_ttbr0();
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}
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/* Copy or clear the remaining sections */
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for(size_t i = 0; i < reloc_list->nb_relocs_post_mmu_init; i++) {
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