exo2: suspend fixes (sleep/wake now works on hardware)
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@@ -63,6 +63,9 @@ DEFINE_CLK_RST_REG(MISC_CLK_ENB_CFG_ALL_VISIBLE, 28, 1);
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC (0x1A0)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON (0x3E8)
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/* RST_DEV_*_SET */
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#define CLK_RST_CONTROLLER_RST_DEV_L_SET (0x300)
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/* RST_DEV_*_CLR */
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#define CLK_RST_CONTROLLER_RST_DEV_L_CLR (0x304)
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@@ -100,4 +103,6 @@ DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTC_UARTC_CLK_SRC, 29, PLLP_OUT0,
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_ACTMON_ACTMON_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, CLK_S, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
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DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_L_SET_SET_COP_RST, 1, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_L_CLR_CLR_COP_RST, 1, DISABLE, ENABLE);
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@@ -42,6 +42,8 @@
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#define APBDEV_PMC_WAKE_DELAY (0x0E0)
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#define APBDEV_PMC_PWR_DET_VAL (0x0E4)
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#define APBDEV_PMC_CRYPTO_OP (0x0F4)
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#define APBDEV_PMC_SCRATCH31 (0x118)
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#define APBDEV_PMC_SCRATCH32 (0x11C)
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#define APBDEV_PMC_WAKE2_MASK (0x160)
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#define APBDEV_PMC_WAKE2_LVL (0x164)
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#define APBDEV_PMC_WAKE2_STATUS (0x168)
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