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sdmmc: complete abstract logic for Sdmmc1 power controller

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This commit is contained in:
Michael Scire
2020-10-21 12:26:15 -07:00
parent bd9b01e405
commit 9340183541
9 changed files with 429 additions and 15 deletions
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3
libraries/libvapours/include/vapours/dd/dd_io_mapping.hpp
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@@ -20,4 +20,7 @@ namespace ams::dd {
uintptr_t QueryIoMapping(dd::PhysicalAddress phys_addr, size_t size);
u32 ReadIoRegister(dd::PhysicalAddress phys_addr);
void WriteIoRegister(dd::PhysicalAddress phys_addr, u32 value);
}

1
libraries/libvapours/include/vapours/results.hpp
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@@ -41,6 +41,7 @@
#include <vapours/results/nim_results.hpp>
#include <vapours/results/ns_results.hpp>
#include <vapours/results/os_results.hpp>
#include <vapours/results/pcv_results.hpp>
#include <vapours/results/pgl_results.hpp>
#include <vapours/results/pm_results.hpp>
#include <vapours/results/psc_results.hpp>

26
libraries/libvapours/include/vapours/results/pcv_results.hpp Normal file
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@@ -0,0 +1,26 @@
/*
* Copyright (c) 2018-2020 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include <vapours/results/results_common.hpp>
namespace ams::pcv {
R_DEFINE_NAMESPACE_RESULT_MODULE(133);
R_DEFINE_ERROR_RESULT(IllegalRequest, 16);
}

4
libraries/libvapours/include/vapours/tegra/tegra_pmc.hpp
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@@ -202,6 +202,10 @@ DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_VE2, 29, OFF, ON);
DEFINE_PMC_REG(PWRGATE_STATUS_CE123, 9, 3);
DEFINE_PMC_REG_BIT_ENUM(NO_IOPOWER_SDMMC1, 12, DISABLE, ENABLE);
DEFINE_PMC_REG_BIT_ENUM(PWR_DET_SDMMC1, 12, DISABLE, ENABLE);
DEFINE_PMC_REG_BIT_ENUM(PWR_DET_VAL_SDMMC1, 12, DISABLE, ENABLE);
DEFINE_PMC_REG(SET_SW_CLAMP_CRAIL, 0, 1);
DEFINE_PMC_REG_TWO_BIT_ENUM(IO_DPD_REQ_CODE, 30, IDLE, DPD_OFF, DPD_ON, RESERVED3);