kern: Implement exception vector ASM
This commit is contained in:
Michael Scire
@@ -0,0 +1,343 @@
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/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* ams::kern::arm64::SvcHandler64() */
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.section .text._ZN3ams4kern5arm6412SvcHandler64Ev, "ax", %progbits
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.global _ZN3ams4kern5arm6412SvcHandler64Ev
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.type _ZN3ams4kern5arm6412SvcHandler64Ev, %function
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_ZN3ams4kern5arm6412SvcHandler64Ev:
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/* Create a KExceptionContext for the exception. */
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sub sp, sp, #0x120
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/* Save registers needed for ReturnFromException */
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stp x9, x10, [sp, #(8 * 9)]
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str x11, [sp, #(8 * 11)]
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str x18, [sp, #(8 * 18)]
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mrs x8, sp_el0
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mrs x9, elr_el1
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mrs x10, spsr_el1
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mrs x11, tpidr_el0
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/* Save callee-saved registers. */
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stp x19, x20, [sp, #(8 * 19)]
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stp x21, x22, [sp, #(8 * 21)]
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stp x23, x24, [sp, #(8 * 23)]
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stp x25, x26, [sp, #(8 * 25)]
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stp x27, x28, [sp, #(8 * 27)]
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/* Save miscellaneous registers. */
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stp x0, x1, [sp, #(8 * 0)]
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stp x2, x3, [sp, #(8 * 2)]
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stp x4, x5, [sp, #(8 * 4)]
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stp x6, x7, [sp, #(8 * 6)]
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stp x29, x30, [sp, #(8 * 29)]
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stp x8, x9, [sp, #(8 * 31)]
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stp x10, x11, [sp, #(8 * 33)]
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/* Check if the SVC index is out of range. */
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mrs x8, esr_el1
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and x8, x8, #0xFF
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cmp x8, #0x80
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b.ge 3f
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/* Check the specific SVC permission bit for allowal. */
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mov x9, sp
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add x9, x9, x8, lsr#3
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ldrb w9, [x9, #0x120]
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and x10, x8, #0x7
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lsr x10, x9, x10
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tst x10, #1
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b.eq 3f
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/* Check if our preemption state allows us to call SVCs. */
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mrs x10, tpidrro_el0
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ldrh w10, [x10, #0x100]
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cbz w10, 1f
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/* It might not, so check the stack params to see if we must not allow the SVC. */
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ldrb w10, [sp, #(0x120 + 0x14)]
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cbz w10, 3f
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1: /* We can call the SVC. */
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adr x10, _ZN3ams4kern3svc10SvcTable64E
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ldr x11, [x10, x8, lsl#3]
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cbz x11, 3f
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/* Note that we're calling the SVC. */
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mov w10, #1
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strb w10, [sp, #(0x120 + 0x12)]
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strb w8, [sp, #(0x120 + 0x11)]
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/* Invoke the SVC handler. */
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mrs x18, tpidr_el1
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msr daifclr, #2
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blr x11
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msr daifset, #2
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2: /* We completed the SVC, and we should handle DPC. */
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/* Check the dpc flags. */
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ldrb w8, [sp, #(0x120 + 0x10)]
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cbz w8, 4f
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/* We have DPC to do! */
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/* Save registers and call ams::kern::KDpcManager::HandleDpc(). */
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sub sp, sp, #0x40
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stp x0, x1, [sp, #(8 * 0)]
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stp x2, x3, [sp, #(8 * 2)]
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stp x4, x5, [sp, #(8 * 4)]
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stp x6, x7, [sp, #(8 * 6)]
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bl _ZN3ams4kern11KDpcManager9HandleDpcEv
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ldp x0, x1, [sp, #(8 * 0)]
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ldp x2, x3, [sp, #(8 * 2)]
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ldp x4, x5, [sp, #(8 * 4)]
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ldp x6, x7, [sp, #(8 * 6)]
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add sp, sp, #0x40
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b 2b
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3: /* Invalid SVC. */
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/* Setup the context to call into HandleException. */
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stp x0, x1, [sp, #(8 * 0)]
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stp x2, x3, [sp, #(8 * 2)]
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stp x4, x5, [sp, #(8 * 4)]
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stp x6, x7, [sp, #(8 * 6)]
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stp xzr, xzr, [sp, #(8 * 8)]
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stp xzr, xzr, [sp, #(8 * 10)]
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stp xzr, xzr, [sp, #(8 * 12)]
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stp xzr, xzr, [sp, #(8 * 14)]
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stp xzr, xzr, [sp, #(8 * 16)]
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stp xzr, x19, [sp, #(8 * 18)]
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stp x20, x21, [sp, #(8 * 20)]
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stp x22, x23, [sp, #(8 * 22)]
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stp x24, x25, [sp, #(8 * 24)]
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stp x26, x27, [sp, #(8 * 26)]
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stp x28, x29, [sp, #(8 * 28)]
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/* Call ams::kern::arm64::HandleException(ams::kern::arm64::KExceptionContext *) */
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mrs x18, tpidr_el1
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mov x0, sp
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bl _ZN3ams4kern5arm6415HandleExceptionEPNS1_17KExceptionContextE
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/* Restore registers. */
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ldp x30, x8, [sp, #(8 * 30)]
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ldp x9, x10, [sp, #(8 * 32)]
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ldr x11, [sp, #(8 * 34)]
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msr sp_el0, x8
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msr elr_el1, x9
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msr spsr_el1, x10
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msr tpidr_el0, x11
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ldp x0, x1, [sp, #(8 * 0)]
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ldp x2, x3, [sp, #(8 * 2)]
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ldp x4, x5, [sp, #(8 * 4)]
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ldp x6, x7, [sp, #(8 * 6)]
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ldp x8, x9, [sp, #(8 * 8)]
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ldp x10, x11, [sp, #(8 * 10)]
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ldp x12, x13, [sp, #(8 * 12)]
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ldp x14, x15, [sp, #(8 * 14)]
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ldp x16, x17, [sp, #(8 * 16)]
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ldp x18, x19, [sp, #(8 * 18)]
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ldp x20, x21, [sp, #(8 * 20)]
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ldp x22, x23, [sp, #(8 * 22)]
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ldp x24, x25, [sp, #(8 * 24)]
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ldp x26, x27, [sp, #(8 * 26)]
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ldp x28, x29, [sp, #(8 * 28)]
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/* Return. */
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add sp, sp, #0x120
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eret
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4: /* Return from SVC. */
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/* Clear our in-SVC note. */
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strb wzr, [sp, #(0x120 + 0x12)]
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/* Restore registers. */
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ldp x30, x8, [sp, #(8 * 30)]
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ldp x9, x10, [sp, #(8 * 32)]
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ldr x11, [sp, #(8 * 34)]
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msr sp_el0, x8
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msr elr_el1, x9
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msr spsr_el1, x10
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msr tpidr_el0, x11
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/* Clear registers. */
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mov x8, xzr
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mov x9, xzr
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mov x10, xzr
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mov x11, xzr
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mov x12, xzr
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mov x13, xzr
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mov x14, xzr
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mov x15, xzr
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mov x16, xzr
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mov x17, xzr
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mov x18, xzr
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/* Return. */
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add sp, sp, #0x120
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eret
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/* ams::kern::arm64::SvcHandler32() */
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.section .text._ZN3ams4kern5arm6412SvcHandler32Ev, "ax", %progbits
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.global _ZN3ams4kern5arm6412SvcHandler32Ev
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.type _ZN3ams4kern5arm6412SvcHandler32Ev, %function
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_ZN3ams4kern5arm6412SvcHandler32Ev:
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/* Ensure that our registers are 32-bit. */
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mov w0, w0
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mov w1, w1
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mov w2, w2
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mov w3, w3
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mov w4, w4
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mov w5, w5
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mov w6, w6
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mov w7, w7
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/* Create a KExceptionContext for the exception. */
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sub sp, sp, #0x120
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/* Save system registers */
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mrs x17, elr_el1
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mrs x20, spsr_el1
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mrs x19, tpidr_el0
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stp x17, x20, [sp, #(8 * 32)]
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str x19, [sp, #(8 * 34)]
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/* Save registers. */
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stp x0, x1, [sp, #(8 * 0)]
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stp x2, x3, [sp, #(8 * 2)]
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stp x4, x5, [sp, #(8 * 4)]
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stp x6, x7, [sp, #(8 * 6)]
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stp x8, x9, [sp, #(8 * 8)]
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stp x10, x11, [sp, #(8 * 10)]
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stp x12, x13, [sp, #(8 * 12)]
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stp x14, xzr, [sp, #(8 * 14)]
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/* Check if the SVC index is out of range. */
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mrs x16, esr_el1
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and x16, x16, #0xFF
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cmp x16, #0x80
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b.ge 3f
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/* Check the specific SVC permission bit for allowal. */
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mov x20, sp
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add x20, x20, x16, lsr#3
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ldrb w20, [x20, #0x120]
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and x17, x16, #0x7
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lsr x17, x20, x17
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tst x17, #1
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b.eq 3f
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/* Check if our preemption state allows us to call SVCs. */
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mrs x15, tpidrro_el0
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ldrh w15, [x15, #0x100]
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cbz w15, 1f
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/* It might not, so check the stack params to see if we must not allow the SVC. */
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ldrb w15, [sp, #(0x120 + 0x14)]
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cbz w15, 3f
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1: /* We can call the SVC. */
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adr x15, _ZN3ams4kern3svc16SvcTable64From32E
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ldr x19, [x15, x16, lsl#3]
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cbz x19, 3f
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/* Note that we're calling the SVC. */
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mov w15, #1
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strb w15, [sp, #(0x120 + 0x12)]
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strb w16, [sp, #(0x120 + 0x11)]
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/* Invoke the SVC handler. */
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mrs x18, tpidr_el1
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msr daifclr, #2
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blr x19
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msr daifset, #2
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2: /* We completed the SVC, and we should handle DPC. */
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/* Check the dpc flags. */
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ldrb w16, [sp, #(0x120 + 0x10)]
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cbz w16, 4f
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/* We have DPC to do! */
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/* Save registers and call ams::kern::KDpcManager::HandleDpc(). */
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sub sp, sp, #0x20
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stp w0, w1, [sp, #(4 * 0)]
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stp w2, w3, [sp, #(4 * 2)]
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stp w4, w5, [sp, #(4 * 4)]
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stp w6, w7, [sp, #(4 * 6)]
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bl _ZN3ams4kern11KDpcManager9HandleDpcEv
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ldp w0, w1, [sp, #(4 * 0)]
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ldp w2, w3, [sp, #(4 * 2)]
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ldp w4, w5, [sp, #(4 * 4)]
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ldp w6, w7, [sp, #(4 * 6)]
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add sp, sp, #0x20
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b 2b
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3: /* Invalid SVC. */
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/* Setup the context to call into HandleException. */
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stp x0, x1, [sp, #(8 * 0)]
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stp x2, x3, [sp, #(8 * 2)]
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stp x4, x5, [sp, #(8 * 4)]
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stp x6, x7, [sp, #(8 * 6)]
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stp xzr, xzr, [sp, #(8 * 16)]
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stp xzr, xzr, [sp, #(8 * 18)]
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stp xzr, xzr, [sp, #(8 * 20)]
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stp xzr, xzr, [sp, #(8 * 22)]
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stp xzr, xzr, [sp, #(8 * 24)]
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stp xzr, xzr, [sp, #(8 * 26)]
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stp xzr, xzr, [sp, #(8 * 28)]
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stp xzr, xzr, [sp, #(8 * 30)]
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/* Call ams::kern::arm64::HandleException(ams::kern::arm64::KExceptionContext *) */
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mrs x18, tpidr_el1
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mov x0, sp
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bl _ZN3ams4kern5arm6415HandleExceptionEPNS1_17KExceptionContextE
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/* Restore registers. */
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ldp x17, x20, [sp, #(8 * 32)]
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ldr x19, [sp, #(8 * 34)]
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msr elr_el1, x17
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msr spsr_el1, x20
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msr tpidr_el0, x19
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ldp x0, x1, [sp, #(8 * 0)]
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ldp x2, x3, [sp, #(8 * 2)]
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ldp x4, x5, [sp, #(8 * 4)]
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ldp x6, x7, [sp, #(8 * 6)]
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ldp x8, x9, [sp, #(8 * 8)]
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ldp x10, x11, [sp, #(8 * 10)]
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ldp x12, x13, [sp, #(8 * 12)]
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ldp x14, x15, [sp, #(8 * 14)]
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/* Return. */
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add sp, sp, #0x120
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eret
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4: /* Return from SVC. */
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/* Clear our in-SVC note. */
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strb wzr, [sp, #(0x120 + 0x12)]
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/* Restore registers. */
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ldp x8, x9, [sp, #(8 * 8)]
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ldp x10, x11, [sp, #(8 * 10)]
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ldp x12, x13, [sp, #(8 * 12)]
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ldp x14, xzr, [sp, #(8 * 14)]
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ldp x17, x20, [sp, #(8 * 32)]
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ldr x19, [sp, #(8 * 34)]
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msr elr_el1, x17
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msr spsr_el1, x20
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msr tpidr_el0, x19
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/* Return. */
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add sp, sp, #0x120
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eret
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@@ -13,24 +13,32 @@
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <mesosphere.hpp>
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#include <mesosphere/kern_debug_log.hpp>
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#include <mesosphere/svc/kern_svc_tables.hpp>
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#include <vapours/svc/svc_codegen.hpp>
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/* TODO: Enable compilation of this file when the kernel supports supervisor calls. */
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#if 0
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namespace ams::kern::svc {
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namespace {
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#define DECLARE_SVC_STRUCT(ID, RETURN_TYPE, NAME, ...) \
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class NAME { \
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private: \
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using Impl = ::ams::svc::codegen::KernelSvcWrapper<::ams::kern::svc::NAME##64, ::ams::kern::svc::NAME##64From32>; \
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public: \
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static NOINLINE void Call64() { return Impl::Call64(); } \
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static NOINLINE void Call64From32() { return Impl::Call64From32(); } \
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};
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/* TODO: Enable compilation of this file when the kernel supports supervisor calls. */
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#if 0
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#define DECLARE_SVC_STRUCT(ID, RETURN_TYPE, NAME, ...) \
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class NAME { \
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private: \
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using Impl = ::ams::svc::codegen::KernelSvcWrapper<::ams::kern::svc::NAME##64, ::ams::kern::svc::NAME##64From32>; \
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public: \
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static NOINLINE void Call64() { return Impl::Call64(); } \
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static NOINLINE void Call64From32() { return Impl::Call64From32(); } \
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};
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#else
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#define DECLARE_SVC_STRUCT(ID, RETURN_TYPE, NAME, ...) \
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class NAME { \
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public: \
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static NOINLINE void Call64() { MESOSPHERE_LOG("Stubbed Svc"#NAME"64 was called\n"); } \
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static NOINLINE void Call64From32() { MESOSPHERE_LOG("Stubbed Svc"#NAME"64From32 was called\n"); } \
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};
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#endif
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/* Set omit-frame-pointer to prevent GCC from emitting MOV X29, SP instructions. */
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@@ -66,4 +74,3 @@ namespace ams::kern::svc {
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}();
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}
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#endif
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