Cleanup and re-write uart code
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@@ -17,35 +17,81 @@
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#include "uart.h"
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#include "timers.h"
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#include "pinmux.h"
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void uart_config(UartDevice dev) {
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volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
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switch (dev) {
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case UART_A:
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pinmux->uart1_rx = 0;
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pinmux->uart1_tx = (PINMUX_INPUT | PINMUX_PULL_UP);
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pinmux->uart1_rts = 0;
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pinmux->uart1_cts = (PINMUX_INPUT | PINMUX_PULL_DOWN);
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break;
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case UART_B:
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pinmux->uart2_rx = 0;
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pinmux->uart2_tx = (PINMUX_INPUT | PINMUX_PULL_UP);
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pinmux->uart2_rts = 0;
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pinmux->uart2_cts = (PINMUX_INPUT | PINMUX_PULL_DOWN);
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break;
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case UART_C:
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pinmux->uart3_rx = 0;
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pinmux->uart3_tx = (PINMUX_INPUT | PINMUX_PULL_UP);
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pinmux->uart3_rts = 0;
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pinmux->uart3_cts = (PINMUX_INPUT | PINMUX_PULL_DOWN);
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break;
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case UART_D:
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pinmux->uart4_rx = 0;
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pinmux->uart4_tx = (PINMUX_INPUT | PINMUX_PULL_UP);
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pinmux->uart4_rts = 0;
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pinmux->uart4_cts = (PINMUX_INPUT | PINMUX_PULL_DOWN);
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break;
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case UART_E:
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/* Unused. */
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break;
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default: break;
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}
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}
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void uart_init(UartDevice dev, uint32_t baud) {
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volatile tegra_uart_t *uart = uart_get_regs(dev);
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/* Set baud rate. */
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uint32_t rate = (8 * baud + 408000000) / (16 * baud);
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uart->UART_LCR = UART_LCR_DLAB; /* Enable DLAB. */
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uart->UART_THR_DLAB = (uint8_t)rate; /* Divisor latch LSB. */
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uart->UART_IER_DLAB = (uint8_t)(rate >> 8); /* Divisor latch MSB. */
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uart->UART_LCR = 0; /* Diable DLAB. */
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/* Wait for idle state. */
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uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE);
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/* Setup UART in fifo mode. */
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/* Calculate baud rate. */
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uint32_t rate = (8 * baud + 408000000) / (16 * baud);
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/* Setup UART in FIFO mode. */
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uart->UART_IER_DLAB = 0;
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uart->UART_IIR_FCR = UART_FCR_FCR_EN_FIFO | UART_FCR_RX_CLR | UART_FCR_TX_CLR; /* Enable and clear TX and RX FIFOs. */
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(void)uart->UART_LSR;
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udelay(3 * ((baud + 999999) / baud));
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uart->UART_LCR = UART_LCR_WD_LENGTH_8; /* Set word length 8. */
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uart->UART_MCR = 0;
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uart->UART_MSR = 0;
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uart->UART_IRDA_CSR = 0;
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uart->UART_RX_FIFO_CFG = 1; /* Set RX_FIFO trigger level */
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uart->UART_MIE = 0;
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uart->UART_ASR = 0;
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uart->UART_LCR = (UART_LCR_DLAB | UART_LCR_WD_LENGTH_8); /* Enable DLAB and set word length 8. */
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uart->UART_THR_DLAB = (uint8_t)rate; /* Divisor latch LSB. */
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uart->UART_IER_DLAB = (uint8_t)(rate >> 8); /* Divisor latch MSB. */
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uart->UART_LCR &= ~(UART_LCR_DLAB); /* Disable DLAB. */
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/* Flush FIFO. */
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uart->UART_IIR_FCR = (UART_FCR_FCR_EN_FIFO | UART_FCR_RX_CLR | UART_FCR_TX_CLR); /* Enable and clear TX and RX FIFOs. */
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udelay(3 * ((baud + 999999) / baud));
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/* Wait for idle state. */
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uart_wait_idle(dev, UART_VENDOR_STATE_TX_IDLE | UART_VENDOR_STATE_RX_IDLE);
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}
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/* This function blocks until the UART device (dev) is in the desired state (status). Make sure the desired state can be reached! */
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/* This function blocks until the UART device is in the desired state. */
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void uart_wait_idle(UartDevice dev, UartVendorStatus status) {
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while (!(uart_get_regs(dev)->UART_VENDOR_STATUS & status)) {
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/* Wait */
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volatile tegra_uart_t *uart = uart_get_regs(dev);
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if (status & UART_VENDOR_STATE_TX_IDLE) {
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while (!(uart->UART_LSR & UART_LSR_TMTY)) {
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/* Wait */
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}
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}
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if (status & UART_VENDOR_STATE_RX_IDLE) {
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while (uart->UART_LSR & UART_LSR_RDR) {
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/* Wait */
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}
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}
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}
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@@ -53,8 +99,8 @@ void uart_send(UartDevice dev, const void *buf, size_t len) {
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volatile tegra_uart_t *uart = uart_get_regs(dev);
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for (size_t i = 0; i < len; i++) {
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while (uart->UART_LSR & UART_LSR_TX_FIFO_FULL) {
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/* Wait until the TX FIFO isn't full */
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while (!(uart->UART_LSR & UART_LSR_THRE)) {
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/* Wait until it's possible to send data. */
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}
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uart->UART_THR_DLAB = *((const uint8_t *)buf + i);
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}
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@@ -64,8 +110,8 @@ void uart_recv(UartDevice dev, void *buf, size_t len) {
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volatile tegra_uart_t *uart = uart_get_regs(dev);
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for (size_t i = 0; i < len; i++) {
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while (uart->UART_LSR & UART_LSR_RX_FIFO_EMPTY) {
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/* Wait until the RX FIFO isn't empty */
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while (!(uart->UART_LSR & UART_LSR_RDR)) {
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/* Wait until it's possible to receive data. */
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}
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*((uint8_t *)buf + i) = uart->UART_THR_DLAB;
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}
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