thermosphere: major refactor of memory map
- use recursive stage 1 page table (thanks @fincs for this idea) - NULL now unmapped - no identity mapping - image + GICv2 now mapped at the same address for every platform - tempbss mapped just after "real" bss, can now steal unused mem from the latter - no hardcoded VAs for other MMIO devices - tegra: remove timers, use the generic timer instead
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@@ -32,16 +32,13 @@ g_initialKernelEntrypoint:
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start:
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mov x19, #1
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b _startCommon
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.global start2
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.type start2, %function
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start2:
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mov x19, xzr
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_startCommon:
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// Disable interrupts, select sp_el2
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msr daifset, 0b1111
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msr spsel, #1
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// Disable interrupts, select sp_el0 before mmu is enabled
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mrs x20, cntpct_el0
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msr daifset, 0b1111
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msr spsel, #0
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// Set sctlr_el2 ASAP to disable mmu/caching if not already done.
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mov x1, #0x0838
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@@ -52,25 +49,39 @@ _startCommon:
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bl cacheClearLocalDataCacheOnBoot
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cbz x19, 1f
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// "Boot core only" stuff:
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bl cacheClearSharedDataCachesOnBoot
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// Temporarily use temp end region as stack, then create the translation table
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// The stack top is also equal to the mmu table address...
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adr x0, g_loadImageLayout
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ldp x2, x3, [x0, #0x18]
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add x1, x2, x3
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mov sp, x1
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bl memoryMapSetupMmu
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1:
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// Enable MMU, note that the function is not allowed to use any stack
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adr x0, g_loadImageLayout
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ldr x18, =_postMmuEnableReturnAddr
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bl memoryMapEnableMmu
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// This is where we will land on exception return after enabling the MMU:
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_postMmuEnableReturnAddr:
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// Select sp_el2
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msr spsel, #1
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// Get core ID
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// Ensure Aff0 is 4-1 at most (4 cores), and that Aff1, 2 and 3 are 0 (1 cluster only)
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mrs x0, mpidr_el1
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tst x0, #(0xFF << 32)
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bne .
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and x0, x0, #0x00FFFFFF // Aff0 to 2
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cmp x0, #4
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bhs .
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mrs x8, mpidr_el1
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and x8, x8, #0xFF
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// Set stack pointer
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adrp x8, __stacks_top__
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lsl x9, x0, #10
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sub sp, x8, x9
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mov w0, w8
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bl memoryMapGetStackTop
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mov sp, x0
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// Set up x18, other sysregs, BSS, MMU, etc.
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// Set up x18, other sysregs, BSS, etc.
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// Don't call init array to save space?
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mov w0, w8
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mov w1, w19
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bl initSystem
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@@ -92,3 +103,26 @@ _startCommon:
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b _restoreAllRegisters
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.pool
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/*
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typedef struct LoadImageLayout {
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uintptr_t startPa;
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size_t imageSize; // "image" includes "real" BSS but not tempbss
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size_t maxImageSize;
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uintptr_t tempPa;
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size_t maxTempSize;
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size_t tempSize;
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uintptr_t vbar;
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} LoadImageLayout;
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*/
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.global g_loadImageLayout
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g_loadImageLayout:
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.quad __start_pa__
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.quad __max_image_size__
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.quad __image_size__
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.quad __temp_pa__
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.quad __max_temp_size__
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.quad __temp_size__
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.quad __vectors_start__
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