thermosphere: major refactor of memory map

- use recursive stage 1 page table (thanks @fincs for this idea) - NULL now unmapped - no identity mapping - image + GICv2 now mapped at the same address for every platform - tempbss mapped just after "real" bss, can now steal unused mem from the latter - no hardcoded VAs for other MMIO devices - tegra: remove timers, use the generic timer instead
2020-01-17 22:10:26 +00:00
parent 92a291cd41
commit 626f0ecb98
47 changed files with 795 additions and 469 deletions
--- a/thermosphere/src/platform/qemu/devices.c
+++ b/thermosphere/src/platform/qemu/devices.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2019 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "devices.h"
+#include "../../memory_map.h"
+#include "../../utils.h"
+
+#include "uart.h"
+
+void devicesMapAllExtra(void)
+{
+    uartSetRegisterBase(memoryMapPlatformMmio(MEMORY_MAP_PA_UART, 0x1000));
+
+    // Don't broadcast, since it's only ran once per boot by only one core, before the others are started...
+    __tlb_invalidate_el2_local();
+    __dsb();
+    __isb();
+}
--- a/thermosphere/src/platform/qemu/devices.h
+++ b/thermosphere/src/platform/qemu/devices.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2019 Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+void devicesMapAllExtra(void);
--- a/thermosphere/src/platform/qemu/interrupt_config.h
+++ b/thermosphere/src/platform/qemu/interrupt_config.h
@@ -18,17 +18,17 @@

 #include "../../gicv2.h"

-// For both guest and host
-#define MAX_NUM_REGISTERED_INTERRUPTS 512
+#define MEMORY_MAP_PA_GICD              0x08000000ull
+#define MEMORY_MAP_PA_GICC              0x08010000ull
+#define MEMORY_MAP_PA_GICH              0x08030000ull
+#define MEMORY_MAP_PA_GICV              0x08040000ull

 #define GIC_IRQID_PMU                   23
 #define GIC_IRQID_MAINTENANCE           25
 #define GIC_IRQID_NS_PHYS_HYP_TIMER     26
 #define GIC_IRQID_NS_VIRT_TIMER         27
-//#define GIC_IRQID_LEGACY_NFIQ         28 not defined?
 #define GIC_IRQID_SEC_PHYS_TIMER        29
 #define GIC_IRQID_NS_PHYS_TIMER         30
-//#define GIC_IRQID_LEGACY_NIRQ         31 not defined?


 #define GIC_IRQID_NS_VIRT_HYP_TIMER     GIC_IRQID_SPURIOUS // SBSA: 28. Unimplemented
@@ -36,11 +36,3 @@
 #define GIC_IRQID_SEC_VIRT_HYP_TIMER    GIC_IRQID_SPURIOUS // SBSA: 19. Unimplemented

 #define GIC_IRQID_UART                  (32 + 1)
-
-static inline void initGicV2Pointers(ArmGicV2 *gic)
-{
-    gic->gicd = (volatile ArmGicV2Distributor *)0x08000000ull;
-    gic->gicc = (volatile ArmGicV2Controller *)0x08010000ull;
-    gic->gich = (volatile ArmGicV2VirtualInterfaceController *)0x08030000ull;
-    gic->gicv = (volatile ArmGicV2Controller *)0x08040000ull;
-}
--- a/thermosphere/src/platform/qemu/stage2_config.c
+++ b/thermosphere/src/platform/qemu/stage2_config.c
@@ -14,7 +14,9 @@
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

-#include "memory_map.h"
+#include "stage2_config.h"
+#include "interrupt_config.h"
+#include "../../memory_map.h"
 #include "../../utils.h"
 #include "../../mmu.h"
 #include "../../core_ctx.h"
@@ -23,11 +25,10 @@
 #define ADDRSPACESZ    39
 #define ADDRSPACESZ2   ADDRSPACESZ

-static ALIGN(0x1000) u64 g_ttbl[BIT(ADDRSPACESZ - 30)] = {0};
-
-static ALIGN(0x1000) u64 g_vttbl[BIT(ADDRSPACESZ2 - 30)] = {0};
+static TEMPORARY ALIGN(0x1000) u64 g_vttbl[BIT(ADDRSPACESZ2 - 30)] = {0};
 static TEMPORARY ALIGN(0x1000) u64 g_vttbl_l2_mmio_0_0[512] = {0};
 static TEMPORARY ALIGN(0x1000) u64 g_vttbl_l3_0[512] = {0};
+static TEMPORARY uintptr_t g_vttblPaddr;

 static inline void identityMapL1(u64 *tbl, uintptr_t addr, size_t size, u64 attribs)
 {
@@ -44,39 +45,31 @@ static inline void identityMapL3(u64 *tbl, uintptr_t addr, size_t size, u64 attr
    mmu_map_block_range(3, tbl, addr, addr, size, attribs | MMU_PTE_BLOCK_INNER_SHAREBLE);
 }

-uintptr_t configureMemoryMap(u32 *addrSpaceSize)
-{
-    // QEMU virt RAM address space starts at 0x40000000
-    *addrSpaceSize = ADDRSPACESZ;
-    if (currentCoreCtx->isBootCore && !currentCoreCtx->warmboot) {
-        identityMapL1(g_ttbl, 0x00000000ull, BITL(30), ATTRIB_MEMTYPE_DEVICE);
-        identityMapL1(g_ttbl, 0x40000000ull, (BITL(ADDRSPACESZ - 30) - 1ull) << 30, ATTRIB_MEMTYPE_NORMAL);
-    }
-
-    return (uintptr_t)g_ttbl;
-}
-
-uintptr_t configureStage2MemoryMap(u32 *addrSpaceSize)
+uintptr_t stage2Configure(u32 *addrSpaceSize)
 {
    *addrSpaceSize = ADDRSPACESZ2;
-    static const u64 devattrs = MMU_S2AP_RW | MMU_MEMATTR_DEVICE_NGNRE;
+    static const u64 devattrs = 0 | MMU_S2AP_RW | MMU_MEMATTR_DEVICE_NGNRE;
    static const u64 unchanged = MMU_S2AP_RW | MMU_MEMATTR_NORMAL_CACHEABLE_OR_UNCHANGED;

    if (currentCoreCtx->isBootCore) {
+        g_vttblPaddr = va2pa(g_vttbl);
+        uintptr_t *l2pa = (uintptr_t *)va2pa(g_vttbl_l2_mmio_0_0);
+        uintptr_t *l3pa = (uintptr_t *)va2pa(g_vttbl_l3_0);
+
        identityMapL1(g_vttbl, 0, 4ull << 30, unchanged);
        identityMapL1(g_vttbl, 0x40000000ull, (BITL(ADDRSPACESZ2 - 30) - 1ull) << 30, unchanged);
-        mmu_map_table(1, g_vttbl, 0x00000000ull, g_vttbl_l2_mmio_0_0, 0);
+        mmu_map_table(1, g_vttbl, 0x00000000ull, l2pa, 0);

        identityMapL2(g_vttbl_l2_mmio_0_0, 0x08000000ull, BITL(30), unchanged);
-        mmu_map_table(2, g_vttbl_l2_mmio_0_0, 0x08000000ull, g_vttbl_l3_0, 0);
+        mmu_map_table(2, g_vttbl_l2_mmio_0_0, 0x08000000ull, l3pa, 0);

        identityMapL3(g_vttbl_l3_0, 0x08000000ull, BITL(21), unchanged);

        // GICD -> trapped, GICv2 CPU -> vCPU interface, GICH -> trapped (deny access)
-        mmu_unmap_range(3, g_vttbl_l3_0, 0x08000000ull, 0x10000ull);
-        mmu_unmap_range(3, g_vttbl_l3_0, 0x08030000ull, 0x10000ull);
-        mmu_map_page_range(g_vttbl_l3_0, 0x08010000ull, 0x08040000ull, 0x10000ull, devattrs);
+        mmu_unmap_range(3, g_vttbl_l3_0, MEMORY_MAP_PA_GICD, 0x10000ull);
+        mmu_unmap_range(3, g_vttbl_l3_0, MEMORY_MAP_PA_GICH, 0x10000ull);
+        mmu_map_page_range(g_vttbl_l3_0, MEMORY_MAP_PA_GICC, MEMORY_MAP_PA_GICV, 0x10000ull, devattrs);
    }

-    return (uintptr_t)g_vttbl;
+    return g_vttblPaddr;
 }
--- a/thermosphere/src/platform/qemu/stage2_config.h
+++ b/thermosphere/src/platform/qemu/stage2_config.h
@@ -18,5 +18,4 @@

 #include "../../types.h"

-uintptr_t configureMemoryMap(u32 *addrSpaceSize);
-uintptr_t configureStage2MemoryMap(u32 *addrSpaceSize);
+uintptr_t stage2Configure(u32 *addrSpaceSize);
--- a/thermosphere/src/platform/qemu/uart.c
+++ b/thermosphere/src/platform/qemu/uart.c
@@ -28,16 +28,23 @@

 //115200

+static uintptr_t g_uartRegBase;
+
 static inline volatile PL011UartRegisters *uartGetRegisters(UartDevice dev)
 {
    switch (dev) {
        case UART_A:
-            return (volatile PL011UartRegisters *)0x09000000;
+            return (volatile PL011UartRegisters *)g_uartRegBase;
        default:
            return NULL;
    }
 }

+void uartSetRegisterBase(uintptr_t regBase)
+{
+    g_uartRegBase = regBase;
+}
+
 void uartInit(UartDevice dev, u32 baudRate, u32 flags)
 {
    /* The TRM (DDI0183) reads:
--- a/thermosphere/src/platform/qemu/uart.h
+++ b/thermosphere/src/platform/qemu/uart.h
@@ -19,6 +19,8 @@
 #include "../../utils.h"
 #include "interrupt_config.h"

+#define MEMORY_MAP_PA_UART      0x09000000ull
+
 // AMBA PL011 driver
 // Originally from
 /*
@@ -56,10 +58,10 @@ typedef struct PL011UartRegisters {
 } PL011UartRegisters;

 // Data status bits
-#define UART_DATA_ERROR_MASK        0x0F00
+#define PL011_DATA_ERROR_MASK       0x0F00

 // Status reg bits
-#define UART_STATUS_ERROR_MASK      0x0F
+#define PL011_STATUS_ERROR_MASK     0x0F

 // Errors
 #define PL011_OE                    BIT(3)  // Overrun error
@@ -128,6 +130,7 @@ typedef struct PL011UartRegisters {

 #define UART_CLK_IN_HZ              1

+void uartSetRegisterBase(uintptr_t regBase);
 void uartInit(UartDevice dev, u32 baudRate, u32 flags);
 void uartWriteData(UartDevice dev, const void *buffer, size_t size);
 void uartReadData(UartDevice dev, void *buffer, size_t size);