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fusee: Implement BootConfig and Boot Reason handling.

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This commit is contained in:
hexkyz
2018-08-29 18:28:21 +01:00
parent 1cbbdb43d3
commit 611e85e6ee
19 changed files with 299 additions and 109 deletions
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2
fusee/fusee-primary/src/btn.c
View File

@@ -16,7 +16,7 @@ uint32_t btn_read()
res |= BTN_VOL_UP;
uint32_t val = 0;
if (i2c_query(4, 0x3C, 0x15, &val, 1))
if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, 0x15, &val, 1))
{
if (val & 0x4)
res |= BTN_POWER;

4
fusee/fusee-primary/src/di.c
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@@ -36,9 +36,9 @@ void display_init()
/* Power on. */
uint8_t val = 0xD0;
i2c_send(4, 0x3C, MAX77620_REG_LDO0_CFG, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_LDO0_CFG, &val, 1);
val = 0x09;
i2c_send(4, 0x3C, MAX77620_REG_GPIO7, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_GPIO7, &val, 1);
/* Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks. */
car->rst_dev_h_clr = 0x1010000;

26
fusee/fusee-primary/src/hwinit.c
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@@ -203,33 +203,33 @@ void nx_hwinit()
clkrst_reboot(CARDEVICE_UNK);
/* Initialize I2C1 and I2C5. */
i2c_init(0);
i2c_init(4);
i2c_init(I2C_1);
i2c_init(I2C_5);
uint8_t val = 0x40;
i2c_send(4, 0x3C, MAX77620_REG_CNFGBBC, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGBBC, &val, 1);
val = 0x78;
i2c_send(4, 0x3C, MAX77620_REG_ONOFFCNFG1, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &val, 1);
val = 0x38;
i2c_send(4, 0x3C, MAX77620_REG_FPS_CFG0, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG0, &val, 1);
val = 0x3A;
i2c_send(4, 0x3C, MAX77620_REG_FPS_CFG1, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG1, &val, 1);
val = 0x38;
i2c_send(4, 0x3C, MAX77620_REG_FPS_CFG2, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG2, &val, 1);
val = 0xF;
i2c_send(4, 0x3C, MAX77620_REG_FPS_LDO4, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_LDO4, &val, 1);
val = 0xC7;
i2c_send(4, 0x3C, MAX77620_REG_FPS_LDO8, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_LDO8, &val, 1);
val = 0x4F;
i2c_send(4, 0x3C, MAX77620_REG_FPS_SD0, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD0, &val, 1);
val = 0x29;
i2c_send(4, 0x3C, MAX77620_REG_FPS_SD1, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD1, &val, 1);
val = 0x1B;
i2c_send(4, 0x3C, MAX77620_REG_FPS_SD3, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD3, &val, 1);
val = 42; /* 42 = (1125000 - 600000) / 12500 -> 1.125V */
i2c_send(4, 0x3C, MAX77620_REG_SD0, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD0, &val, 1);
/* Configure and lock PMC scratch registers. */
config_pmc_scratch();

26
fusee/fusee-primary/src/i2c.c
View File

@@ -43,16 +43,16 @@ void i2c_init(unsigned int id) {
void i2c_send_pmic_cpu_shutdown_cmd(void) {
uint32_t val = 0;
/* PMIC == Device 4:3C. */
i2c_query(4, 0x3C, 0x41, &val, 1);
i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, 0x41, &val, 1);
val |= 4;
i2c_send(4, 0x3C, 0x41, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, 0x41, &val, 1);
}
/* Queries the value of TI charger bit over I2C. */
bool i2c_query_ti_charger_bit_7(void) {
uint32_t val = 0;
/* TI Charger = Device 0:6B. */
i2c_query(0, 0x6B, 0, &val, 1);
i2c_query(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1);
return (val & 0x80) != 0;
}
@@ -60,34 +60,34 @@ bool i2c_query_ti_charger_bit_7(void) {
void i2c_clear_ti_charger_bit_7(void) {
uint32_t val = 0;
/* TI Charger = Device 0:6B. */
i2c_query(0, 0x6B, 0, &val, 1);
i2c_query(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1);
val &= 0x7F;
i2c_send(0, 0x6B, 0, &val, 1);
i2c_send(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1);
}
/* Sets TI charger bit over I2C. */
void i2c_set_ti_charger_bit_7(void) {
uint32_t val = 0;
/* TI Charger = Device 0:6B. */
i2c_query(0, 0x6B, 0, &val, 1);
i2c_query(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1);
val |= 0x80;
i2c_send(0, 0x6B, 0, &val, 1);
i2c_send(I2C_1, BQ24193_I2C_ADDR, 0, &val, 1);
}
/* Get registers pointer based on I2C ID. */
volatile tegra_i2c_t *i2c_get_registers_from_id(unsigned int id) {
switch (id) {
case 0:
case I2C_1:
return I2C1_REGS;
case 1:
case I2C_2:
return I2C2_REGS;
case 2:
case I2C_3:
return I2C3_REGS;
case 3:
case I2C_4:
return I2C4_REGS;
case 4:
case I2C_5:
return I2C5_REGS;
case 5:
case I2C_6:
return I2C6_REGS;
default:
generic_panic();

14
fusee/fusee-primary/src/i2c.h
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@@ -8,6 +8,20 @@
#define I2C234_BASE 0x7000C000
#define I2C56_BASE 0x7000D000
#define I2C_1 0
#define I2C_2 1
#define I2C_3 2
#define I2C_4 3
#define I2C_5 4
#define I2C_6 5
#define MAX77621_CPU_I2C_ADDR 0x1B
#define MAX77621_GPU_I2C_ADDR 0x1C
#define MAX17050_I2C_ADDR 0x36
#define MAX77620_PWR_I2C_ADDR 0x3C
#define MAX77620_RTC_I2C_ADDR 0x68
#define BQ24193_I2C_ADDR 0x6B
typedef struct {
uint32_t I2C_I2C_CNFG_0;
uint32_t I2C_I2C_CMD_ADDR0_0;

30
fusee/fusee-primary/src/max77620.h
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@@ -11,6 +11,36 @@
#ifndef _MFD_MAX77620_H_
#define _MFD_MAX77620_H_
/* RTC Registers */
#define MAX77620_REG_RTCINT 0x00
#define MAX77620_REG_RTCINTM 0x01
#define MAX77620_REG_RTCCNTLM 0x02
#define MAX77620_REG_RTCCNTL 0x03
#define MAX77620_REG_RTCUPDATE0 0x04
#define MAX77620_REG_RTCUPDATE1 0x05
#define MAX77620_REG_RTCSMPL 0x06
#define MAX77620_REG_RTCSEC 0x07
#define MAX77620_REG_RTCMIN 0x08
#define MAX77620_REG_RTCHOUR 0x09
#define MAX77620_REG_RTCDOW 0x0A
#define MAX77620_REG_RTCMONTH 0x0B
#define MAX77620_REG_RTCYEAR 0x0C
#define MAX77620_REG_RTCDOM 0x0D
#define MAX77620_REG_RTCSECA1 0x0E
#define MAX77620_REG_RTCMINA1 0x0F
#define MAX77620_REG_RTCHOURA1 0x10
#define MAX77620_REG_RTCDOWA1 0x11
#define MAX77620_REG_RTCMONTHA1 0x12
#define MAX77620_REG_RTCYEARA1 0x13
#define MAX77620_REG_RTCDOMA1 0x14
#define MAX77620_REG_RTCSECA2 0x15
#define MAX77620_REG_RTCMINA2 0x16
#define MAX77620_REG_RTCHOURA2 0x17
#define MAX77620_REG_RTCDOWA2 0x18
#define MAX77620_REG_RTCMONTHA2 0x19
#define MAX77620_REG_RTCYEARA2 0x1A
#define MAX77620_REG_RTCDOMA2 0x1B
/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */
#define MAX77620_REG_CNFGGLBL1 0x00
#define MAX77620_REG_CNFGGLBL2 0x01

20
fusee/fusee-primary/src/max7762x.c
View File

@@ -55,11 +55,11 @@ int max77620_regulator_get_status(uint32_t id)
uint8_t val = 0;
if (reg->type == REGULATOR_SD) {
if (i2c_query(4, 0x3C, MAX77620_REG_STATSD, &val, 1))
if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_STATSD, &val, 1))
return (val & reg->status_mask) ? 0 : 1;
}
if (i2c_query(4, 0x3C, reg->cfg_addr, &val, 1))
if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, reg->cfg_addr, &val, 1))
return (val & 8) ? 0 : 1;
return 0;
@@ -73,7 +73,7 @@ int max77620_regulator_config_fps(uint32_t id)
const max77620_regulator_t *reg = &_pmic_regulators[id];
uint8_t val = ((reg->fps_src << 6) | (reg->pu_period << 3) | (reg->pd_period));
if (i2c_send(4, 0x3C, reg->fps_addr, &val, 1)) {
if (i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, reg->fps_addr, &val, 1)) {
return 1;
}
@@ -93,11 +93,11 @@ int max77620_regulator_set_voltage(uint32_t id, uint32_t mv)
uint32_t mult = (mv + reg->mv_step - 1 - reg->mv_min) / reg->mv_step;
uint8_t val = 0;
if (i2c_query(4, 0x3C, reg->volt_addr, &val, 1))
if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, reg->volt_addr, &val, 1))
{
val = ((val & ~reg->volt_mask) | (mult & reg->volt_mask));
if (i2c_send(4, 0x3C, reg->volt_addr, &val, 1))
if (i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, reg->volt_addr, &val, 1))
{
udelay(1000);
return 1;
@@ -117,14 +117,14 @@ int max77620_regulator_enable(uint32_t id, int enable)
uint32_t addr = (reg->type == REGULATOR_SD) ? reg->cfg_addr : reg->volt_addr;
uint8_t val = 0;
if (i2c_query(4, 0x3C, addr, &val, 1))
if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, addr, &val, 1))
{
if (enable)
val = ((val & ~reg->enable_mask) | ((3 << reg->enable_shift) & reg->enable_mask));
else
val &= ~reg->enable_mask;
if (i2c_send(4, 0x3C, addr, &val, 1))
if (i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, addr, &val, 1))
{
udelay(1000);
return 1;
@@ -139,7 +139,7 @@ void max77620_config_default()
for (uint32_t i = 1; i <= REGULATOR_MAX; i++)
{
uint8_t val = 0;
if (i2c_query(4, 0x3C, MAX77620_REG_CID4, &val, 1))
if (i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CID4, &val, 1))
{
max77620_regulator_config_fps(i);
max77620_regulator_set_voltage(i, _pmic_regulators[i].mv_default);
@@ -151,11 +151,11 @@ void max77620_config_default()
}
uint8_t val = 4;
i2c_send(4, 0x3C, MAX77620_REG_SD_CFG2, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD_CFG2, &val, 1);
}
void max77620_low_battery_monitor_config()
{
uint8_t val = (MAX77620_CNFGGLBL1_LBDAC_EN | MAX77620_CNFGGLBL1_LBHYST_N | MAX77620_CNFGGLBL1_LBDAC_N);
i2c_send(4, 0x3C, MAX77620_REG_CNFGGLBL1, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGGLBL1, &val, 1);
}

4
fusee/fusee-primary/src/sdram.c
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@@ -542,9 +542,9 @@ void sdram_init()
const sdram_params_t *params = (const sdram_params_t *)sdram_get_params();
uint8_t val = 5;
i2c_send(4, 0x3C, MAX77620_REG_SD_CFG2, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD_CFG2, &val, 1);
val = 40; /* 40 = (1000 * 1100 - 600000) / 12500 -> 1.1V */
i2c_send(4, 0x3C, MAX77620_REG_SD1, &val, 1);
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD1, &val, 1);
pmc->vddp_sel = params->pmc_vddp_sel;
udelay(params->pmc_vddp_sel_wait);