Merge SD stuff into fusee-secondary. Switch diskio to single-sector reads temporarily
This commit is contained in:
Michael Scire
@@ -1,15 +1,15 @@
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/*
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* Defining registers address and its bit definitions of MAX77620 and MAX20024
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*
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* Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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* Defining registers address and its bit definitions of MAX77620 and MAX20024
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*
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* Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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#ifndef _MAX77620_H_
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#define _MAX77620_H_
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#ifndef _MFD_MAX77620_H_
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#define _MFD_MAX77620_H_
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/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */
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#define MAX77620_REG_CNFGGLBL1 0x00
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@@ -72,7 +72,7 @@
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#define MAX77620_LDO_SLEW_RATE_MASK 0x1
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/* LDO Configuration 3 */
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#define MAX77620_TRACK4_MASK BIT(5)
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#define MAX77620_TRACK4_MASK (1 << 5)
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#define MAX77620_TRACK4_SHIFT 5
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/* Voltage */
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@@ -113,6 +113,29 @@
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#define MAX77620_REG_FPS_SD2 0x51
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#define MAX77620_REG_FPS_SD3 0x52
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#define MAX77620_REG_FPS_SD4 0x53
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#define MAX77620_REG_FPS_NONE 0
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#define MAX77620_FPS_SRC_MASK 0xC0
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#define MAX77620_FPS_SRC_SHIFT 6
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#define MAX77620_FPS_PU_PERIOD_MASK 0x38
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#define MAX77620_FPS_PU_PERIOD_SHIFT 3
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#define MAX77620_FPS_PD_PERIOD_MASK 0x07
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#define MAX77620_FPS_PD_PERIOD_SHIFT 0
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#define MAX77620_FPS_TIME_PERIOD_MASK 0x38
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#define MAX77620_FPS_TIME_PERIOD_SHIFT 3
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#define MAX77620_FPS_EN_SRC_MASK 0x06
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#define MAX77620_FPS_EN_SRC_SHIFT 1
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#define MAX77620_FPS_ENFPS_SW_MASK 0x01
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#define MAX77620_FPS_ENFPS_SW 0x01
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/* Minimum and maximum FPS period time (in microseconds) are
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* different for MAX77620 and Max20024.
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*/
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#define MAX77620_FPS_PERIOD_MIN_US 40
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#define MAX20024_FPS_PERIOD_MIN_US 20
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#define MAX77620_FPS_PERIOD_MAX_US 2560
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#define MAX20024_FPS_PERIOD_MAX_US 5120
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#define MAX77620_REG_FPS_GPIO1 0x54
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#define MAX77620_REG_FPS_GPIO2 0x55
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@@ -128,4 +151,174 @@
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#define MAX77620_REG_DVSSD4 0x5E
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#define MAX20024_REG_MAX_ADD 0x70
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#endif
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#define MAX77620_CID_DIDM_MASK 0xF0
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#define MAX77620_CID_DIDM_SHIFT 4
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/* CNCG2SD */
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#define MAX77620_SD_CNF2_ROVS_EN_SD1 (1 << 1)
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#define MAX77620_SD_CNF2_ROVS_EN_SD0 (1 << 2)
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/* Device Identification Metal */
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#define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF)
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/* Device Indentification OTP */
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#define MAX77620_CID5_DIDO(n) ((n) & 0xF)
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/* SD CNFG1 */
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#define MAX77620_SD_SR_MASK 0xC0
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#define MAX77620_SD_SR_SHIFT 6
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#define MAX77620_SD_POWER_MODE_MASK 0x30
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#define MAX77620_SD_POWER_MODE_SHIFT 4
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#define MAX77620_SD_CFG1_ADE_MASK (1 << 3)
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#define MAX77620_SD_CFG1_ADE_DISABLE 0
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#define MAX77620_SD_CFG1_ADE_ENABLE (1 << 3)
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#define MAX77620_SD_FPWM_MASK 0x04
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#define MAX77620_SD_FPWM_SHIFT 2
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#define MAX77620_SD_FSRADE_MASK 0x01
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#define MAX77620_SD_FSRADE_SHIFT 0
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#define MAX77620_SD_CFG1_FPWM_SD_MASK (1 << 2)
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#define MAX77620_SD_CFG1_FPWM_SD_SKIP 0
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#define MAX77620_SD_CFG1_FPWM_SD_FPWM (1 << 2)
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#define MAX20024_SD_CFG1_MPOK_MASK (1 << 1)
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#define MAX77620_SD_CFG1_FSRADE_SD_MASK (1 << 0)
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#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0
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#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE (1 << 0)
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/* LDO_CNFG2 */
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#define MAX77620_LDO_POWER_MODE_MASK 0xC0
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#define MAX77620_LDO_POWER_MODE_SHIFT 6
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#define MAX20024_LDO_CFG2_MPOK_MASK (1 << 2)
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#define MAX77620_LDO_CFG2_ADE_MASK (1 << 1)
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#define MAX77620_LDO_CFG2_ADE_DISABLE 0
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#define MAX77620_LDO_CFG2_ADE_ENABLE (1 << 1)
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#define MAX77620_LDO_CFG2_SS_MASK (1 << 0)
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#define MAX77620_LDO_CFG2_SS_FAST (1 << 0)
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#define MAX77620_LDO_CFG2_SS_SLOW 0
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#define MAX77620_IRQ_TOP_GLBL_MASK (1 << 7)
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#define MAX77620_IRQ_TOP_SD_MASK (1 << 6)
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#define MAX77620_IRQ_TOP_LDO_MASK (1 << 5)
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#define MAX77620_IRQ_TOP_GPIO_MASK (1 << 4)
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#define MAX77620_IRQ_TOP_RTC_MASK (1 << 3)
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#define MAX77620_IRQ_TOP_32K_MASK (1 << 2)
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#define MAX77620_IRQ_TOP_ONOFF_MASK (1 << 1)
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#define MAX77620_IRQ_LBM_MASK (1 << 3)
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#define MAX77620_IRQ_TJALRM1_MASK (1 << 2)
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#define MAX77620_IRQ_TJALRM2_MASK (1 << 1)
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#define MAX77620_CNFG_GPIO_DRV_MASK (1 << 0)
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#define MAX77620_CNFG_GPIO_DRV_PUSHPULL (1 << 0)
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#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN 0
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#define MAX77620_CNFG_GPIO_DIR_MASK (1 << 1)
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#define MAX77620_CNFG_GPIO_DIR_INPUT (1 << 1)
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#define MAX77620_CNFG_GPIO_DIR_OUTPUT 0
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#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK (1 << 2)
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#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK (1 << 3)
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#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH (1 << 3)
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#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW 0
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#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4)
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#define MAX77620_CNFG_GPIO_INT_FALLING (1 << 4)
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#define MAX77620_CNFG_GPIO_INT_RISING (1 << 5)
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#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6)
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#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6)
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#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6)
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#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6)
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#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6)
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#define MAX77620_IRQ_LVL2_GPIO_EDGE0 (1 << 0)
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#define MAX77620_IRQ_LVL2_GPIO_EDGE1 (1 << 1)
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#define MAX77620_IRQ_LVL2_GPIO_EDGE2 (1 << 2)
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#define MAX77620_IRQ_LVL2_GPIO_EDGE3 (1 << 3)
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#define MAX77620_IRQ_LVL2_GPIO_EDGE4 (1 << 4)
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#define MAX77620_IRQ_LVL2_GPIO_EDGE5 (1 << 5)
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#define MAX77620_IRQ_LVL2_GPIO_EDGE6 (1 << 6)
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#define MAX77620_IRQ_LVL2_GPIO_EDGE7 (1 << 7)
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#define MAX77620_CNFG1_32K_OUT0_EN (1 << 2)
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#define MAX77620_ONOFFCNFG1_SFT_RST (1 << 7)
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#define MAX77620_ONOFFCNFG1_MRT_MASK 0x38
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#define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3
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#define MAX77620_ONOFFCNFG1_SLPEN (1 << 2)
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#define MAX77620_ONOFFCNFG1_PWR_OFF (1 << 1)
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#define MAX20024_ONOFFCNFG1_CLRSE 0x18
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#define MAX77620_ONOFFCNFG2_SFT_RST_WK (1 << 7)
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#define MAX77620_ONOFFCNFG2_WD_RST_WK (1 << 6)
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#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK (1 << 5)
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#define MAX77620_ONOFFCNFG2_WK_ALARM1 (1 << 2)
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#define MAX77620_ONOFFCNFG2_WK_EN0 (1 << 0)
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#define MAX77620_GLBLM_MASK (1 << 0)
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#define MAX77620_WDTC_MASK 0x3
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#define MAX77620_WDTOFFC (1 << 4)
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#define MAX77620_WDTSLPC (1 << 3)
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#define MAX77620_WDTEN (1 << 2)
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#define MAX77620_TWD_MASK 0x3
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#define MAX77620_TWD_2s 0x0
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#define MAX77620_TWD_16s 0x1
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#define MAX77620_TWD_64s 0x2
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#define MAX77620_TWD_128s 0x3
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#define MAX77620_CNFGGLBL1_LBDAC_EN (1 << 7)
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#define MAX77620_CNFGGLBL1_MPPLD (1 << 6)
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#define MAX77620_CNFGGLBL1_LBHYST ((1 << 5) | (1 << 4))
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#define MAX77620_CNFGGLBL1_LBDAC 0x0E
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#define MAX77620_CNFGGLBL1_LBRSTEN (1 << 0)
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/* CNFG BBC registers */
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#define MAX77620_CNFGBBC_ENABLE (1 << 0)
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#define MAX77620_CNFGBBC_CURRENT_MASK 0x06
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#define MAX77620_CNFGBBC_CURRENT_SHIFT 1
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#define MAX77620_CNFGBBC_VOLTAGE_MASK 0x18
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#define MAX77620_CNFGBBC_VOLTAGE_SHIFT 3
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#define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE (1 << 5)
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#define MAX77620_CNFGBBC_RESISTOR_MASK 0xC0
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#define MAX77620_CNFGBBC_RESISTOR_SHIFT 6
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#define MAX77620_FPS_COUNT 3
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/* Interrupts */
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enum {
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MAX77620_IRQ_TOP_GLBL, /* Low-Battery */
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MAX77620_IRQ_TOP_SD, /* SD power fail */
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MAX77620_IRQ_TOP_LDO, /* LDO power fail */
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MAX77620_IRQ_TOP_GPIO, /* TOP GPIO internal int to MAX77620 */
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MAX77620_IRQ_TOP_RTC, /* RTC */
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MAX77620_IRQ_TOP_32K, /* 32kHz oscillator */
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MAX77620_IRQ_TOP_ONOFF, /* ON/OFF oscillator */
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MAX77620_IRQ_LBT_MBATLOW, /* Thermal alarm status, > 120C */
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MAX77620_IRQ_LBT_TJALRM1, /* Thermal alarm status, > 120C */
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MAX77620_IRQ_LBT_TJALRM2, /* Thermal alarm status, > 140C */
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};
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/* GPIOs */
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enum {
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MAX77620_GPIO0,
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MAX77620_GPIO1,
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MAX77620_GPIO2,
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MAX77620_GPIO3,
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MAX77620_GPIO4,
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MAX77620_GPIO5,
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MAX77620_GPIO6,
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MAX77620_GPIO7,
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MAX77620_GPIO_NR,
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};
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/* FPS Source */
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enum max77620_fps_src {
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MAX77620_FPS_SRC_0,
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MAX77620_FPS_SRC_1,
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MAX77620_FPS_SRC_2,
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MAX77620_FPS_SRC_NONE,
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MAX77620_FPS_SRC_DEF,
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};
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enum max77620_chip_id {
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MAX77620,
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MAX20024,
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};
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#endif /* _MFD_MAX77620_H_ */
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