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exo2: implement SmcPowerCpuOn

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This commit is contained in:
Michael Scire
2020-05-13 21:48:07 -07:00
committed by SciresM
parent ab703646d5
commit 3d6baf96a3
4 changed files with 147 additions and 9 deletions
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4
libraries/libexosphere/include/exosphere/tegra/tegra_clkrst.hpp
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@@ -71,6 +71,10 @@ DEFINE_CLK_RST_REG(MISC_CLK_ENB_CFG_ALL_VISIBLE, 28, 1);
#define CLK_RST_CONTROLLER_CLK_ENB_UARTC_INDEX (0x17)
#define CLK_RST_CONTROLLER_CLK_ENB_ACTMON_INDEX (0x17)
/* RST_CPUG_CMPLX_* */
#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET (0x450)
#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR (0x454)
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_ARC_CLK_OVR_ON, 19, OFF, ON);
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_TSEC_CLK_OVR_ON, 20, OFF, ON);
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_TSECB_CLK_OVR_ON, 21, OFF, ON);

35
libraries/libexosphere/include/exosphere/tegra/tegra_pmc.hpp
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@@ -103,6 +103,41 @@ DEFINE_PMC_REG_BIT_ENUM(DPD_SAMPLE_ON, 0, DISABLE, ENABLE);
DEFINE_PMC_REG_BIT_ENUM(DPD_ENABLE_ON, 0, DISABLE, ENABLE);
DEFINE_PMC_REG_BIT_ENUM(DPD_ENABLE_TSC_MULT_EN, 1, DISABLE, ENABLE);
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_TOGGLE_START, 8, DISABLE, ENABLE);
DEFINE_PMC_REG(PWRGATE_TOGGLE_PARTID, 0, 5);
enum APBDEV_PMC_PWRGATE_TOGGLE_PARTID : u8 {
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CRAIL = 0,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_VE = 2,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_PCX = 3,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_MPE = 6,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_SAX = 8,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE1 = 9,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE2 = 10,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE3 = 11,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE0 = 14,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_C0NC = 15,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_SOR = 17,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_DIS = 18,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_DISB = 19,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_XUSBA = 20,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_XUSBB = 21,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_XUSBC = 22,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_VIC = 23,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_IRAM = 24,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_NVDEC = 25,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_NVJPG = 26,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_AUD = 27,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_DFD = 28,
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_VE2 = 29,
};
enum APBDEV_PMC_PWRGATE_STATUS_STATUS {
APBDEV_PMC_PWRGATE_STATUS_STATUS_OFF = 0,
APBDEV_PMC_PWRGATE_STATUS_STATUS_ON = 1,
};
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_CRAIL, 0, OFF, ON);
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_VE, 2, OFF, ON);
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_PCX, 3, OFF, ON);