thermosphere: continue vgic rewrite
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@@ -161,8 +161,6 @@ namespace ams::hvisor {
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using difference_type = ptrdiff_t;
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using iterator = Iterator<false>;
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using const_iterator = Iterator<true>;
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using reverse_iterator = std::reverse_iterator<iterator>;
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using const_reverse_iterator = std::reverse_iterator<const_iterator>;
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constexpr void Initialize(VirqState *storage) { m_storage = storage; }
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@@ -181,24 +179,47 @@ namespace ams::hvisor {
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constexpr iterator begin() { return iterator{m_first, m_storage}; }
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constexpr iterator end() { return iterator{&m_storage[virqListEndIndex], m_storage}; }
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constexpr const_reverse_iterator crbegin() const {
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return const_reverse_iterator{const_iterator{m_last, m_storage}};
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}
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constexpr const_reverse_iterator crend() const { return const_reverse_iterator{cend()}; }
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constexpr const_reverse_iterator rbegin() const { return crbegin(); }
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constexpr const_reverse_iterator rend() const { return crend(); }
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constexpr reverse_iterator rbegin() { return reverse_iterator{iterator{m_first, m_storage}}; }
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constexpr reverse_iterator rend() { return reverse_iterator{end()}; }
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iterator insert(iterator pos, VirqState &elem);
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iterator insert(VirqState &elem);
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iterator erase(iterator startPos, iterator endPos);
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constexpr iterator erase(iterator startPos, iterator endPos)
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{
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VirqState &prev = m_storage[startPos->listPrev];
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VirqState &next = *endPos;
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u32 nextPos = GetStateIndex(*endPos);
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iterator erase(iterator pos) { return erase(pos, std::next(pos)); }
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ENSURE(startPos->IsQueued());
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if (startPos->listPrev != virqListEndIndex) {
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prev.listNext = nextPos;
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} else {
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m_first = &next;
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}
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if (nextPos != virqListEndIndex) {
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next.listPrev = startPos->listPrev;
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} else {
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m_last = &prev;
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}
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for (iterator it = startPos; it != endPos; ++it) {
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it->listPrev = it->listNext = virqListInvalidIndex;
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}
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}
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constexpr iterator erase(iterator pos) { return erase(pos, std::next(pos)); }
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constexpr iterator erase(VirqState &pos) { return erase(iterator{&pos, m_storage}); }
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template<typename Pred>
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void erase_if(Pred p)
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{
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for (iterator it = begin(); l = end(); i != l) {
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if(p(*it)) {
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it = erase(it);
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} else {
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++it;
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}
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}
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}
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};
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@@ -225,7 +246,6 @@ namespace ams::hvisor {
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bool m_distributorEnabled = false;
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private:
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constexpr VirqState &GetVirqState(u32 coreId, u32 id)
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{
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if (id >= 32) {
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@@ -253,12 +273,12 @@ namespace ams::hvisor {
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}
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}
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u32 vgicGetDistributorControlRegister(void)
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u32 GetDistributorControlRegister(void)
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{
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return m_distributorEnabled ? 1 : 0;
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}
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u32 vgicGetDistributorTypeRegister(void)
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u32 GetDistributorTypeRegister(void)
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{
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// See above comment.
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// Therefore, LSPI = 0, SecurityExtn = 0, rest = from physical distributor
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@@ -309,6 +329,18 @@ namespace ams::hvisor {
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void SetSgiPendingState(u32 id, u32 coreId, u32 srcCoreId);
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void SendSgi(u32 id, GicV2Distributor::SgirTargetListFilter filter, u32 coreList);
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void ResampleVirqLevel(VirqState &state);
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void CleanupPendingQueue();
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size_t ChoosePendingInterrupts(VirqState *chosen[], size_t maxNum);
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void UpdateState();
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public:
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static bool ValidateGicdRegisterAccess(size_t offset, size_t sz);
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public:
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void WriteGicdRegister(u32 val, size_t offset, size_t sz);
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u32 ReadGicdRegister(size_t offset, size_t sz);
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};
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}
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