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thermosphere: rewrite sysreg trapping code, add skeleton code for timer val trap handling; support A32 EL1 once again

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This commit is contained in:
TuxSH
2020-01-07 02:17:05 +00:00
parent a67d682c10
commit 2f999497df
9 changed files with 217 additions and 74 deletions
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11
thermosphere/src/exceptions.c
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@@ -96,14 +96,17 @@ void handleLowerElSyncException(ExceptionStackFrame *frame, ExceptionSyndromeReg
switch (esr.ec) {
case Exception_CP15RTTrap:
case Exception_CP15RRTTrap:
handleMcrMrcCP15Trap(frame, esr);
break;
case Exception_CP15RRTTrap:
handleMcrrMrrcCP15Trap(frame, esr);
break;
case Exception_CP14RTTrap:
case Exception_CP14DTTrap:
case Exception_CP14RRTTrap: {
case Exception_CP14RRTTrap:
// A32 stub: Skip instruction, read 0 if necessary (there are debug regs at EL0)
handleSysregAccessA32Stub(frame, esr);
handleA32CP14Trap(frame, esr);
break;
}
case Exception_HypervisorCallA64:
handleHypercall(frame, esr);
break;