sdmmc: implement most of SdmmcController
This commit is contained in:
Michael Scire
@@ -26,6 +26,11 @@
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#include <vapours/util.hpp>
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#include <vapours/results.hpp>
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#include <vapours/reg.hpp>
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#if defined(ATMOSPHERE_BOARD_NINTENDO_NX)
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#include <vapours/tegra.hpp>
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#endif
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#include <vapours/crypto.hpp>
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#include <vapours/svc.hpp>
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@@ -40,14 +40,26 @@ namespace ams::sdmmc {
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R_DEFINE_ERROR_RESULT(AutoCommandResponseTimeoutError, 44);
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R_DEFINE_ERROR_RESULT(CommandCompleteSoftwareTimeout, 45);
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R_DEFINE_ERROR_RESULT(TransferCompleteSoftwareTimeout, 46);
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R_DEFINE_ERROR_RESULT(AbortTransactionSoftwareTimeout, 74);
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R_DEFINE_ERROR_RESULT(CommandInhibitCmdSoftwareTimeout, 75);
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R_DEFINE_ERROR_RESULT(CommandInhibitDatSoftwareTimeout, 76);
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R_DEFINE_ERROR_RESULT(BusySoftwareTimeout, 77);
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R_DEFINE_ERROR_RESULT(AbortTransactionSoftwareTimeout, 74);
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R_DEFINE_ERROR_RESULT(CommandInhibitCmdSoftwareTimeout, 75);
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R_DEFINE_ERROR_RESULT(CommandInhibitDatSoftwareTimeout, 76);
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R_DEFINE_ERROR_RESULT(BusySoftwareTimeout, 77);
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R_DEFINE_ERROR_RESULT(IssueTuningCommandSoftwareTimeout, 78);
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R_DEFINE_ERROR_RESULT(TuningFailed, 79);
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R_DEFINE_ERROR_RESULT(SdCardNotReadyToVoltageSwitch, 96);
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R_DEFINE_ERROR_RESULT(SdCardNotCompleteVoltageSwitch, 97);
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R_DEFINE_ERROR_RANGE(HostControllerUnexpected, 128, 158);
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R_DEFINE_ERROR_RESULT(SdHostStandardUnknownAutoCmdError, 130);
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R_DEFINE_ERROR_RESULT(SdHostStandardUnknownError, 131);
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R_DEFINE_ERROR_RESULT(InternalClockStableSoftwareTimeout, 129);
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R_DEFINE_ERROR_RESULT(SdHostStandardUnknownAutoCmdError, 130);
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R_DEFINE_ERROR_RESULT(SdHostStandardUnknownError, 131);
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R_DEFINE_ERROR_RESULT(SdmmcDllCalibrationSoftwareTimeout, 132);
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R_DEFINE_ERROR_RESULT(SdmmcDllApplicationSoftwareTimeout, 133);
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R_DEFINE_ERROR_RESULT(SdHostStandardFailSwitchTo1_8V, 134);
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R_DEFINE_ERROR_RESULT(DriveStrengthCalibrationNotCompleted, 135);
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R_DEFINE_ERROR_RESULT(DriveStrengthCalibrationSoftwareTimeout, 136);
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R_DEFINE_ERROR_RESULT(SdmmcCompShortToGnd, 137);
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R_DEFINE_ERROR_RESULT(SdmmcCompOpen, 138);
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R_DEFINE_ERROR_RANGE(InternalError, 160, 190);
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R_DEFINE_ERROR_RESULT(NoWaitedInterrupt, 161);
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@@ -24,6 +24,7 @@
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#if defined(ATMOSPHERE_IS_EXOSPHERE)
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//#define AMS_SDMMC_THREAD_SAFE
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//#define AMS_SDMMC_USE_DEVICE_VIRTUAL_ADDRESS
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//#define AMS_SDMMC_USE_PCV_CLOCK_RESET_CONTROL
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//#define AMS_SDMMC_USE_OS_EVENTS
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@@ -32,6 +33,7 @@
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#elif defined(ATMOSPHERE_IS_MESOSPHERE)
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//#define AMS_SDMMC_THREAD_SAFE
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//#define AMS_SDMMC_USE_DEVICE_VIRTUAL_ADDRESS
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//#define AMS_SDMMC_USE_PCV_CLOCK_RESET_CONTROL
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//#define AMS_SDMMC_USE_OS_EVENTS
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@@ -40,6 +42,7 @@
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#elif defined(ATMOSPHERE_IS_STRATOSPHERE)
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#define AMS_SDMMC_THREAD_SAFE
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#define AMS_SDMMC_USE_DEVICE_VIRTUAL_ADDRESS
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#define AMS_SDMMC_USE_PCV_CLOCK_RESET_CONTROL
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#define AMS_SDMMC_USE_OS_EVENTS
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39
libraries/libvapours/include/vapours/tegra.hpp
Normal file
39
libraries/libvapours/include/vapours/tegra.hpp
Normal file
@@ -0,0 +1,39 @@
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/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <vapours/common.hpp>
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#include <vapours/assert.hpp>
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#include <vapours/literals.hpp>
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#include <vapours/util.hpp>
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#include <vapours/results.hpp>
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#include <vapours/reg.hpp>
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#include <vapours/tegra/tegra_ahb_arbc.hpp>
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#include <vapours/tegra/tegra_apb_misc.hpp>
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#include <vapours/tegra/tegra_avp_cache.hpp>
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#include <vapours/tegra/tegra_clkrst.hpp>
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#include <vapours/tegra/tegra_emc.hpp>
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#include <vapours/tegra/tegra_evp.hpp>
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#include <vapours/tegra/tegra_flow_ctlr.hpp>
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#include <vapours/tegra/tegra_ictlr.hpp>
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#include <vapours/tegra/tegra_mc.hpp>
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#include <vapours/tegra/tegra_mselect.hpp>
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#include <vapours/tegra/tegra_pinmux.hpp>
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#include <vapours/tegra/tegra_pg_up.hpp>
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#include <vapours/tegra/tegra_pmc.hpp>
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#include <vapours/tegra/tegra_sb.hpp>
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#include <vapours/tegra/tegra_sysctr0.hpp>
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#include <vapours/tegra/tegra_timer.hpp>
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@@ -0,0 +1,52 @@
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/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <vapours/common.hpp>
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#include <vapours/assert.hpp>
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#include <vapours/literals.hpp>
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#include <vapours/util.hpp>
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#include <vapours/results.hpp>
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#include <vapours/reg.hpp>
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#define AHB_ARBC(x) (0x6000c000 + x)
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#define AHB_ARBITRATION_DISABLE (0x004)
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#define AHB_ARBITRATION_PRIORITY_CTRL (0x008)
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#define AHB_MASTER_SWID (0x018)
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#define AHB_MASTER_SWID_1 (0x038)
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#define AHB_GIZMO_TZRAM (0x054)
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#define AHB_AHB_SPARE_REG (0x110)
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#define AHB_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (AHB_, NAME)
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#define AHB_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (AHB_, NAME, VALUE)
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#define AHB_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (AHB_, NAME, ENUM)
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#define AHB_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(AHB_, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
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#define DEFINE_AHB_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (AHB_, NAME, __OFFSET__, __WIDTH__)
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#define DEFINE_AHB_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (AHB_, NAME, __OFFSET__, ZERO, ONE)
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#define DEFINE_AHB_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (AHB_, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
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#define DEFINE_AHB_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(AHB_, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
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#define DEFINE_AHB_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (AHB_, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
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DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_COP, 1, ENABLE, DISABLE);
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DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_AHBDMA, 5, ENABLE, DISABLE);
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DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_USB, 6, ENABLE, DISABLE);
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DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_USB2, 18, ENABLE, DISABLE);
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DEFINE_AHB_REG(AHB_SPARE_REG_CSITE_PADMACRO3_TRIM_SEL, 0, 5);
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DEFINE_AHB_REG_BIT_ENUM(AHB_SPARE_REG_OBS_OVERRIDE_EN, 5, DISABLE, ENABLE);
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DEFINE_AHB_REG_BIT_ENUM(AHB_SPARE_REG_APB2JTAG_OVERRIDE_EN, 6, DISABLE, ENABLE);
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DEFINE_AHB_REG(AHB_SPARE_REG_AHB_SPARE_REG, 12, 32-12);
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126
libraries/libvapours/include/vapours/tegra/tegra_apb_misc.hpp
Normal file
126
libraries/libvapours/include/vapours/tegra/tegra_apb_misc.hpp
Normal file
@@ -0,0 +1,126 @@
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/*
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* Copyright (c) 2018-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <vapours/common.hpp>
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#include <vapours/assert.hpp>
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#include <vapours/literals.hpp>
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#include <vapours/util.hpp>
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#include <vapours/results.hpp>
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#include <vapours/reg.hpp>
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#define APB_MISC_PP_CONFIG_CTL (0x024)
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#define APB_MISC_GP_ASDBGREG (0x810)
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#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL (0xAB4)
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#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL (0xABC)
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#define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 (0xc00)
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#define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 (0xc00)
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#define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0 (0xc04)
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#define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0 (0xc08)
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#define APB_MISC_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (APB_MISC, NAME)
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#define APB_MISC_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (APB_MISC, NAME, VALUE)
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#define APB_MISC_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (APB_MISC, NAME, ENUM)
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#define APB_MISC_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(APB_MISC, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
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#define DEFINE_APB_MISC_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (APB_MISC, NAME, __OFFSET__, __WIDTH__)
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#define DEFINE_APB_MISC_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (APB_MISC, NAME, __OFFSET__, ZERO, ONE)
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#define DEFINE_APB_MISC_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (APB_MISC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
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#define DEFINE_APB_MISC_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(APB_MISC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
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#define DEFINE_APB_MISC_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (APB_MISC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
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DEFINE_APB_MISC_REG_BIT_ENUM(PP_CONFIG_CTL_JTAG, 6, DISABLE, ENABLE);
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DEFINE_APB_MISC_REG_BIT_ENUM(PP_CONFIG_CTL_TBE, 7, DISABLE, ENABLE);
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DEFINE_APB_MISC_REG(GP_ASDBGREG_CFG2TMC_RAM_SVOP_PDP, 24, 2);
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DEFINE_APB_MISC_REG_BIT_ENUM(GP_EMMC4_PAD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_E_SCH, 0, DISABLE, ENABLE);
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DEFINE_APB_MISC_REG (GP_EMMC4_PAD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_DRVDN_COMP, 2, 6);
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DEFINE_APB_MISC_REG (GP_EMMC4_PAD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_DRVUP_COMP, 8, 6);
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DEFINE_APB_MISC_REG (GP_EMMC4_PAD_CFGPADCTRL_MISC2PMC_EMMC4_ALL_PARK, 14, 13);
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DEFINE_APB_MISC_REG(GP_EMMC4_PAD_PUPD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLU, 1, 1);
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DEFINE_APB_MISC_REG(GP_EMMC4_PAD_PUPD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLD, 2, 1);
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DEFINE_APB_MISC_REG(GP_EMMC4_PAD_PUPD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLD, 22, 1);
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#define DEFINE_SLAVE_SECURITY_REG(RINDEX, INDEX, NAME) DEFINE_APB_MISC_REG_BIT_ENUM(SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG##RINDEX##_##NAME##_SECURITY_EN, INDEX, DISABLE, ENABLE)
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DEFINE_SLAVE_SECURITY_REG(0, 29, STM);
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DEFINE_SLAVE_SECURITY_REG(0, 24, CEC);
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DEFINE_SLAVE_SECURITY_REG(0, 23, ATOMICS);
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DEFINE_SLAVE_SECURITY_REG(0, 22, LA);
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DEFINE_SLAVE_SECURITY_REG(0, 21, HDA);
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DEFINE_SLAVE_SECURITY_REG(0, 20, SATA);
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DEFINE_SLAVE_SECURITY_REG(0, 16, KFUSE);
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DEFINE_SLAVE_SECURITY_REG(0, 15, FUSE);
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DEFINE_SLAVE_SECURITY_REG(0, 14, SE);
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DEFINE_SLAVE_SECURITY_REG(0, 13, PMC);
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DEFINE_SLAVE_SECURITY_REG(0, 11, RTC);
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DEFINE_SLAVE_SECURITY_REG(0, 10, CSITE);
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DEFINE_SLAVE_SECURITY_REG(0, 9, QSPI);
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DEFINE_SLAVE_SECURITY_REG(0, 8, PWM);
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DEFINE_SLAVE_SECURITY_REG(0, 6, DTV);
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DEFINE_SLAVE_SECURITY_REG(0, 4, APE);
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DEFINE_SLAVE_SECURITY_REG(0, 3, PINMUX_AUX);
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DEFINE_SLAVE_SECURITY_REG(0, 2, SATA_AUX);
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DEFINE_SLAVE_SECURITY_REG(0, 1, MISC_REGS);
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DEFINE_SLAVE_SECURITY_REG(1, 31, I2C6);
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DEFINE_SLAVE_SECURITY_REG(1, 30, DVC);
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DEFINE_SLAVE_SECURITY_REG(1, 29, I2C4);
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DEFINE_SLAVE_SECURITY_REG(1, 28, I2C3);
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DEFINE_SLAVE_SECURITY_REG(1, 27, I2C2);
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DEFINE_SLAVE_SECURITY_REG(1, 26, I2C1);
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DEFINE_SLAVE_SECURITY_REG(1, 25, SPI6);
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DEFINE_SLAVE_SECURITY_REG(1, 24, SPI5);
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DEFINE_SLAVE_SECURITY_REG(1, 23, SPI4);
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DEFINE_SLAVE_SECURITY_REG(1, 22, SPI3);
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DEFINE_SLAVE_SECURITY_REG(1, 21, SPI2);
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DEFINE_SLAVE_SECURITY_REG(1, 20, SPI1);
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DEFINE_SLAVE_SECURITY_REG(1, 15, UART_D);
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DEFINE_SLAVE_SECURITY_REG(1, 14, UART_C);
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DEFINE_SLAVE_SECURITY_REG(1, 13, UART_B);
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DEFINE_SLAVE_SECURITY_REG(1, 12, UART_A);
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DEFINE_SLAVE_SECURITY_REG(1, 11, EMCB);
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DEFINE_SLAVE_SECURITY_REG(1, 10, MCB);
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DEFINE_SLAVE_SECURITY_REG(1, 9, EMC1);
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DEFINE_SLAVE_SECURITY_REG(1, 8, MC1);
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DEFINE_SLAVE_SECURITY_REG(1, 5, EMC0);
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DEFINE_SLAVE_SECURITY_REG(1, 4, MC0);
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DEFINE_SLAVE_SECURITY_REG(2, 21, FEK);
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DEFINE_SLAVE_SECURITY_REG(2, 20, PKA1);
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DEFINE_SLAVE_SECURITY_REG(2, 19, SE2);
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DEFINE_SLAVE_SECURITY_REG(2, 16, DVFS);
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DEFINE_SLAVE_SECURITY_REG(2, 15, MIPI_CAL);
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DEFINE_SLAVE_SECURITY_REG(2, 14, XUSB_PADCTL);
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DEFINE_SLAVE_SECURITY_REG(2, 13, XUSB_DEV);
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DEFINE_SLAVE_SECURITY_REG(2, 12, XUSB_HOST);
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DEFINE_SLAVE_SECURITY_REG(2, 11, APB2JTAG);
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DEFINE_SLAVE_SECURITY_REG(2, 10, SOC_THERM);
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DEFINE_SLAVE_SECURITY_REG(2, 9, DP2);
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DEFINE_SLAVE_SECURITY_REG(2, 8, DDS);
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DEFINE_SLAVE_SECURITY_REG(2, 7, MIPIBIF);
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DEFINE_SLAVE_SECURITY_REG(2, 3, SDMMC4);
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DEFINE_SLAVE_SECURITY_REG(2, 2, SDMMC3);
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DEFINE_SLAVE_SECURITY_REG(2, 1, SDMMC2);
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DEFINE_SLAVE_SECURITY_REG(2, 0, SDMMC1);
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#undef DEFINE_SLAVE_SECURITY_REG
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#define SLAVE_SECURITY_REG_BITS_ENUM(RINDEX, NAME, ENUM) APB_MISC_REG_BITS_ENUM(SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG##RINDEX##_##NAME##_SECURITY_EN, ENUM)
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@@ -0,0 +1,40 @@
|
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/*
|
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* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define AVP_CACHE_ADDRESS(x) (0x50040000 + x)
|
||||
|
||||
#define AVP_CACHE_CONFIG (0x000)
|
||||
|
||||
#define AVP_CACHE_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (AVP_CACHE, NAME)
|
||||
#define AVP_CACHE_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (AVP_CACHE, NAME, VALUE)
|
||||
#define AVP_CACHE_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (AVP_CACHE, NAME, ENUM)
|
||||
#define AVP_CACHE_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(AVP_CACHE, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_AVP_CACHE_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (AVP_CACHE, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_AVP_CACHE_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (AVP_CACHE, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_AVP_CACHE_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (AVP_CACHE, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_AVP_CACHE_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(AVP_CACHE, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_AVP_CACHE_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (AVP_CACHE, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(DISABLE_WB, 10, FALSE, TRUE);
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(DISABLE_RB, 11, FALSE, TRUE);
|
||||
263
libraries/libvapours/include/vapours/tegra/tegra_clkrst.hpp
Normal file
263
libraries/libvapours/include/vapours/tegra/tegra_clkrst.hpp
Normal file
@@ -0,0 +1,263 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
/* Clock source enums. */
|
||||
#define CLK_RST_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (CLK_RST_CONTROLLER, NAME)
|
||||
#define CLK_RST_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (CLK_RST_CONTROLLER, NAME, VALUE)
|
||||
#define CLK_RST_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (CLK_RST_CONTROLLER, NAME, ENUM)
|
||||
#define CLK_RST_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(CLK_RST_CONTROLLER, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_CLK_RST_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (CLK_RST_CONTROLLER, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_CLK_RST_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_CLK_RST_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_CLK_RST_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
|
||||
#define CLK_RST_CONTROLLER_RST_SOURCE (0x000)
|
||||
|
||||
#define CLK_RST_CONTROLLER_MISC_CLK_ENB (0x048)
|
||||
#define CLK_RST_CONTROLLER_OSC_CTRL (0x050)
|
||||
#define CLK_RST_CONTROLLER_PLLX_BASE (0x0E0)
|
||||
#define CLK_RST_CONTROLLER_CCLKG_BURST_POLICY (0x368)
|
||||
#define CLK_RST_CONTROLLER_SUPER_CCLKG_DIVIDER (0x36C)
|
||||
#define CLK_RST_CONTROLLER_CCLKLP_BURST_POLICY (0x370)
|
||||
#define CLK_RST_CONTROLLER_SUPER_CCLKLP_DIVIDER (0x374)
|
||||
#define CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2 (0x388)
|
||||
#define CLK_RST_CONTROLLER_SPARE_REG0 (0x55C)
|
||||
|
||||
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA (0x0F8)
|
||||
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB (0x0FC)
|
||||
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC (0x3A0)
|
||||
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD (0x3A4)
|
||||
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE (0x554)
|
||||
|
||||
DEFINE_CLK_RST_REG(MISC_CLK_ENB_CFG_ALL_VISIBLE, 28, 1);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(OSC_CTRL_XOE, 0, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG(OSC_CTRL_XOFS, 4, 6);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLX_BASE_PLLX_ENABLE, 30, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIVISOR, 0, 8);
|
||||
DEFINE_CLK_RST_REG(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIVIDEND, 8, 8);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIS_FROM_CPU_IRQ, 24, NO_IMPACT, DISABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIS_FROM_COP_IRQ, 25, NO_IMPACT, DISABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIS_FROM_CPU_FIQ, 26, NO_IMPACT, DISABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIS_FROM_COP_FIQ, 27, NO_IMPACT, DISABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLKG_DIVIDER_SUPER_CDIV_ENB, 31, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLKLP_DIVIDER_SUPER_CDIV_ENB, 31, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(CCLK_BURST_POLICY_CWAKEUP_IDLE_SOURCE, 0, CLKM, RSVD1, CLKS, RSVD3, PLLP_OUT0, PLLP_OUT4, RSVD6, RSVD7, PLLX_OUT0_LJ, DVFS_CPU_CLK, RSVD10, RSVD11, RSVD12, RSVD13, PLLX_OUT0, DVFS_CPU_CLK_LJ);
|
||||
DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(CCLK_BURST_POLICY_CWAKEUP_RUN_SOURCE, 4, CLKM, RSVD1, CLKS, RSVD3, PLLP_OUT0, PLLP_OUT4, RSVD6, RSVD7, PLLX_OUT0_LJ, DVFS_CPU_CLK, RSVD10, RSVD11, RSVD12, RSVD13, PLLX_OUT0, DVFS_CPU_CLK_LJ);
|
||||
DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(CCLK_BURST_POLICY_CWAKEUP_IRQ_SOURCE, 8, CLKM, RSVD1, CLKS, RSVD3, PLLP_OUT0, PLLP_OUT4, RSVD6, RSVD7, PLLX_OUT0_LJ, DVFS_CPU_CLK, RSVD10, RSVD11, RSVD12, RSVD13, PLLX_OUT0, DVFS_CPU_CLK_LJ);
|
||||
DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(CCLK_BURST_POLICY_CWAKEUP_FIQ_SOURCE, 12, CLKM, RSVD1, CLKS, RSVD3, PLLP_OUT0, PLLP_OUT4, RSVD6, RSVD7, PLLX_OUT0_LJ, DVFS_CPU_CLK, RSVD10, RSVD11, RSVD12, RSVD13, PLLX_OUT0, DVFS_CPU_CLK_LJ);
|
||||
DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(CCLK_BURST_POLICY_CPU_STATE, 28, STDBY, IDLE, RUN, RSVD3, IRQ, RSVD5, RSVD6, RSVD7, FIQ, RSVD9, RSVD10, RSVD11, RSVD12, RSVD13, RSVD14, RSVD15);
|
||||
|
||||
DEFINE_CLK_RST_REG(CPU_SOFTRST_CTRL2_CAR2PMC_CPU_ACK_WIDTH, 0, 12);
|
||||
|
||||
DEFINE_CLK_RST_REG_TWO_BIT_ENUM(SPARE_REG0_CLK_M_DIVISOR, 2, CLK_M_DIVISOR1, CLK_M_DIVISOR2, CLK_M_DIVISOR3, CLK_M_DIVISOR4);
|
||||
|
||||
/* RST_DEVICES */
|
||||
#define CLK_RST_CONTROLLER_RST_DEVICES_L (0x004)
|
||||
#define CLK_RST_CONTROLLER_RST_DEVICES_H (0x008)
|
||||
#define CLK_RST_CONTROLLER_RST_DEVICES_U (0x00C)
|
||||
#define CLK_RST_CONTROLLER_RST_DEVICES_X (0x28C)
|
||||
#define CLK_RST_CONTROLLER_RST_DEVICES_Y (0x2A4)
|
||||
#define CLK_RST_CONTROLLER_RST_DEVICES_V (0x358)
|
||||
#define CLK_RST_CONTROLLER_RST_DEVICES_W (0x35C)
|
||||
|
||||
/* CLK_OUT_ENB */
|
||||
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L (0x010)
|
||||
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H (0x014)
|
||||
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U (0x018)
|
||||
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X (0x280)
|
||||
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_Y (0x298)
|
||||
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_V (0x360)
|
||||
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_W (0x364)
|
||||
|
||||
/* CLK_SOURCE */
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 (0x124)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 (0x128)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA (0x178)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB (0x17C)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC (0x1A0)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT (0x3B4)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON (0x3E8)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF (0x62C)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_SOC (0x630)
|
||||
|
||||
/* RST_DEV_*_SET */
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_L_SET (0x300)
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_H_SET (0x308)
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_U_SET (0x310)
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_V_SET (0x430)
|
||||
|
||||
/* RST_DEV_*_CLR */
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_L_CLR (0x304)
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_H_CLR (0x30C)
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_U_CLR (0x314)
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_V_CLR (0x434)
|
||||
|
||||
/* CLK_ENB_*_SET */
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_L_SET (0x320)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_H_SET (0x328)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_U_SET (0x330)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_V_SET (0x440)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_W_SET (0x448)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_X_SET (0x284)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_Y_SET (0x29C)
|
||||
|
||||
/* CLK_ENB_*_CLR */
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR (0x324)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR (0x32C)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR (0x334)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_X_CLR (0x288)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_Y_CLR (0x2A0)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_V_CLR (0x444)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_W_CLR (0x44C)
|
||||
|
||||
/* CLK_ENB_*_INDEX */
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_I2C1_INDEX (0x0C)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_I2C5_INDEX (0x0F)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_UARTA_INDEX (0x06)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_UARTB_INDEX (0x07)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_UARTC_INDEX (0x17)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_ACTMON_INDEX (0x17)
|
||||
|
||||
/* RST_CPUG_CMPLX_* */
|
||||
#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET (0x450)
|
||||
#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR (0x454)
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_ARC_CLK_OVR_ON, 19, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_TSEC_CLK_OVR_ON, 20, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_TSECB_CLK_OVR_ON, 21, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_ISPB_CLK_OVR_ON, 22, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_TZRAM_CLK_OVR_ON, 23, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_QSPI_CLK_OVR_ON, 24, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_A9AVP_CLK_OVR_ON, 26, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_MPCORE_MSELECT_CLK_OVR_ON, 27, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_SDMMC1_LEGACY_TMCLK_OVR_ON, 28, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_SDMMC2_LEGACY_TMCLK_OVR_ON, 29, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_SDMMC3_LEGACY_TMCLK_OVR_ON, 30, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_SDMMC4_LEGACY_TMCLK_OVR_ON, 31, OFF, ON);
|
||||
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_I2C1_I2C1_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_I2C1_I2C1_CLK_DIVISOR, 0, 8);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_I2C5_I2C5_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_I2C5_I2C5_CLK_DIVISOR, 0, 8);
|
||||
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTA_UARTA_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTB_UARTB_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTC_UARTC_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_MSELECT_MSELECT_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT2, PLLC4_OUT1, CLK_S, CLK_M, PLLC4_OUT0);
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_MSELECT_MSELECT_CLK_DIVISOR, 0, 8);
|
||||
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_ACTMON_ACTMON_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, CLK_S, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_DVFS_REF_DVFS_REF_DIVISOR, 0, 8);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_DVFS_REF_DVFS_REF_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_DVFS_SOC_DVFS_SOC_DIVISOR, 0, 8);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_DVFS_SOC_DVFS_SOC_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_L_SET_SET_COP_RST, 1, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_L_CLR_CLR_COP_RST, 1, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CPURESET0, 0, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CPURESET1, 1, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CPURESET2, 2, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CPURESET3, 3, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET0, 16, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET1, 17, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET2, 18, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET3, 19, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_NONCPURESET, 29, DISABLE, ENABLE);
|
||||
|
||||
/* TODO: Actually include all devices. */
|
||||
#define CLK_RST_FOREACH_DEVICE(HANDLER) \
|
||||
HANDLER(L, CPU, 0, 0) \
|
||||
HANDLER(L, RTC, 0, 4) \
|
||||
HANDLER(L, TMR, 0, 5) \
|
||||
HANDLER(L, GPIO, 0, 8) \
|
||||
HANDLER(L, USBD, 0, 22) \
|
||||
HANDLER(L, CACHE2, 0, 31) \
|
||||
HANDLER(H, MEM, 1, 0) \
|
||||
HANDLER(H, AHBDMA, 1, 1) \
|
||||
HANDLER(H, APBDMA, 1, 2) \
|
||||
HANDLER(H, PMC, 1, 6) \
|
||||
HANDLER(H, FUSE, 1, 7) \
|
||||
HANDLER(H, KFUSE, 1, 8) \
|
||||
HANDLER(H, I2C5, 1, 15) \
|
||||
HANDLER(H, EMC, 1, 25) \
|
||||
HANDLER(H, USB2, 1, 26) \
|
||||
HANDLER(U, CSITE, 2, 9) \
|
||||
HANDLER(U, IRAMA, 2, 20) \
|
||||
HANDLER(U, IRAMB, 2, 21) \
|
||||
HANDLER(U, IRAMC, 2, 22) \
|
||||
HANDLER(U, IRAMD, 2, 23) \
|
||||
HANDLER(U, CRAM2, 2, 24) \
|
||||
HANDLER(V, CPUG, 3, 0) \
|
||||
HANDLER(V, MSELECT, 3, 3) \
|
||||
HANDLER(V, SPDIF_DOUBLER, 3, 22) \
|
||||
HANDLER(V, ACTMON, 3, 23) \
|
||||
HANDLER(V, TZRAM, 3, 30) \
|
||||
HANDLER(V, SE, 3, 31) \
|
||||
HANDLER(W, PCIERX0, 4, 2) \
|
||||
HANDLER(W, PCIERX1, 4, 3) \
|
||||
HANDLER(W, PCIERX2, 4, 4) \
|
||||
HANDLER(W, PCIERX3, 4, 5) \
|
||||
HANDLER(W, PCIERX4, 4, 6) \
|
||||
HANDLER(W, PCIERX5, 4, 7) \
|
||||
HANDLER(W, ENTROPY, 4, 21) \
|
||||
HANDLER(W, DVFS, 4, 27) \
|
||||
HANDLER(W, MC1, 4, 30) \
|
||||
HANDLER(X, MC_CAPA, 5, 7) \
|
||||
HANDLER(X, MC_CBPA, 5, 8) \
|
||||
HANDLER(X, MC_CPU, 5, 9) \
|
||||
HANDLER(X, MC_BBC, 5, 10) \
|
||||
HANDLER(X, EMC_DLL, 5, 14) \
|
||||
HANDLER(X, GPU, 5, 24) \
|
||||
HANDLER(X, DBGAPB, 5, 25) \
|
||||
HANDLER(X, PLLG_REF, 5, 29) \
|
||||
HANDLER(Y, MC_CCPA, 6, 8) \
|
||||
HANDLER(Y, MC_CDPA, 6, 9) \
|
||||
HANDLER(Y, PLLP_OUT_CPU, 6, 31)
|
||||
|
||||
#define CLK_RST_DEFINE_SET_CLR_REG(REGISTER, DEVICE, REGISTER_INDEX, DEVICE_INDEX) \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(CLK_ENB_##REGISTER##_SET_SET_CLK_ENB_##DEVICE, DEVICE_INDEX, DISABLE, ENABLE); \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(CLK_ENB_##REGISTER##_CLR_CLR_CLK_ENB_##DEVICE, DEVICE_INDEX, DISABLE, ENABLE); \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(CLK_OUT_ENB_##REGISTER##_CLK_ENB_##DEVICE, DEVICE_INDEX, DISABLE, ENABLE); \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(CLK_ENB_##REGISTER##_CLK_ENB_##DEVICE, DEVICE_INDEX, DISABLE, ENABLE); \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_##REGISTER##_SET_SET_##DEVICE##_RST, DEVICE_INDEX, DISABLE, ENABLE); \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_##REGISTER##_CLR_CLR_##DEVICE##_RST, DEVICE_INDEX, DISABLE, ENABLE); \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_##REGISTER##_##DEVICE##_RST, DEVICE_INDEX, DISABLE, ENABLE); \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEVICES_##REGISTER##_SWR_##DEVICE##_RST, DEVICE_INDEX, DISABLE, ENABLE);
|
||||
|
||||
CLK_RST_FOREACH_DEVICE(CLK_RST_DEFINE_SET_CLR_REG)
|
||||
|
||||
#undef CLK_RST_DEFINE_SET_CLR_REG
|
||||
|
||||
122
libraries/libvapours/include/vapours/tegra/tegra_emc.hpp
Normal file
122
libraries/libvapours/include/vapours/tegra/tegra_emc.hpp
Normal file
@@ -0,0 +1,122 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define EMC_ADDRESS(x) (0x7001B000 + x)
|
||||
#define EMC0_ADDRESS(x) (0x7001E000 + x)
|
||||
#define EMC1_ADDRESS(x) (0x7001F000 + x)
|
||||
|
||||
#define EMC_CFG (0x00C)
|
||||
#define EMC_ADR_CFG (0x010)
|
||||
#define EMC_TIMING_CONTROL (0x028)
|
||||
#define EMC_SELF_REF (0x0E0)
|
||||
#define EMC_MRW (0x0E8)
|
||||
#define EMC_FBIO_CFG5 (0x104)
|
||||
#define EMC_MRW3 (0x138)
|
||||
#define EMC_AUTO_CAL_CONFIG (0x2A4)
|
||||
#define EMC_REQ_CTRL (0x2B0)
|
||||
#define EMC_EMC_STATUS (0x2B4)
|
||||
#define EMC_CFG_DIG_DLL (0x2BC)
|
||||
#define EMC_ZCAL_INTERVAL (0x2E0)
|
||||
#define EMC_PMC_SCRATCH3 (0x448)
|
||||
#define EMC_FBIO_CFG7 (0x584)
|
||||
#define EMC_PMACRO_CFG_PM_GLOBAL_0 (0xC30)
|
||||
#define EMC_PMACRO_TRAINING_CTRL_0 (0xCF8)
|
||||
#define EMC_PMACRO_TRAINING_CTRL_1 (0xCFC)
|
||||
|
||||
#define EMC_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (EMC, NAME)
|
||||
#define EMC_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (EMC, NAME, VALUE)
|
||||
#define EMC_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (EMC, NAME, ENUM)
|
||||
#define EMC_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(EMC, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_EMC_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (EMC, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_EMC_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (EMC, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_EMC_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (EMC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_EMC_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(EMC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_EMC_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (EMC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(CFG_DYN_SELF_REF, 28, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(CFG_DRAM_ACPD, 29, NO_POWERDOWN, ACTIVE_POWERDOWN);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(ADR_CFG_EMEM_NUMDEV, 0, N1, N2);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(TIMING_CONTROL_TIMING_UPDATE, 0, DISABLED, ENABLED);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(SELF_REF_SELF_REF_CMD, 0, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(SELF_REF_ACTIVE_SELF_REF, 8, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_TWO_BIT_ENUM(SELF_REF_SREF_DEV_SELECTN, 30, BOTH, DEV1, DEV0, RESERVED);
|
||||
|
||||
DEFINE_EMC_REG(MRW_OP, 0, 8);
|
||||
DEFINE_EMC_REG(MRW_MA, 16, 8);
|
||||
DEFINE_EMC_REG_TWO_BIT_ENUM(MRW_CNT, 26, SHORT, LONG, EXT1, EXT2);
|
||||
DEFINE_EMC_REG_TWO_BIT_ENUM(MRW_DEV_SELECTN, 30, BOTH, DEV1, DEV0, RESERVED);
|
||||
|
||||
DEFINE_EMC_REG_TWO_BIT_ENUM(FBIO_CFG5_DRAM_TYPE, 0, DDR4, LPDDR4, LPDDR2, DDR2);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(AUTO_CAL_CONFIG_AUTO_CAL_MEASURE_STALL, 9, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(AUTO_CAL_CONFIG_AUTO_CAL_UPDATE_STALL, 10, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(AUTO_CAL_CONFIG_AUTO_CAL_START, 31, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_EMC_REG(REQ_CTRL_STALL_ALL_READS, 0, 1);
|
||||
DEFINE_EMC_REG(REQ_CTRL_STALL_ALL_WRITES, 1, 1);
|
||||
|
||||
DEFINE_EMC_REG_TWO_BIT_ENUM(EMC_STATUS_DRAM_IN_SELF_REFRESH, 8, DISABLED, DEV0_ENABLED, DEV1_ENABLED, BOTH_ENABLED);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(EMC_STATUS_DRAM_DEV0_IN_SELF_REFRESH, 8, DISABLED, ENABLED);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(EMC_STATUS_NO_OUTSTANDING_TRANSACTIONS, 2, WAITING, COMPLETED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(EMC_STATUS_TIMING_UPDATE_STALLED, 23, DONE, BUSY);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(CFG_DIG_DLL_CFG_DLL_EN, 0, DISABLED, ENABLED);
|
||||
|
||||
DEFINE_EMC_REG(ZCAL_INTERVAL_LO, 0, 10);
|
||||
DEFINE_EMC_REG(ZCAL_INTERVAL_HI, 10, 14);
|
||||
|
||||
DEFINE_EMC_REG(PMC_SCRATCH3_DDR_CNTRL, 0, 19);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMC_SCRATCH3_WEAK_BIAS, 30, DISABLED, ENABLED);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(FBIO_CFG7_CH1_ENABLE, 2, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE0, 16, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE1, 17, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE2, 18, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE3, 19, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE4, 20, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE5, 21, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE6, 22, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE7, 23, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD0, 24, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD1, 25, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD2, 26, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD3, 27, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_0_CH0_TRAINING_ENABLED, 0, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_0_CH0_TRAINING_TRAIN_QPOP, 1, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_0_CH0_TRAINING_RX_E_DIRECT_ZI, 2, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_0_CH0_TRAINING_E_WRPTR, 3, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_0_CH0_TRAINING_DRV_DQS, 4, DISABLED, ENABLED);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_ENABLED, 0, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_TRAIN_QPOP, 1, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_RX_E_DIRECT_ZI, 2, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_E_WRPTR, 3, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_DRV_DQS, 4, DISABLED, ENABLED);
|
||||
33
libraries/libvapours/include/vapours/tegra/tegra_evp.hpp
Normal file
33
libraries/libvapours/include/vapours/tegra/tegra_evp.hpp
Normal file
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define EVP_CPU_RESET_VECTOR (0x100)
|
||||
|
||||
#define EVP_COP_RESET_VECTOR (0x200)
|
||||
#define EVP_COP_UNDEF_VECTOR (0x204)
|
||||
#define EVP_COP_SWI_VECTOR (0x208)
|
||||
#define EVP_COP_PREFETCH_ABORT_VECTOR (0x20C)
|
||||
#define EVP_COP_DATA_ABORT_VECTOR (0x210)
|
||||
#define EVP_COP_RSVD_VECTOR (0x214)
|
||||
#define EVP_COP_IRQ_VECTOR (0x218)
|
||||
#define EVP_COP_FIQ_VECTOR (0x21C)
|
||||
@@ -0,0 +1,79 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define FLOW_CTLR_RAM_REPAIR (0x040)
|
||||
#define FLOW_CTLR_FLOW_DBG_QUAL (0x050)
|
||||
#define FLOW_CTLR_L2FLUSH_CONTROL (0x094)
|
||||
#define FLOW_CTLR_BPMP_CLUSTER_CONTROL (0x098)
|
||||
|
||||
#define FLOW_CTLR_CPU0_CSR (0x008)
|
||||
#define FLOW_CTLR_CPU1_CSR (0x018)
|
||||
#define FLOW_CTLR_CPU2_CSR (0x020)
|
||||
#define FLOW_CTLR_CPU3_CSR (0x028)
|
||||
|
||||
#define FLOW_CTLR_HALT_CPU0_EVENTS (0x000)
|
||||
#define FLOW_CTLR_HALT_CPU1_EVENTS (0x014)
|
||||
#define FLOW_CTLR_HALT_CPU2_EVENTS (0x01C)
|
||||
#define FLOW_CTLR_HALT_CPU3_EVENTS (0x024)
|
||||
#define FLOW_CTLR_HALT_COP_EVENTS (0x004)
|
||||
|
||||
#define FLOW_CTLR_CC4_CORE0_CTRL (0x06C)
|
||||
#define FLOW_CTLR_CC4_CORE1_CTRL (0x070)
|
||||
#define FLOW_CTLR_CC4_CORE2_CTRL (0x074)
|
||||
#define FLOW_CTLR_CC4_CORE3_CTRL (0x078)
|
||||
|
||||
#define FLOW_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (FLOW_CTLR, NAME)
|
||||
#define FLOW_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (FLOW_CTLR, NAME, VALUE)
|
||||
#define FLOW_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (FLOW_CTLR, NAME, ENUM)
|
||||
#define FLOW_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(FLOW_CTLR, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_FLOW_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (FLOW_CTLR, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_FLOW_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (FLOW_CTLR, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_FLOW_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (FLOW_CTLR, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_FLOW_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(FLOW_CTLR, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_FLOW_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (FLOW_CTLR, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_FLOW_REG_BIT_ENUM(CPUN_CSR_ENABLE, 0, DISABLE, ENABLE);
|
||||
DEFINE_FLOW_REG(CPUN_CSR_WAIT_WFI_BITMAP, 8, 4);
|
||||
DEFINE_FLOW_REG_TWO_BIT_ENUM(CPUN_CSR_ENABLE_EXT, 12, POWERGATE_CPU_ONLY, POWERGATE_BOTH_CPU_NONCPU, POWERGATE_CPU_TURNOFF_CPURAIL, PG_EMULATION);
|
||||
DEFINE_FLOW_REG_BIT_ENUM(CPUN_CSR_EVENT_FLAG, 14, FALSE, TRUE);
|
||||
DEFINE_FLOW_REG_BIT_ENUM(CPUN_CSR_INTR_FLAG, 15, FALSE, TRUE);
|
||||
|
||||
DEFINE_FLOW_REG_BIT_ENUM(HALT_CPUN_EVENTS_GIC_FIQN, 8, DISABLE, ENABLE);
|
||||
DEFINE_FLOW_REG_BIT_ENUM(HALT_CPUN_EVENTS_GIC_IRQN, 9, DISABLE, ENABLE);
|
||||
DEFINE_FLOW_REG_BIT_ENUM(HALT_CPUN_EVENTS_LIC_FIQN, 10, DISABLE, ENABLE);
|
||||
DEFINE_FLOW_REG_BIT_ENUM(HALT_CPUN_EVENTS_LIC_IRQN, 11, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_FLOW_REG_THREE_BIT_ENUM(HALT_CPUN_EVENTS_FLOW_MODE, 29, NONE, RUN_AND_INT, WAITEVENT, WAITEVENT_AND_INT, STOP_UNTIL_IRQ, STOP_UNTIL_EVENT_AND_IRQ, RESERVED6, RESERVED7);
|
||||
|
||||
DEFINE_FLOW_REG_BIT_ENUM(HALT_COP_EVENTS_JTAG, 28, DISABLED, ENABLED);
|
||||
DEFINE_FLOW_REG_THREE_BIT_ENUM(HALT_COP_EVENTS_MODE, 29, FLOW_MODE_NONE, FLOW_MODE_RUN_AND_INT, FLOW_MODE_STOP, FLOW_MODE_STOP_AND_INT, FLOW_MODE_STOP_UNTIL_IRQ, FLOW_MODE_STOP_UNTIL_IRQ_AND_INT, FLOW_MODE_STOP_UNTIL_EVENT_AND_IRQ, RESERVED7);
|
||||
|
||||
DEFINE_FLOW_REG_BIT_ENUM(FLOW_DBG_QUAL_FIQ2CCPLEX_ENABLE, 28, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_FLOW_REG_BIT_ENUM(RAM_REPAIR_REQ, 0, DISABLE, ENABLE);
|
||||
DEFINE_FLOW_REG_BIT_ENUM(RAM_REPAIR_STS, 1, REQUESTED, DONE);
|
||||
|
||||
DEFINE_FLOW_REG_BIT_ENUM(BPMP_CLUSTER_CONTROL_ACTIVE_CLUSTER, 0, FAST, SLOW);
|
||||
DEFINE_FLOW_REG_BIT_ENUM(BPMP_CLUSTER_CONTROL_CLUSTER_SWITCH_ENABLE, 1, DISABLE, ENABLE);
|
||||
DEFINE_FLOW_REG_BIT_ENUM(BPMP_CLUSTER_CONTROL_ACTIVE_CLUSTER_LOCK, 2, DISABLE, ENABLE);
|
||||
32
libraries/libvapours/include/vapours/tegra/tegra_ictlr.hpp
Normal file
32
libraries/libvapours/include/vapours/tegra/tegra_ictlr.hpp
Normal file
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define PRI_ICTLR(n) (0x60004000 + n)
|
||||
#define SEC_ICTLR(n) (0x60004100 + n)
|
||||
#define TRI_ICTLR(n) (0x60004200 + n)
|
||||
#define QUAD_ICTLR(n) (0x60004300 + n)
|
||||
#define PENTA_ICTLR(n) (0x60004400 + n)
|
||||
#define HEXA_ICTLR(n) (0x60004500 + n)
|
||||
|
||||
#define ICTLR_COP_IER_CLR (0x038)
|
||||
|
||||
555
libraries/libvapours/include/vapours/tegra/tegra_mc.hpp
Normal file
555
libraries/libvapours/include/vapours/tegra/tegra_mc.hpp
Normal file
@@ -0,0 +1,555 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define MC_INTSTATUS (0x000)
|
||||
#define MC_INTMASK (0x004)
|
||||
#define MC_ERR_STATUS (0x008)
|
||||
#define MC_ERR_ADR (0x00C)
|
||||
#define MC_SMMU_CONFIG (0x010)
|
||||
#define MC_SMMU_PTB_ASID (0x01C)
|
||||
#define MC_SMMU_PTB_DATA (0x020)
|
||||
#define MC_SMMU_TLB_FLUSH (0x030)
|
||||
#define MC_SMMU_PTC_FLUSH (0x034)
|
||||
#define MC_EMEM_CFG (0x050)
|
||||
#define MC_EMEM_ADR_CFG (0x054)
|
||||
#define MC_EMEM_ARB_CFG (0x090)
|
||||
#define MC_EMEM_ARB_OUTSTANDING_REQ (0x094)
|
||||
#define MC_EMEM_ARB_TIMING_RCD (0x098)
|
||||
#define MC_EMEM_ARB_TIMING_RP (0x09C)
|
||||
#define MC_EMEM_ARB_TIMING_RC (0x0A0)
|
||||
#define MC_EMEM_ARB_TIMING_RAS (0x0A4)
|
||||
#define MC_EMEM_ARB_TIMING_FAW (0x0A8)
|
||||
#define MC_EMEM_ARB_TIMING_RRD (0x0AC)
|
||||
#define MC_EMEM_ARB_TIMING_RAP2PRE (0x0B0)
|
||||
#define MC_EMEM_ARB_TIMING_WAP2PRE (0x0B4)
|
||||
#define MC_EMEM_ARB_TIMING_R2R (0x0B8)
|
||||
#define MC_EMEM_ARB_TIMING_W2W (0x0BC)
|
||||
#define MC_EMEM_ARB_TIMING_R2W (0x0C0)
|
||||
#define MC_EMEM_ARB_TIMING_W2R (0x0C4)
|
||||
#define MC_EMEM_ARB_MISC2 (0x0C8)
|
||||
#define MC_EMEM_ARB_DA_TURNS (0x0D0)
|
||||
#define MC_EMEM_ARB_DA_COVERS (0x0D4)
|
||||
#define MC_EMEM_ARB_MISC0 (0x0D8)
|
||||
#define MC_EMEM_ARB_MISC1 (0x0DC)
|
||||
#define MC_EMEM_ARB_RING1_THROTTLE (0x0E0)
|
||||
#define MC_CLIENT_HOTRESET_CTRL (0x200)
|
||||
#define MC_CLIENT_HOTRESET_STATUS (0x204)
|
||||
#define MC_SMMU_AFI_ASID (0x238)
|
||||
#define MC_SMMU_DC_ASID (0x240)
|
||||
#define MC_SMMU_DCB_ASID (0x244)
|
||||
#define MC_SMMU_HC_ASID (0x250)
|
||||
#define MC_SMMU_HDA_ASID (0x254)
|
||||
#define MC_SMMU_ISP2_ASID (0x258)
|
||||
#define MC_SMMU_NVENC_ASID (0x264)
|
||||
#define MC_SMMU_NV_ASID (0x268)
|
||||
#define MC_SMMU_NV2_ASID (0x26C)
|
||||
#define MC_SMMU_PPCS_ASID (0x270)
|
||||
#define MC_SMMU_SATA_ASID (0x274)
|
||||
#define MC_SMMU_VI_ASID (0x280)
|
||||
#define MC_SMMU_VIC_ASID (0x284)
|
||||
#define MC_SMMU_XUSB_HOST_ASID (0x288)
|
||||
#define MC_SMMU_XUSB_DEV_ASID (0x28C)
|
||||
#define MC_SMMU_TSEC_ASID (0x294)
|
||||
#define MC_LATENCY_ALLOWANCE_AVPC_0 (0x2E4)
|
||||
#define MC_LATENCY_ALLOWANCE_DC_0 (0x2E8)
|
||||
#define MC_LATENCY_ALLOWANCE_DC_1 (0x2EC)
|
||||
#define MC_LATENCY_ALLOWANCE_DCB_0 (0x2F4)
|
||||
#define MC_LATENCY_ALLOWANCE_DCB_1 (0x2F8)
|
||||
#define MC_LATENCY_ALLOWANCE_HC_0 (0x310)
|
||||
#define MC_LATENCY_ALLOWANCE_HC_1 (0x314)
|
||||
#define MC_LATENCY_ALLOWANCE_MPCORE_0 (0x320)
|
||||
#define MC_LATENCY_ALLOWANCE_NVENC_0 (0x328)
|
||||
#define MC_LATENCY_ALLOWANCE_PPCS_0 (0x344)
|
||||
#define MC_LATENCY_ALLOWANCE_PPCS_1 (0x348)
|
||||
#define MC_LATENCY_ALLOWANCE_ISP2_0 (0x370)
|
||||
#define MC_LATENCY_ALLOWANCE_ISP2_1 (0x374)
|
||||
#define MC_LATENCY_ALLOWANCE_XUSB_0 (0x37C)
|
||||
#define MC_LATENCY_ALLOWANCE_XUSB_1 (0x380)
|
||||
#define MC_LATENCY_ALLOWANCE_TSEC_0 (0x390)
|
||||
#define MC_LATENCY_ALLOWANCE_VIC_0 (0x394)
|
||||
#define MC_LATENCY_ALLOWANCE_VI2_0 (0x398)
|
||||
#define MC_LATENCY_ALLOWANCE_GPU_0 (0x3AC)
|
||||
#define MC_LATENCY_ALLOWANCE_SDMMCA_0 (0x3B8)
|
||||
#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 (0x3BC)
|
||||
#define MC_LATENCY_ALLOWANCE_SDMMC_0 (0x3C0)
|
||||
#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 (0x3C4)
|
||||
#define MC_LATENCY_ALLOWANCE_NVDEC_0 (0x3D8)
|
||||
#define MC_LATENCY_ALLOWANCE_GPU2_0 (0x3E8)
|
||||
#define MC_DIS_PTSA_RATE (0x41C)
|
||||
#define MC_DIS_PTSA_MIN (0x420)
|
||||
#define MC_DIS_PTSA_MAX (0x424)
|
||||
#define MC_DISB_PTSA_RATE (0x428)
|
||||
#define MC_DISB_PTSA_MIN (0x42C)
|
||||
#define MC_DISB_PTSA_MAX (0x430)
|
||||
#define MC_VE_PTSA_RATE (0x434)
|
||||
#define MC_VE_PTSA_MIN (0x438)
|
||||
#define MC_VE_PTSA_MAX (0x43C)
|
||||
#define MC_MLL_MPCORER_PTSA_RATE (0x44C)
|
||||
#define MC_RING1_PTSA_RATE (0x47C)
|
||||
#define MC_RING1_PTSA_MIN (0x480)
|
||||
#define MC_RING1_PTSA_MAX (0x484)
|
||||
#define MC_PCX_PTSA_RATE (0x4AC)
|
||||
#define MC_PCX_PTSA_MIN (0x4B0)
|
||||
#define MC_PCX_PTSA_MAX (0x4B4)
|
||||
#define MC_MSE_PTSA_RATE (0x4C4)
|
||||
#define MC_MSE_PTSA_MIN (0x4C8)
|
||||
#define MC_MSE_PTSA_MAX (0x4CC)
|
||||
#define MC_AHB_PTSA_RATE (0x4DC)
|
||||
#define MC_AHB_PTSA_MIN (0x4E0)
|
||||
#define MC_AHB_PTSA_MAX (0x4E4)
|
||||
#define MC_APB_PTSA_RATE (0x4E8)
|
||||
#define MC_APB_PTSA_MIN (0x4EC)
|
||||
#define MC_APB_PTSA_MAX (0x4F0)
|
||||
#define MC_FTOP_PTSA_RATE (0x50C)
|
||||
#define MC_HOST_PTSA_RATE (0x518)
|
||||
#define MC_HOST_PTSA_MIN (0x51C)
|
||||
#define MC_HOST_PTSA_MAX (0x520)
|
||||
#define MC_USBX_PTSA_RATE (0x524)
|
||||
#define MC_USBX_PTSA_MIN (0x528)
|
||||
#define MC_USBX_PTSA_MAX (0x52C)
|
||||
#define MC_USBD_PTSA_RATE (0x530)
|
||||
#define MC_USBD_PTSA_MIN (0x534)
|
||||
#define MC_USBD_PTSA_MAX (0x538)
|
||||
#define MC_GK_PTSA_RATE (0x53C)
|
||||
#define MC_GK_PTSA_MIN (0x540)
|
||||
#define MC_GK_PTSA_MAX (0x544)
|
||||
#define MC_AUD_PTSA_RATE (0x548)
|
||||
#define MC_AUD_PTSA_MIN (0x54C)
|
||||
#define MC_AUD_PTSA_MAX (0x550)
|
||||
#define MC_VICPC_PTSA_RATE (0x554)
|
||||
#define MC_VICPC_PTSA_MIN (0x558)
|
||||
#define MC_VICPC_PTSA_MAX (0x55C)
|
||||
#define MC_JPG_PTSA_RATE (0x584)
|
||||
#define MC_JPG_PTSA_MIN (0x588)
|
||||
#define MC_JPG_PTSA_MAX (0x58C)
|
||||
#define MC_GK2_PTSA_RATE (0x610)
|
||||
#define MC_GK2_PTSA_MIN (0x614)
|
||||
#define MC_GK2_PTSA_MAX (0x618)
|
||||
#define MC_SDM_PTSA_RATE (0x61C)
|
||||
#define MC_SDM_PTSA_MIN (0x620)
|
||||
#define MC_SDM_PTSA_MAX (0x624)
|
||||
#define MC_HDAPC_PTSA_RATE (0x628)
|
||||
#define MC_HDAPC_PTSA_MIN (0x62C)
|
||||
#define MC_HDAPC_PTSA_MAX (0x630)
|
||||
#define MC_SEC_CARVEOUT_BOM (0x670)
|
||||
#define MC_SEC_CARVEOUT_SIZE_MB (0x674)
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A (0x690)
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB (0x694)
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B (0x698)
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB (0x69C)
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C (0x6A0)
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB (0x6A4)
|
||||
#define MC_EMEM_ARB_TIMING_RFCPB (0x6C0)
|
||||
#define MC_EMEM_ARB_TIMING_CCDMW (0x6C4)
|
||||
#define MC_EMEM_ARB_REFPB_HP_CTRL (0x6F0)
|
||||
#define MC_EMEM_ARB_REFPB_BANK_CTRL (0x6F4)
|
||||
#define MC_PTSA_GRANT_DECREMENT (0x960)
|
||||
#define MC_CLIENT_HOTRESET_CTRL_1 (0x970)
|
||||
#define MC_CLIENT_HOTRESET_STATUS_1 (0x974)
|
||||
#define MC_SMMU_PTC_FLUSH_1 (0x9B8)
|
||||
#define MC_SMMU_DC1_ASID (0xA88)
|
||||
#define MC_SMMU_SDMMC1A_ASID (0xA94)
|
||||
#define MC_SMMU_SDMMC2A_ASID (0xA98)
|
||||
#define MC_SMMU_SDMMC3A_ASID (0xA9C)
|
||||
#define MC_SMMU_SDMMC4A_ASID (0xAA0)
|
||||
#define MC_SMMU_ISP2B_ASID (0xAA4)
|
||||
#define MC_SMMU_GPU_ASID (0xAA8)
|
||||
#define MC_SMMU_GPUB_ASID (0xAAC)
|
||||
#define MC_SMMU_PPCS2_ASID (0xAB0)
|
||||
#define MC_SMMU_NVDEC_ASID (0xAB4)
|
||||
#define MC_SMMU_APE_ASID (0xAB8)
|
||||
#define MC_SMMU_SE_ASID (0xABC)
|
||||
#define MC_SMMU_NVJPG_ASID (0xAC0)
|
||||
#define MC_SMMU_HC1_ASID (0xAC4)
|
||||
#define MC_SMMU_SE1_ASID (0xAC8)
|
||||
#define MC_SMMU_AXIAP_ASID (0xACC)
|
||||
#define MC_SMMU_ETR_ASID (0xAD0)
|
||||
#define MC_SMMU_TSECB_ASID (0xAD4)
|
||||
#define MC_SMMU_TSEC1_ASID (0xAD8)
|
||||
#define MC_SMMU_TSECB1_ASID (0xADC)
|
||||
#define MC_SMMU_NVDEC1_ASID (0xAE0)
|
||||
#define MC_EMEM_ARB_DHYST_CTRL (0xBCC)
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 (0xBD0)
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 (0xBD4)
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 (0xBD8)
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 (0xBDC)
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 (0xBE0)
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 (0xBE4)
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 (0xBE8)
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 (0xBEC)
|
||||
#define MC_ERR_GENERALIZED_CARVEOUT_STATUS (0xC00)
|
||||
|
||||
#define MC_SMMU_TLB_CONFIG (0x014)
|
||||
#define MC_SMMU_PTC_CONFIG (0x018)
|
||||
|
||||
#define MC_SMMU_AVPC_ASID (0x23C)
|
||||
#define MC_SMMU_PPCS1_ASID (0x298)
|
||||
|
||||
#define MC_SECURITY_CFG0 (0x070)
|
||||
#define MC_SECURITY_CFG1 (0x074)
|
||||
#define MC_SECURITY_CFG3 (0x9BC)
|
||||
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_0 (0x228)
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_1 (0x22C)
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_2 (0x230)
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_3 (0x234)
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_4 (0xB98)
|
||||
|
||||
#define MC_SMMU_ASID_SECURITY (0x038)
|
||||
#define MC_SMMU_ASID_SECURITY_1 (0x03c)
|
||||
#define MC_SMMU_ASID_SECURITY_2 (0x9e0)
|
||||
#define MC_SMMU_ASID_SECURITY_3 (0x9e4)
|
||||
#define MC_SMMU_ASID_SECURITY_4 (0x9e8)
|
||||
#define MC_SMMU_ASID_SECURITY_5 (0x9ec)
|
||||
#define MC_SMMU_ASID_SECURITY_6 (0x9f0)
|
||||
#define MC_SMMU_ASID_SECURITY_7 (0x9f4)
|
||||
|
||||
#define MC_IRAM_BOM (0x65c)
|
||||
#define MC_IRAM_TOM (0x660)
|
||||
#define MC_IRAM_REG_CTRL (0x964)
|
||||
|
||||
#define MC_SEC_CARVEOUT_BOM (0x670)
|
||||
#define MC_SEC_CARVEOUT_SIZE_MB (0x674)
|
||||
#define MC_SEC_CARVEOUT_REG_CTRL (0x678)
|
||||
|
||||
#define MC_VIDEO_PROTECT_BOM (0x648)
|
||||
#define MC_VIDEO_PROTECT_SIZE_MB (0x64c)
|
||||
#define MC_VIDEO_PROTECT_REG_CTRL (0x650)
|
||||
#define MC_VIDEO_PROTECT_GPU_OVERRIDE_0 (0x984)
|
||||
#define MC_VIDEO_PROTECT_GPU_OVERRIDE_1 (0x988)
|
||||
|
||||
#define MC_MTS_CARVEOUT_BOM (0x9a0)
|
||||
#define MC_MTS_CARVEOUT_SIZE_MB (0x9a4)
|
||||
#define MC_MTS_CARVEOUT_ADR_HI (0x9a8)
|
||||
#define MC_MTS_CARVEOUT_REG_CTRL (0x9ac)
|
||||
|
||||
#define MC_SECURITY_CARVEOUT1_CFG0 (0xc08)
|
||||
#define MC_SECURITY_CARVEOUT1_BOM (0xc0c)
|
||||
#define MC_SECURITY_CARVEOUT1_BOM_HI (0xc10)
|
||||
#define MC_SECURITY_CARVEOUT1_SIZE_128KB (0xc14)
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0 (0xc18)
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1 (0xc1c)
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2 (0xc20)
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3 (0xc24)
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4 (0xc28)
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0 (0xc2c)
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1 (0xc30)
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2 (0xc34)
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3 (0xc38)
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4 (0xc3c)
|
||||
|
||||
#define MC_SECURITY_CARVEOUT2_CFG0 (0xc58)
|
||||
#define MC_SECURITY_CARVEOUT2_BOM (0xc5c)
|
||||
#define MC_SECURITY_CARVEOUT2_BOM_HI (0xc60)
|
||||
#define MC_SECURITY_CARVEOUT2_SIZE_128KB (0xc64)
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0 (0xc68)
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1 (0xc6c)
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2 (0xc70)
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3 (0xc74)
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4 (0xc78)
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0 (0xc7c)
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1 (0xc80)
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2 (0xc84)
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3 (0xc88)
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4 (0xc8c)
|
||||
|
||||
#define MC_SECURITY_CARVEOUT3_CFG0 (0xca8)
|
||||
#define MC_SECURITY_CARVEOUT3_BOM (0xcac)
|
||||
#define MC_SECURITY_CARVEOUT3_BOM_HI (0xcb0)
|
||||
#define MC_SECURITY_CARVEOUT3_SIZE_128KB (0xcb4)
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0 (0xcb8)
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1 (0xcbc)
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2 (0xcc0)
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3 (0xcc4)
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4 (0xcc8)
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0 (0xccc)
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1 (0xcd0)
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2 (0xcd4)
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3 (0xcd8)
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4 (0xcdc)
|
||||
|
||||
#define MC_SECURITY_CARVEOUT4_CFG0 (0xcf8)
|
||||
#define MC_SECURITY_CARVEOUT4_BOM (0xcfc)
|
||||
#define MC_SECURITY_CARVEOUT4_BOM_HI (0xd00)
|
||||
#define MC_SECURITY_CARVEOUT4_SIZE_128KB (0xd04)
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 (0xd08)
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1 (0xd0c)
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2 (0xd10)
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3 (0xd14)
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4 (0xd18)
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0 (0xd1c)
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1 (0xd20)
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2 (0xd24)
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3 (0xd28)
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4 (0xd2c)
|
||||
|
||||
#define MC_SECURITY_CARVEOUT5_CFG0 (0xd48)
|
||||
#define MC_SECURITY_CARVEOUT5_BOM (0xd4c)
|
||||
#define MC_SECURITY_CARVEOUT5_BOM_HI (0xd50)
|
||||
#define MC_SECURITY_CARVEOUT5_SIZE_128KB (0xd54)
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0 (0xd58)
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1 (0xd5c)
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2 (0xd60)
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3 (0xd64)
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4 (0xd68)
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0 (0xd6c)
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1 (0xd70)
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2 (0xd74)
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3 (0xd78)
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4 (0xd7c)
|
||||
|
||||
#define MC_STAT_CONTROL (0x100)
|
||||
#define MC_STAT_EMC_CLOCK_LIMIT (0x108)
|
||||
#define MC_STAT_EMC_CLOCK_LIMIT_MSBS (0x10c)
|
||||
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_LO (0x118)
|
||||
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_HI (0x11c)
|
||||
#define MC_STAT_EMC_FILTER_SET0_SPARE (0x124)
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_0 (0x128)
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_1 (0x12c)
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_2 (0x130)
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_3 (0x134)
|
||||
#define MC_STAT_EMC_SET0_COUNT (0x138)
|
||||
#define MC_STAT_EMC_SET0_COUNT_MSBS (0x13c)
|
||||
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_LO (0x158)
|
||||
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_HI (0x15c)
|
||||
#define MC_STAT_EMC_FILTER_SET1_SPARE (0x164)
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_0 (0x168)
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_1 (0x16c)
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_2 (0x170)
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_3 (0x174)
|
||||
#define MC_STAT_EMC_SET1_COUNT (0x178)
|
||||
#define MC_STAT_EMC_SET1_COUNT_MSBS (0x17c)
|
||||
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_UPPER (0xa20)
|
||||
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_UPPER (0xa24)
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_4 (0xb88)
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_4 (0xb8c)
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_5 (0xbc4)
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_5 (0xbc8)
|
||||
|
||||
#define MC_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (MC, NAME)
|
||||
#define MC_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (MC, NAME, VALUE)
|
||||
#define MC_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (MC, NAME, ENUM)
|
||||
#define MC_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(MC, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_MC_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (MC, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_MC_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (MC, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_MC_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (MC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_MC_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(MC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_MC_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (MC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_CONFIG_SMMU_ENABLE, 0, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_MC_REG(SMMU_TLB_CONFIG_TLB_ACTIVE_LINES, 0, 6);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_TLB_CONFIG_TLB_ROUND_ROBIN_ARBITRATION, 28, DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_TLB_CONFIG_TLB_HIT_UNDER_MISS, 29, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_MC_REG(SMMU_PTC_CONFIG_PTC_INDEX_MAP, 0, 7);
|
||||
DEFINE_MC_REG(SMMU_PTC_CONFIG_PTC_REQ_LIMIT, 24, 4);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_PTC_CONFIG_PTC_CACHE_ENABLE, 29, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_MC_REG(SMMU_PTB_ASID_CURRENT_ASID, 0, 7);
|
||||
|
||||
DEFINE_MC_REG(SMMU_PTB_DATA_ASID_PDE_BASE, 0, 22);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_PTB_DATA_ASID_NONSECURE, 29, DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_PTB_DATA_ASID_WRITABLE, 30, DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_PTB_DATA_ASID_READABLE, 31, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_MC_REG(SMMU_AVPC_ASID_AVPC_ASID, 0, 7);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_AVPC_ASID_AVPC_SMMU_ENABLE, 31, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_MC_REG(SMMU_PPCS1_ASID_PPCS1_ASID, 0, 7);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_PPCS1_ASID_PPCS1_SMMU_ENABLE, 31, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_0, 0, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_1, 1, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_2, 2, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_3, 3, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_4, 4, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_5, 5, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_6, 6, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_7, 7, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_8, 8, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_9, 9, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_10, 10, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_11, 11, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_12, 12, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_13, 13, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_14, 14, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_15, 15, NONSECURE, SECURE);
|
||||
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_0, 16, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_1, 17, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_2, 18, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_3, 19, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_4, 20, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_5, 21, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_6, 22, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_7, 23, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_8, 24, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_9, 25, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_10, 26, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_11, 27, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_12, 28, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_13, 29, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_14, 30, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_15, 31, NONPROMOTING, PROMOTING);
|
||||
|
||||
DEFINE_MC_REG(SECURITY_CFG0_SECURITY_BOM, 20, 12);
|
||||
DEFINE_MC_REG(SECURITY_CFG1_SECURITY_SIZE, 0, 13);
|
||||
DEFINE_MC_REG(SECURITY_CFG3_SECURITY_BOM_HI, 0, 2);
|
||||
|
||||
DEFINE_MC_REG_BIT_ENUM(SEC_CARVEOUT_REG_CTRL_SEC_CARVEOUT_WRITE_ACCESS, 0, ENABLED, DISABLED);
|
||||
|
||||
DEFINE_MC_REG_BIT_ENUM(VIDEO_PROTECT_REG_CTRL_VIDEO_PROTECT_WRITE_ACCESS, 0, ENABLED, DISABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(VIDEO_PROTECT_REG_CTRL_VIDEO_PROTECT_ALLOW_TZ_WRITE, 1, DISABLED, ENABLED);
|
||||
|
||||
DEFINE_MC_REG_BIT_ENUM(MTS_CARVEOUT_REG_CTRL_MTS_CARVEOUT_WRITE_ACCESS, 0, ENABLED, DISABLED);
|
||||
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_PROTECT_MODE, 0, LOCKBIT_SECURE, TZ_SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_LOCK_MODE, 1, UNLOCKED, LOCKED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_ADDRESS_TYPE, 2, ANY_ADDRESS, UNTRANSLATED_ONLY);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_READ_ACCESS_LEVEL0, 3, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_READ_ACCESS_LEVEL1, 4, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_READ_ACCESS_LEVEL2, 5, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_READ_ACCESS_LEVEL3, 6, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_WRITE_ACCESS_LEVEL0, 7, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_WRITE_ACCESS_LEVEL1, 8, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_WRITE_ACCESS_LEVEL2, 9, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_WRITE_ACCESS_LEVEL3, 10, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG(SECURITY_CARVEOUT_CFG0_APERTURE_ID, 11, 3);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_READ_CHECK_ACCESS_LEVEL0, 14, ENABLE_CHECKS, DISABLE_CHECKS);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_READ_CHECK_ACCESS_LEVEL1, 15, ENABLE_CHECKS, DISABLE_CHECKS);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_READ_CHECK_ACCESS_LEVEL2, 16, ENABLE_CHECKS, DISABLE_CHECKS);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_READ_CHECK_ACCESS_LEVEL3, 17, ENABLE_CHECKS, DISABLE_CHECKS);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_WRITE_CHECK_ACCESS_LEVEL0, 18, ENABLE_CHECKS, DISABLE_CHECKS);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_WRITE_CHECK_ACCESS_LEVEL1, 19, ENABLE_CHECKS, DISABLE_CHECKS);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_WRITE_CHECK_ACCESS_LEVEL2, 20, ENABLE_CHECKS, DISABLE_CHECKS);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_WRITE_CHECK_ACCESS_LEVEL3, 21, ENABLE_CHECKS, DISABLE_CHECKS);
|
||||
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_SEND_CFG_TO_GPU, 22, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_TZ_GLOBAL_WR_EN, 23, DISABLED, BYPASS_CHECK);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_TZ_GLOBAL_RD_EN, 24, DISABLED, BYPASS_CHECK);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_ALLOW_APERTURE_ID_MISMATCH, 25, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_FORCE_APERTURE_ID_MATCH, 26, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_IS_WPR, 27, DISABLED, ENABLED);
|
||||
|
||||
#define MC_CLIENT_ACCESS_NUM_CLIENTS 32
|
||||
|
||||
/* _ACCESS0 */
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_PTCR, ( 0 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAY0A, ( 1 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAY0AB, ( 2 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAY0B, ( 3 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAY0BB, ( 4 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAY0C, ( 5 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAY0CB, ( 6 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_AFIR, ( 14 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_AVPCARM7R, ( 15 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAYHC, ( 16 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAYHCB, ( 17 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_HDAR, ( 21 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_HOST1XDMAR, ( 22 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_HOST1XR, ( 23 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_NVENCSRD, ( 28 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_PPCSAHBDMAR, ( 29 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_PPCSAHBSLVR, ( 30 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_SATAR, ( 31 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
|
||||
/* _ACCESS1 */
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_VDEBSEVR, ( 34 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_VDEMBER, ( 35 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_VDEMCER, ( 36 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_VDETPER, ( 37 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_MPCORELPR, ( 38 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_MPCORER, ( 39 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_NVENCSWR, ( 43 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_AFIW, ( 49 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_AVPCARM7W, ( 50 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_HDAW, ( 53 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_HOST1XW, ( 54 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_MPCORELPW, ( 56 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_MPCOREW, ( 57 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_PPCSAHBDMAW, ( 59 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_PPCSAHBSLVW, ( 60 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_SATAW, ( 61 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_VDEBSEVW, ( 62 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_VDEDBGW, ( 63 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
|
||||
/* _ACCESS2 */
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_VDEMBEW, ( 64 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_VDETPMW, ( 65 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_ISPRA, ( 68 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_ISPWA, ( 70 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_ISPWB, ( 71 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_XUSB_HOSTR, ( 74 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_XUSB_HOSTW, ( 75 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_XUSB_DEVR, ( 76 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_XUSB_DEVW, ( 77 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_ISPRAB, ( 78 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_ISPWAB, ( 80 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_ISPWBB, ( 81 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_TSECSRD, ( 84 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_TSECSWR, ( 85 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_A9AVPSCR, ( 86 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_A9AVPSCW, ( 87 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_GPUSRD, ( 88 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_GPUSWR, ( 89 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_DISPLAYT, ( 90 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
|
||||
/* _ACCESS3 */
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCRA, ( 96 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCRAA, ( 97 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCR, ( 98 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCRAB, ( 99 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCWA, (100 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCWAA, (101 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCW, (102 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCWAB, (103 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_VICSRD, (108 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_VICSWR, (109 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_VIW, (114 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_DISPLAYD, (115 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_NVDECSRD, (120 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_NVDECSWR, (121 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_APER, (122 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_APEW, (123 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_NVJPGSRD, (126 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_NVJPGSWR, (127 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
|
||||
/* _ACCESS4 */
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_SESRD, (128 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_SESWR, (129 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_AXIAPR, (130 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_AXIAPW, (131 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_ETRR, (132 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_ETRW, (133 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_TSECRDB, (134 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_TSECWRB, (135 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_GPUSRD2, (136 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_GPUSWR2, (137 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
|
||||
|
||||
DEFINE_MC_REG(IRAM_BOM_IRAM_BOM, 12, BITSIZEOF(u32) - 12);
|
||||
DEFINE_MC_REG(IRAM_TOM_IRAM_TOM, 12, BITSIZEOF(u32) - 12);
|
||||
|
||||
DEFINE_MC_REG_BIT_ENUM(IRAM_REG_CTRL_IRAM_CFG_WRITE_ACCESS, 0, ENABLED, DISABLED);
|
||||
|
||||
44
libraries/libvapours/include/vapours/tegra/tegra_mselect.hpp
Normal file
44
libraries/libvapours/include/vapours/tegra/tegra_mselect.hpp
Normal file
@@ -0,0 +1,44 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define MSELECT(x) (0x50060000 + x)
|
||||
|
||||
#define MSELECT_CONFIG (0x000)
|
||||
|
||||
#define MSELECT_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (MSELECT, NAME)
|
||||
#define MSELECT_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (MSELECT, NAME, VALUE)
|
||||
#define MSELECT_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (MSELECT, NAME, ENUM)
|
||||
#define MSELECT_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(MSELECT, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_MSELECT_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (MSELECT, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_MSELECT_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (MSELECT, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_MSELECT_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (MSELECT, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_MSELECT_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(MSELECT, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_MSELECT_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (MSELECT, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_MSELECT_REG_BIT_ENUM(CONFIG_ERR_RESP_EN_SLAVE1, 24, DISABLE, ENABLE);
|
||||
DEFINE_MSELECT_REG_BIT_ENUM(CONFIG_ERR_RESP_EN_SLAVE2, 25, DISABLE, ENABLE);
|
||||
DEFINE_MSELECT_REG_BIT_ENUM(CONFIG_WRAP_TO_INCR_SLAVE0, 27, DISABLE, ENABLE);
|
||||
DEFINE_MSELECT_REG_BIT_ENUM(CONFIG_WRAP_TO_INCR_SLAVE1, 28, DISABLE, ENABLE);
|
||||
DEFINE_MSELECT_REG_BIT_ENUM(CONFIG_WRAP_TO_INCR_SLAVE2, 29, DISABLE, ENABLE);
|
||||
DEFINE_MSELECT_REG_BIT_ENUM(CONFIG_WRAP_TO_INCR_SLAVE3, 30, DISABLE, ENABLE);
|
||||
28
libraries/libvapours/include/vapours/tegra/tegra_pg_up.hpp
Normal file
28
libraries/libvapours/include/vapours/tegra/tegra_pg_up.hpp
Normal file
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define PG_UP(x) (0x60000000 + x)
|
||||
|
||||
#define PG_UP_TAG (0x000)
|
||||
|
||||
#define PG_UP_TAG_PID_COP 0xAAAAAAAA
|
||||
73
libraries/libvapours/include/vapours/tegra/tegra_pinmux.hpp
Normal file
73
libraries/libvapours/include/vapours/tegra/tegra_pinmux.hpp
Normal file
@@ -0,0 +1,73 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define PINMUX_AUX_GEN1_I2C_SCL (0x30BC)
|
||||
#define PINMUX_AUX_GEN1_I2C_SDA (0x30C0)
|
||||
#define PINMUX_AUX_PWR_I2C_SCL (0x30DC)
|
||||
#define PINMUX_AUX_PWR_I2C_SDA (0x30E0)
|
||||
|
||||
#define PINMUX_AUX_UART1_TX (0x30E4)
|
||||
#define PINMUX_AUX_UART1_RX (0x30E8)
|
||||
#define PINMUX_AUX_UART1_RTS (0x30EC)
|
||||
#define PINMUX_AUX_UART1_CTS (0x30F0)
|
||||
#define PINMUX_AUX_UART2_TX (0x30F4)
|
||||
#define PINMUX_AUX_UART2_RX (0x30F8)
|
||||
#define PINMUX_AUX_UART2_RTS (0x30FC)
|
||||
#define PINMUX_AUX_UART2_CTS (0x3100)
|
||||
#define PINMUX_AUX_UART3_TX (0x3104)
|
||||
#define PINMUX_AUX_UART3_RX (0x3108)
|
||||
#define PINMUX_AUX_UART3_RTS (0x310C)
|
||||
#define PINMUX_AUX_UART3_CTS (0x3110)
|
||||
#define PINMUX_AUX_DVFS_PWM (0x3184)
|
||||
#define PINMUX_AUX_GPIO_PA6 (0x3244)
|
||||
|
||||
#define PINMUX_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (PINMUX, NAME)
|
||||
#define PINMUX_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (PINMUX, NAME, VALUE)
|
||||
#define PINMUX_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (PINMUX, NAME, ENUM)
|
||||
#define PINMUX_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(PINMUX, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_PINMUX_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (PINMUX, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_PINMUX_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (PINMUX, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_PINMUX_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (PINMUX, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_PINMUX_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(PINMUX, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_PINMUX_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (PINMUX, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_PUPD, 2, NONE, PULL_DOWN, PULL_UP, RSVD);
|
||||
DEFINE_PINMUX_REG_BIT_ENUM(AUX_TRISTATE, 4, PASSTHROUGH, TRISTATE);
|
||||
DEFINE_PINMUX_REG_BIT_ENUM(AUX_PARK, 5, NORMAL, PARKED);
|
||||
DEFINE_PINMUX_REG_BIT_ENUM(AUX_E_INPUT, 6, DISABLE, ENABLE);
|
||||
DEFINE_PINMUX_REG_BIT_ENUM(AUX_LOCK, 7, DISABLE, ENABLE);
|
||||
DEFINE_PINMUX_REG_BIT_ENUM(AUX_E_LPDR, 8, DISABLE, ENABLE);
|
||||
DEFINE_PINMUX_REG_BIT_ENUM(AUX_E_OD, 11, DISABLE, ENABLE);
|
||||
DEFINE_PINMUX_REG_BIT_ENUM(AUX_E_SCHMT, 12, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_GEN1_I2C_PM, 0, I2C1, RSVD1, RSVD2, RSVD3);
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_PWR_I2C_PM, 0, I2CPMU, RSVD1, RSVD2, RSVD3);
|
||||
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_UART1_PM, 0, UARTA, RSVD1, RSVD2, RSVD3);
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_UART2_PM, 0, UARTB, I2S4A, RSVD2, UART);
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_UART3_PM, 0, UARTC, SPI4, RSVD2, RSVD3);
|
||||
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_DVFS_PWM_PM, 0, RSVD0, CLDVFS, SPI3, RSVD3);
|
||||
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_GPIO_PA6_PM, 0, SATA, RSVD1, RSVD2, RSVD3);
|
||||
240
libraries/libvapours/include/vapours/tegra/tegra_pmc.hpp
Normal file
240
libraries/libvapours/include/vapours/tegra/tegra_pmc.hpp
Normal file
@@ -0,0 +1,240 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define APBDEV_PMC_CNTRL (0x000)
|
||||
#define APBDEV_PMC_WAKE_MASK (0x00C)
|
||||
#define APBDEV_PMC_WAKE_LVL (0x010)
|
||||
#define APBDEV_PMC_WAKE_STATUS (0x014)
|
||||
#define APBDEV_PMC_DPD_PADS_ORIDE (0x01C)
|
||||
#define APBDEV_PMC_DPD_SAMPLE (0x020)
|
||||
#define APBDEV_PMC_DPD_ENABLE (0x024)
|
||||
#define APBDEV_PMC_CLAMP_STATUS (0x02C)
|
||||
#define APBDEV_PMC_PWRGATE_TOGGLE (0x030)
|
||||
#define APBDEV_PMC_REMOVE_CLAMPING_CMD (0x034)
|
||||
#define APBDEV_PMC_PWRGATE_STATUS (0x038)
|
||||
#define APBDEV_PMC_PWRGOOD_TIMER (0x03C)
|
||||
#define APBDEV_PMC_BLINK_TIMER (0x040)
|
||||
#define APBDEV_PMC_NO_IOPOWER (0x044)
|
||||
#define APBDEV_PMC_PWR_DET (0x048)
|
||||
#define APBDEV_PMC_SCRATCH0 (0x050)
|
||||
#define APBDEV_PMC_SCRATCH1 (0x054)
|
||||
#define APBDEV_PMC_SCRATCH12 (0x080)
|
||||
#define APBDEV_PMC_SCRATCH13 (0x084)
|
||||
#define APBDEV_PMC_SCRATCH18 (0x098)
|
||||
#define APBDEV_PMC_SCRATCH20 (0x0A0)
|
||||
#define APBDEV_PMC_AUTO_WAKE_LVL_MASK (0x0DC)
|
||||
#define APBDEV_PMC_WAKE_DELAY (0x0E0)
|
||||
#define APBDEV_PMC_PWR_DET_VAL (0x0E4)
|
||||
#define APBDEV_PMC_CRYPTO_OP (0x0F4)
|
||||
#define APBDEV_PMC_SCRATCH31 (0x118)
|
||||
#define APBDEV_PMC_SCRATCH32 (0x11C)
|
||||
#define APBDEV_PMC_SCRATCH33 (0x120)
|
||||
#define APBDEV_PMC_SCRATCH40 (0x13C)
|
||||
#define APBDEV_PMC_WAKE2_MASK (0x160)
|
||||
#define APBDEV_PMC_WAKE2_LVL (0x164)
|
||||
#define APBDEV_PMC_WAKE2_STATUS (0x168)
|
||||
#define APBDEV_PMC_AUTO_WAKE2_LVL_MASK (0x170)
|
||||
#define APBDEV_PMC_OSC_EDPD_OVER (0x1A4)
|
||||
#define APBDEV_PMC_CLK_OUT_CNTRL (0x1A8)
|
||||
#define APBDEV_PMC_IO_DPD_REQ (0x1B8)
|
||||
#define APBDEV_PMC_IO_DPD_STATUS (0x1BC)
|
||||
#define APBDEV_PMC_IO_DPD2_REQ (0x1C0)
|
||||
#define APBDEV_PMC_IO_DPD2_STATUS (0x1C4)
|
||||
#define APBDEV_PMC_SEL_DPD_TIM (0x1C8)
|
||||
#define APBDEV_PMC_SCRATCH45 (0x234)
|
||||
#define APBDEV_PMC_SCRATCH46 (0x238)
|
||||
#define APBDEV_PMC_TSC_MULT (0x2B4)
|
||||
#define APBDEV_PMC_STICKY_BITS (0x2C0)
|
||||
#define APBDEV_PMC_WEAK_BIAS (0x2C8)
|
||||
#define APBDEV_PMC_GPU_RG_CNTRL (0x2D4)
|
||||
#define APBDEV_PMC_CNTRL2 (0x440)
|
||||
#define APBDEV_PMC_FUSE_CTRL (0x450)
|
||||
#define APBDEV_PMC_IO_DPD3_REQ (0x45C)
|
||||
#define APBDEV_PMC_IO_DPD3_STATUS (0x460)
|
||||
#define APBDEV_PMC_IO_DPD4_REQ (0x464)
|
||||
#define APBDEV_PMC_IO_DPD4_STATUS (0x468)
|
||||
#define APBDEV_PMC_SET_SW_CLAMP (0x47C)
|
||||
#define APBDEV_PMC_WAKE_DEBOUNCE_EN (0x4D8)
|
||||
#define APBDEV_PMC_DDR_CNTRL (0x4E4)
|
||||
#define APBDEV_PMC_SEC_DISABLE (0x004)
|
||||
#define APBDEV_PMC_SEC_DISABLE2 (0x2C4)
|
||||
#define APBDEV_PMC_SEC_DISABLE3 (0x2D8)
|
||||
#define APBDEV_PMC_SEC_DISABLE4 (0x5B0)
|
||||
#define APBDEV_PMC_SEC_DISABLE5 (0x5B4)
|
||||
#define APBDEV_PMC_SEC_DISABLE6 (0x5B8)
|
||||
#define APBDEV_PMC_SEC_DISABLE7 (0x5BC)
|
||||
#define APBDEV_PMC_SEC_DISABLE8 (0x5C0)
|
||||
#define APBDEV_PMC_SCRATCH43 (0x22C)
|
||||
#define APBDEV_PMC_SCRATCH190 (0x818)
|
||||
#define APBDEV_PMC_SCRATCH200 (0x840)
|
||||
#define APBDEV_PMC_SEC_DISABLE3 (0x2D8)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH4 (0x0C0)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH5 (0x0C4)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH6 (0x224)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH7 (0x228)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH16 (0x320)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH21 (0x334)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH24 (0x340)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH25 (0x344)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH26 (0x348)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH27 (0x34C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH32 (0x360)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH34 (0x368)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH35 (0x36C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH39 (0x37C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH51 (0x3AC)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH55 (0x3BC)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH74 (0x408)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH75 (0x40C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH76 (0x410)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH77 (0x414)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH78 (0x418)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH99 (0xAE4)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH100 (0xAE8)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH101 (0xAEC)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH102 (0xAF0)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH103 (0xAF4)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH112 (0xB18)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH113 (0xB1C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH114 (0xB20)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH115 (0xB24)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH119 (0xB34)
|
||||
|
||||
|
||||
#define PMC_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (APBDEV_PMC, NAME)
|
||||
#define PMC_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (APBDEV_PMC, NAME, VALUE)
|
||||
#define PMC_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (APBDEV_PMC, NAME, ENUM)
|
||||
#define PMC_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(APBDEV_PMC, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_PMC_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (APBDEV_PMC, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_PMC_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (APBDEV_PMC, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_PMC_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (APBDEV_PMC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_PMC_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(APBDEV_PMC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_PMC_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (APBDEV_PMC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(CNTRL_MAIN_RESET, 4, DISABLE, ENABLE)
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(DPD_SAMPLE_ON, 0, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(DPD_ENABLE_ON, 0, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(DPD_ENABLE_TSC_MULT_EN, 1, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_TOGGLE_START, 8, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_PMC_REG(PWRGATE_TOGGLE_PARTID, 0, 5);
|
||||
|
||||
enum APBDEV_PMC_PWRGATE_TOGGLE_PARTID : u8 {
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CRAIL = 0,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_VE = 2,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_PCX = 3,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_MPE = 6,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_SAX = 8,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE1 = 9,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE2 = 10,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE3 = 11,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE0 = 14,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_C0NC = 15,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_SOR = 17,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_DIS = 18,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_DISB = 19,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_XUSBA = 20,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_XUSBB = 21,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_XUSBC = 22,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_VIC = 23,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_IRAM = 24,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_NVDEC = 25,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_NVJPG = 26,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_AUD = 27,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_DFD = 28,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_VE2 = 29,
|
||||
};
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(REMOVE_CLAMPING_COMMAND_CRAIL, 0, DISABLE, ENABLE);
|
||||
|
||||
enum APBDEV_PMC_PWRGATE_STATUS_STATUS {
|
||||
APBDEV_PMC_PWRGATE_STATUS_STATUS_OFF = 0,
|
||||
APBDEV_PMC_PWRGATE_STATUS_STATUS_ON = 1,
|
||||
};
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_CRAIL, 0, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_VE, 2, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_PCX, 3, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_MPE, 6, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_SAX, 8, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_CE1, 9, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_CE2, 10, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_CE3, 11, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_CE0, 14, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_C0NC, 15, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_SOR, 17, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_DIS, 18, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_DISB, 19, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_XUSBA, 20, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_XUSBB, 21, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_XUSBC, 22, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_VIC, 23, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_IRAM, 24, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_NVDEC, 25, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_NVJPG, 26, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_AUD, 27, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_DFD, 28, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_VE2, 29, OFF, ON);
|
||||
|
||||
DEFINE_PMC_REG(PWRGATE_STATUS_CE123, 9, 3);
|
||||
|
||||
DEFINE_PMC_REG(SET_SW_CLAMP_CRAIL, 0, 1);
|
||||
|
||||
DEFINE_PMC_REG_TWO_BIT_ENUM(IO_DPD_REQ_CODE, 30, IDLE, DPD_OFF, DPD_ON, RESERVED3);
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_CRAIL, 0, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_TE, 1, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_VE, 2, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_PCX, 3, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_VDE, 4, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_MPE, 6, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_HEG, 7, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_SAX, 8, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_CE1, 9, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_CE2, 10, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_CE3, 11, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_CELP, 12, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_CE0, 14, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_C0NC, 15, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_SOR, 17, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_C1NC, 16, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_DIS, 18, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_DISB, 19, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_XUSBA, 20, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_XUSBB, 21, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_XUSBC, 22, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_VIC, 23, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_IRAM, 24, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_PMC_REG(OSC_EDPD_OVER_XOFS, 1, 6);
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(STICKY_BITS_HDA_LPBK_DIS, 0, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(STICKY_BITS_JTAG_STS, 6, ENABLE, DISABLE);
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(CNTRL2_WAKE_DET_EN, 9, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(SEC_DISABLE2_WRITE21, 26, OFF, ON);
|
||||
52
libraries/libvapours/include/vapours/tegra/tegra_sb.hpp
Normal file
52
libraries/libvapours/include/vapours/tegra/tegra_sb.hpp
Normal file
@@ -0,0 +1,52 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define SB_CSR (0x200)
|
||||
#define SB_PFCFG (0x208)
|
||||
#define SB_AA64_RESET_LOW (0x230)
|
||||
#define SB_AA64_RESET_HIGH (0x234)
|
||||
|
||||
|
||||
#define SB_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (SB, NAME)
|
||||
#define SB_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (SB, NAME, VALUE)
|
||||
#define SB_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (SB, NAME, ENUM)
|
||||
#define SB_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(SB, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_SB_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (SB, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_SB_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (SB, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_SB_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (SB, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_SB_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(SB, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_SB_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (SB, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_SB_REG_BIT_ENUM(CSR_SECURE_BOOT_FLAG, 0, DISABLE, ENABLE);
|
||||
DEFINE_SB_REG_BIT_ENUM(CSR_NS_RST_VEC_WR_DIS, 1, ENABLE, DISABLE);
|
||||
DEFINE_SB_REG_BIT_ENUM(CSR_PIROM_DISABLE, 4, ENABLE, DISABLE);
|
||||
DEFINE_SB_REG_BIT_ENUM(CSR_HANG, 6, DISABLE, ENABLE);
|
||||
DEFINE_SB_REG_BIT_ENUM(CSR_SWDM_ENABLE, 7, DISABLE, ENABLE);
|
||||
DEFINE_SB_REG(CSR_SWDM_FAIL_COUNT, 8, 4);
|
||||
DEFINE_SB_REG(CSR_COT_FAIL_COUNT, 12, 4);
|
||||
|
||||
DEFINE_SB_REG_BIT_ENUM(PFCFG_SPNIDEN, 0, DISABLE, ENABLE);
|
||||
DEFINE_SB_REG_BIT_ENUM(PFCFG_SPIDEN, 1, DISABLE, ENABLE);
|
||||
DEFINE_SB_REG_BIT_ENUM(PFCFG_NIDEN, 2, DISABLE, ENABLE);
|
||||
DEFINE_SB_REG_BIT_ENUM(PFCFG_DBGEN, 3, DISABLE, ENABLE);
|
||||
58
libraries/libvapours/include/vapours/tegra/tegra_sysctr0.hpp
Normal file
58
libraries/libvapours/include/vapours/tegra/tegra_sysctr0.hpp
Normal file
@@ -0,0 +1,58 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define SYSCTR0_CNTCR (0x000)
|
||||
#define SYSCTR0_CNTCV0 (0x008)
|
||||
#define SYSCTR0_CNTCV1 (0x00C)
|
||||
#define SYSCTR0_CNTFID0 (0x020)
|
||||
#define SYSCTR0_CNTFID1 (0x024)
|
||||
|
||||
|
||||
#define SYSCTR0_COUNTERID4 (0xFD0)
|
||||
#define SYSCTR0_COUNTERID5 (0xFD4)
|
||||
#define SYSCTR0_COUNTERID6 (0xFD8)
|
||||
#define SYSCTR0_COUNTERID7 (0xFDC)
|
||||
#define SYSCTR0_COUNTERID0 (0xFE0)
|
||||
#define SYSCTR0_COUNTERID1 (0xFE4)
|
||||
#define SYSCTR0_COUNTERID2 (0xFE8)
|
||||
#define SYSCTR0_COUNTERID3 (0xFEC)
|
||||
#define SYSCTR0_COUNTERID8 (0xFF0)
|
||||
#define SYSCTR0_COUNTERID9 (0xFF4)
|
||||
#define SYSCTR0_COUNTERID10 (0xFF8)
|
||||
#define SYSCTR0_COUNTERID11 (0xFFC)
|
||||
|
||||
#define SYSCTR0_COUNTERID(n) SYSCTR0_COUNTERID##n
|
||||
|
||||
#define SYSCTR0_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (SYSCTR0, NAME)
|
||||
#define SYSCTR0_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (SYSCTR0, NAME, VALUE)
|
||||
#define SYSCTR0_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (SYSCTR0, NAME, ENUM)
|
||||
#define SYSCTR0_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(SYSCTR0, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_SYSCTR0_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (SYSCTR0, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_SYSCTR0_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (SYSCTR0, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_SYSCTR0_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (SYSCTR0, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_SYSCTR0_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(SYSCTR0, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_SYSCTR0_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (SYSCTR0, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_SYSCTR0_REG_BIT_ENUM(CNTCR_EN, 0, DISABLE, ENABLE);
|
||||
DEFINE_SYSCTR0_REG_BIT_ENUM(CNTCR_HDBG, 1, DISABLE, ENABLE);
|
||||
49
libraries/libvapours/include/vapours/tegra/tegra_timer.hpp
Normal file
49
libraries/libvapours/include/vapours/tegra/tegra_timer.hpp
Normal file
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define TIMERUS_USEC_CFG (0x014)
|
||||
#define TIMER_SHARED_TIMER_SECURE_CFG (0x1A4)
|
||||
|
||||
#define TIMER_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (TIMER, NAME)
|
||||
#define TIMER_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (TIMER, NAME, VALUE)
|
||||
#define TIMER_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (TIMER, NAME, ENUM)
|
||||
#define TIMER_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(TIMER, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_TIMER_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (TIMER, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_TIMER_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (TIMER, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_TIMER_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (TIMER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_TIMER_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(TIMER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_TIMER_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (TIMER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_TIMER_REG(USEC_CFG_USEC_DIVISOR, 0, 8);
|
||||
DEFINE_TIMER_REG(USEC_CFG_USEC_DIVIDEND, 8, 8);
|
||||
|
||||
DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_TMR5, 5, DISABLE, ENABLE);
|
||||
DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_TMR6, 6, DISABLE, ENABLE);
|
||||
DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_TMR7, 7, DISABLE, ENABLE);
|
||||
DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_TMR8, 8, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_WDT0, 12, DISABLE, ENABLE);
|
||||
DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_WDT1, 13, DISABLE, ENABLE);
|
||||
DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_WDT2, 14, DISABLE, ENABLE);
|
||||
DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_WDT3, 15, DISABLE, ENABLE);
|
||||
@@ -62,6 +62,66 @@ namespace ams::sdmmc::impl {
|
||||
reg::Read(this->registers->clock_control);
|
||||
}
|
||||
|
||||
Result SdHostStandardController::EnableInternalClock() {
|
||||
/* Enable internal clock. */
|
||||
reg::ReadWrite(this->registers->clock_control, SD_REG_BITS_ENUM(CLOCK_CONTROL_INTERNAL_CLOCK_ENABLE, OSCILLATE));
|
||||
this->EnsureControl();
|
||||
|
||||
/* Wait for the internal clock to become stable. */
|
||||
{
|
||||
ManualTimer timer(ControllerReactionTimeoutMilliSeconds);
|
||||
while (true) {
|
||||
/* Check if the clock is steady. */
|
||||
if (reg::HasValue(this->registers->clock_control, SD_REG_BITS_ENUM(CLOCK_CONTROL_INTERNAL_CLOCK_STABLE, READY))) {
|
||||
break;
|
||||
}
|
||||
|
||||
/* If not, check for timeout. */
|
||||
R_UNLESS(timer.Update(), sdmmc::ResultInternalClockStableSoftwareTimeout());
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure to use host controlled divided clock. */
|
||||
reg::ReadWrite(this->registers->host_control2, SD_REG_BITS_ENUM(HOST_CONTROL2_PRESET_VALUE_ENABLE, HOST_DRIVER));
|
||||
reg::ReadWrite(this->registers->clock_control, SD_REG_BITS_ENUM(CLOCK_CONTROL_CLOCK_GENERATOR_SELECT, DIVIDED_CLOCK));
|
||||
|
||||
/* Set host version 4.0.0 enable. */
|
||||
reg::ReadWrite(this->registers->host_control2, SD_REG_BITS_ENUM(HOST_CONTROL2_HOST_VERSION_4_ENABLE, VERSION_4));
|
||||
|
||||
/* Set host 64 bit addressing enable. */
|
||||
AMS_ABORT_UNLESS(reg::HasValue(this->registers->capabilities, SD_REG_BITS_ENUM(CAPABILITIES_64_BIT_SYSTEM_ADDRESS_SUPPORT_FOR_V3, SUPPORTED)));
|
||||
reg::ReadWrite(this->registers->host_control2, SD_REG_BITS_ENUM(HOST_CONTROL2_64_BIT_ADDRESSING, 64_BIT_ADDRESSING));
|
||||
|
||||
/* Select SDMA mode. */
|
||||
reg::ReadWrite(this->registers->host_control, SD_REG_BITS_ENUM(HOST_CONTROL_DMA_SELECT, SDMA));
|
||||
|
||||
/* Configure timeout control to use the maximum timeout value (TMCLK * 2^27) */
|
||||
reg::ReadWrite(this->registers->timeout_control, SD_REG_BITS_VALUE(TIMEOUT_CONTROL_DATA_TIMEOUT_COUNTER, 0b1110));
|
||||
|
||||
return ResultSuccess();
|
||||
}
|
||||
|
||||
void SdHostStandardController::SetBusPower(BusPower bus_power) {
|
||||
/* Check that we support the bus power. */
|
||||
AMS_ABORT_UNLESS(this->IsSupportedBusPower(bus_power));
|
||||
|
||||
/* Set the appropriate power. */
|
||||
switch (bus_power) {
|
||||
case BusPower_Off:
|
||||
reg::ReadWrite(this->registers->power_control, SD_REG_BITS_ENUM(POWER_CONTROL_SD_BUS_POWER_FOR_VDD1, OFF));
|
||||
break;
|
||||
case BusPower_1_8V:
|
||||
reg::ReadWrite(this->registers->power_control, SD_REG_BITS_ENUM(POWER_CONTROL_SD_BUS_VOLTAGE_SELECT_FOR_VDD1, 1_8V));
|
||||
reg::ReadWrite(this->registers->power_control, SD_REG_BITS_ENUM(POWER_CONTROL_SD_BUS_POWER_FOR_VDD1, ON));
|
||||
break;
|
||||
case BusPower_3_3V:
|
||||
reg::ReadWrite(this->registers->power_control, SD_REG_BITS_ENUM(POWER_CONTROL_SD_BUS_VOLTAGE_SELECT_FOR_VDD1, 3_3V));
|
||||
reg::ReadWrite(this->registers->power_control, SD_REG_BITS_ENUM(POWER_CONTROL_SD_BUS_POWER_FOR_VDD1, ON));
|
||||
break;
|
||||
AMS_UNREACHABLE_DEFAULT_CASE();
|
||||
}
|
||||
}
|
||||
|
||||
void SdHostStandardController::EnableInterruptStatus() {
|
||||
/* Set the status register interrupt enables. */
|
||||
reg::ReadWrite(this->registers->normal_int_enable, SD_HOST_STANDARD_NORMAL_INTERRUPT_ENABLE_ISSUE_COMMAND(ENABLED));
|
||||
@@ -156,7 +216,7 @@ namespace ams::sdmmc::impl {
|
||||
|
||||
/* Configure block size. */
|
||||
AMS_ABORT_UNLESS(xfer_data->block_size <= SdHostStandardBlockSizeTransferBlockSizeMax);
|
||||
reg::Write(this->registers->block_size, SD_REG_BITS_ENUM (BLOCK_SIZE_SDMA_BUFFER_BOUNDARY, FIVE_TWELVE_KB),
|
||||
reg::Write(this->registers->block_size, SD_REG_BITS_ENUM (BLOCK_SIZE_SDMA_BUFFER_BOUNDARY, 512_KB),
|
||||
SD_REG_BITS_VALUE(BLOCK_SIZE_TRANSFER_BLOCK_SIZE, static_cast<u16>(xfer_data->block_size)));
|
||||
|
||||
/* Configure transfer blocks. */
|
||||
@@ -173,6 +233,31 @@ namespace ams::sdmmc::impl {
|
||||
SD_REG_BITS_ENUM_SEL(TRANSFER_MODE_AUTO_CMD_ENABLE, (xfer_data->is_stop_transmission_command_enabled), CMD12_ENABLE, DISABLE));
|
||||
}
|
||||
|
||||
void SdHostStandardController::SetTransferForTuning() {
|
||||
/* Get the tuning block size. */
|
||||
u16 tuning_block_size;
|
||||
switch (this->GetBusWidth()) {
|
||||
case BusWidth_4Bit:
|
||||
tuning_block_size = 64;
|
||||
break;
|
||||
case BusWidth_8Bit:
|
||||
tuning_block_size = 128;
|
||||
break;
|
||||
case BusWidth_1Bit:
|
||||
AMS_UNREACHABLE_DEFAULT_CASE();
|
||||
}
|
||||
|
||||
/* Configure block size. */
|
||||
AMS_ABORT_UNLESS(tuning_block_size <= SdHostStandardBlockSizeTransferBlockSizeMax);
|
||||
reg::Write(this->registers->block_size, SD_REG_BITS_VALUE(BLOCK_SIZE_TRANSFER_BLOCK_SIZE, tuning_block_size));
|
||||
|
||||
/* Configure transfer blocks. */
|
||||
reg::Write(this->registers->block_count, 1);
|
||||
|
||||
/* Configure transfer mode. */
|
||||
reg::Write(this->registers->transfer_mode, SD_REG_BITS_ENUM(TRANSFER_MODE_DATA_TRANSFER_DIRECTION, READ));
|
||||
}
|
||||
|
||||
void SdHostStandardController::SetCommand(const Command *command, bool has_xfer_data) {
|
||||
/* Encode the command value. */
|
||||
u16 command_val = 0;
|
||||
@@ -216,6 +301,11 @@ namespace ams::sdmmc::impl {
|
||||
reg::Write(this->registers->command, command_val);
|
||||
}
|
||||
|
||||
void SdHostStandardController::SetCommandForTuning(u32 command_index) {
|
||||
Command command(command_index, 0, ResponseType_R1, false);
|
||||
return this->SetCommand(std::addressof(command), true);
|
||||
}
|
||||
|
||||
Result SdHostStandardController::ResetCmdDatLine() {
|
||||
/* Set the software reset cmd/dat bits. */
|
||||
reg::ReadWrite(this->registers->software_reset, SD_REG_BITS_ENUM(SOFTWARE_RESET_FOR_CMD, RESET),
|
||||
@@ -855,7 +945,7 @@ namespace ams::sdmmc::impl {
|
||||
AMS_ABORT_UNLESS(this->is_device_clock_enable);
|
||||
|
||||
/* Check if we need to temporarily re-enable the device clock. */
|
||||
bool clock_disabled = reg::HasValue(this->registers->clock_control, SD_REG_BITS_ENUM(CLOCK_CONTROL_SD_CLOCK_ENABLE, DISABLE));
|
||||
const bool clock_disabled = reg::HasValue(this->registers->clock_control, SD_REG_BITS_ENUM(CLOCK_CONTROL_SD_CLOCK_ENABLE, DISABLE));
|
||||
|
||||
/* Ensure that the clock is enabled and the device is usable for the period we're using it. */
|
||||
if (clock_disabled) {
|
||||
@@ -884,7 +974,7 @@ namespace ams::sdmmc::impl {
|
||||
AMS_ABORT_UNLESS(this->is_device_clock_enable);
|
||||
|
||||
/* Check if we need to temporarily re-enable the device clock. */
|
||||
bool clock_disabled = reg::HasValue(this->registers->clock_control, SD_REG_BITS_ENUM(CLOCK_CONTROL_SD_CLOCK_ENABLE, DISABLE));
|
||||
const bool clock_disabled = reg::HasValue(this->registers->clock_control, SD_REG_BITS_ENUM(CLOCK_CONTROL_SD_CLOCK_ENABLE, DISABLE));
|
||||
|
||||
/* Ensure that the clock is enabled and the device is usable for the period we're using it. */
|
||||
if (clock_disabled) {
|
||||
|
||||
@@ -67,12 +67,18 @@ namespace ams::sdmmc::impl {
|
||||
}
|
||||
#endif
|
||||
|
||||
void SetDeviceClockFrequencyKHz(u32 khz) {
|
||||
this->device_clock_frequency_khz = khz;
|
||||
}
|
||||
|
||||
#if defined(AMS_SDMMC_USE_DEVICE_VIRTUAL_ADDRESS)
|
||||
void ResetBufferInfos();
|
||||
dd::DeviceVirtualAddress GetDeviceVirtualAddress(uintptr_t buffer, size_t buffer_size);
|
||||
#endif
|
||||
|
||||
void EnsureControl();
|
||||
Result EnableInternalClock();
|
||||
void SetBusPower(BusPower bus_power);
|
||||
|
||||
void EnableInterruptStatus();
|
||||
void DisableInterruptStatus();
|
||||
@@ -83,8 +89,10 @@ namespace ams::sdmmc::impl {
|
||||
#endif
|
||||
|
||||
void SetTransfer(u32 *out_num_transferred_blocks, const TransferData *xfer_data);
|
||||
void SetTransferForTuning();
|
||||
|
||||
void SetCommand(const Command *command, bool has_xfer_data);
|
||||
void SetCommandForTuning(u32 command_index);
|
||||
|
||||
Result ResetCmdDatLine();
|
||||
Result AbortTransaction();
|
||||
|
||||
@@ -83,7 +83,7 @@ namespace ams::sdmmc::impl {
|
||||
#define DEFINE_SD_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (SD_HOST_STANDARD, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_SD_REG(BLOCK_SIZE_TRANSFER_BLOCK_SIZE, 0, 12);
|
||||
DEFINE_SD_REG_THREE_BIT_ENUM(BLOCK_SIZE_SDMA_BUFFER_BOUNDARY, 12, FOUR_KB, EIGHT_KB, SIXTEEN_KB, THIRTY_TWO_KB, SIXTY_FOUR_KB, ONE_TWENTY_EIGHT_KB, TWO_FIFTY_SIX_KB, FIVE_TWELVE_KB);
|
||||
DEFINE_SD_REG_THREE_BIT_ENUM(BLOCK_SIZE_SDMA_BUFFER_BOUNDARY, 12, 4_KB, 8_KB, 16_KB, 32_KB, 64_KB, 128_KB, 256_KB, 512_KB);
|
||||
constexpr inline size_t SdHostStandardBlockSizeTransferBlockSizeMax = 0xFFF;
|
||||
|
||||
DEFINE_SD_REG_BIT_ENUM(TRANSFER_MODE_DMA_ENABLE, 0, DISABLE, ENABLE);
|
||||
@@ -105,6 +105,7 @@ namespace ams::sdmmc::impl {
|
||||
DEFINE_SD_REG_BIT_ENUM(PRESENT_STATE_DAT1_LINE_SIGNAL_LEVEL, 21, LOW, HIGH);
|
||||
DEFINE_SD_REG_BIT_ENUM(PRESENT_STATE_DAT2_LINE_SIGNAL_LEVEL, 22, LOW, HIGH);
|
||||
DEFINE_SD_REG_BIT_ENUM(PRESENT_STATE_DAT3_LINE_SIGNAL_LEVEL, 23, LOW, HIGH);
|
||||
DEFINE_SD_REG(PRESENT_STATE_DAT0_3_LINE_SIGNAL_LEVEL, 20, 4);
|
||||
|
||||
DEFINE_SD_REG_BIT_ENUM(HOST_CONTROL_DATA_TRANSFER_WIDTH, 1, ONE_BIT, FOUR_BIT);
|
||||
DEFINE_SD_REG_BIT_ENUM(HOST_CONTROL_HIGH_SPEED_ENABLE, 2, NORMAL_SPEED, HIGH_SPEED);
|
||||
@@ -114,7 +115,14 @@ namespace ams::sdmmc::impl {
|
||||
DEFINE_SD_REG_BIT_ENUM(POWER_CONTROL_SD_BUS_POWER_FOR_VDD1, 0, OFF, ON);
|
||||
DEFINE_SD_REG_THREE_BIT_ENUM(POWER_CONTROL_SD_BUS_VOLTAGE_SELECT_FOR_VDD1, 1, RESERVED0, RESERVED1, RESERVED2, RESERVED3, RESERVED4, 1_8V, 3_0V, 3_3V);
|
||||
|
||||
DEFINE_SD_REG_BIT_ENUM(CLOCK_CONTROL_INTERNAL_CLOCK_ENABLE, 0, STOP, OSCILLATE);
|
||||
DEFINE_SD_REG_BIT_ENUM(CLOCK_CONTROL_INTERNAL_CLOCK_STABLE, 1, NOT_READY, READY);
|
||||
DEFINE_SD_REG_BIT_ENUM(CLOCK_CONTROL_SD_CLOCK_ENABLE, 2, DISABLE, ENABLE);
|
||||
DEFINE_SD_REG_BIT_ENUM(CLOCK_CONTROL_CLOCK_GENERATOR_SELECT, 5, DIVIDED_CLOCK, PROGRAMMABLE_CLOCK);
|
||||
DEFINE_SD_REG(CLOCK_CONTROL_UPPER_BITS_OF_SDCLK_FREQUENCY_SELECT, 6, 2);
|
||||
DEFINE_SD_REG(CLOCK_CONTROL_SDCLK_FREQUENCY_SELECT, 8, 8);
|
||||
|
||||
DEFINE_SD_REG(TIMEOUT_CONTROL_DATA_TIMEOUT_COUNTER, 0, 4);
|
||||
|
||||
DEFINE_SD_REG_BIT_ENUM(SOFTWARE_RESET_FOR_ALL, 0, WORK, RESET);
|
||||
DEFINE_SD_REG_BIT_ENUM(SOFTWARE_RESET_FOR_CMD, 1, WORK, RESET);
|
||||
@@ -139,30 +147,47 @@ namespace ams::sdmmc::impl {
|
||||
DEFINE_SD_REG_BIT_ENUM(AUTO_CMD_ERROR_AUTO_CMD_END_BIT, 3, NO_ERROR, ERROR);
|
||||
DEFINE_SD_REG_BIT_ENUM(AUTO_CMD_ERROR_AUTO_CMD_INDEX, 4, NO_ERROR, ERROR);
|
||||
|
||||
DEFINE_SD_REG_BIT_ENUM(NORMAL_INTERRUPT_STATUS_ENABLE_COMMAND_COMPLETE, 0, MASKED, ENABLED);
|
||||
DEFINE_SD_REG_BIT_ENUM(NORMAL_INTERRUPT_STATUS_ENABLE_TRANSFER_COMPLETE, 1, MASKED, ENABLED);
|
||||
DEFINE_SD_REG_BIT_ENUM(NORMAL_INTERRUPT_COMMAND_COMPLETE, 0, MASKED, ENABLED);
|
||||
DEFINE_SD_REG_BIT_ENUM(NORMAL_INTERRUPT_TRANSFER_COMPLETE, 1, MASKED, ENABLED);
|
||||
DEFINE_SD_REG_BIT_ENUM(NORMAL_INTERRUPT_DMA_INTERRUPT, 3, MASKED, ENABLED);
|
||||
DEFINE_SD_REG_BIT_ENUM(NORMAL_INTERRUPT_BUFFER_READ_READY, 5, MASKED, ENABLED);
|
||||
|
||||
#define SD_HOST_STANDARD_NORMAL_INTERRUPT_ENABLE_ISSUE_COMMAND(__ENUM__) \
|
||||
SD_REG_BITS_ENUM(NORMAL_INTERRUPT_STATUS_ENABLE_COMMAND_COMPLETE, __ENUM__), \
|
||||
SD_REG_BITS_ENUM(NORMAL_INTERRUPT_STATUS_ENABLE_TRANSFER_COMPLETE, __ENUM__)
|
||||
SD_REG_BITS_ENUM(NORMAL_INTERRUPT_COMMAND_COMPLETE, __ENUM__), \
|
||||
SD_REG_BITS_ENUM(NORMAL_INTERRUPT_TRANSFER_COMPLETE, __ENUM__), \
|
||||
SD_REG_BITS_ENUM(NORMAL_INTERRUPT_DMA_INTERRUPT, __ENUM__)
|
||||
|
||||
DEFINE_SD_REG_BIT_ENUM(ERROR_INTERRUPT_STATUS_ENABLE_COMMAND_TIMEOUT_ERROR, 0, MASKED, ENABLED);
|
||||
DEFINE_SD_REG_BIT_ENUM(ERROR_INTERRUPT_STATUS_ENABLE_COMMAND_CRC_ERROR, 1, MASKED, ENABLED);
|
||||
DEFINE_SD_REG_BIT_ENUM(ERROR_INTERRUPT_STATUS_ENABLE_COMMAND_END_BIT_ERROR, 2, MASKED, ENABLED);
|
||||
DEFINE_SD_REG_BIT_ENUM(ERROR_INTERRUPT_STATUS_ENABLE_COMMAND_INDEX_ERROR, 3, MASKED, ENABLED);
|
||||
DEFINE_SD_REG_BIT_ENUM(ERROR_INTERRUPT_STATUS_ENABLE_DATA_TIMEOUT_ERROR, 4, MASKED, ENABLED);
|
||||
DEFINE_SD_REG_BIT_ENUM(ERROR_INTERRUPT_STATUS_ENABLE_DATA_CRC_ERROR, 5, MASKED, ENABLED);
|
||||
DEFINE_SD_REG_BIT_ENUM(ERROR_INTERRUPT_STATUS_ENABLE_DATA_END_BIT_ERROR, 6, MASKED, ENABLED);
|
||||
DEFINE_SD_REG_BIT_ENUM(ERROR_INTERRUPT_STATUS_ENABLE_AUTO_CMD_ERROR, 8, MASKED, ENABLED);
|
||||
DEFINE_SD_REG_BIT_ENUM(ERROR_INTERRUPT_COMMAND_TIMEOUT_ERROR, 0, MASKED, ENABLED);
|
||||
DEFINE_SD_REG_BIT_ENUM(ERROR_INTERRUPT_COMMAND_CRC_ERROR, 1, MASKED, ENABLED);
|
||||
DEFINE_SD_REG_BIT_ENUM(ERROR_INTERRUPT_COMMAND_END_BIT_ERROR, 2, MASKED, ENABLED);
|
||||
DEFINE_SD_REG_BIT_ENUM(ERROR_INTERRUPT_COMMAND_INDEX_ERROR, 3, MASKED, ENABLED);
|
||||
DEFINE_SD_REG_BIT_ENUM(ERROR_INTERRUPT_DATA_TIMEOUT_ERROR, 4, MASKED, ENABLED);
|
||||
DEFINE_SD_REG_BIT_ENUM(ERROR_INTERRUPT_DATA_CRC_ERROR, 5, MASKED, ENABLED);
|
||||
DEFINE_SD_REG_BIT_ENUM(ERROR_INTERRUPT_DATA_END_BIT_ERROR, 6, MASKED, ENABLED);
|
||||
DEFINE_SD_REG_BIT_ENUM(ERROR_INTERRUPT_AUTO_CMD_ERROR, 8, MASKED, ENABLED);
|
||||
|
||||
#define SD_HOST_STANDARD_ERROR_INTERRUPT_ENABLE_ISSUE_COMMAND(__ENUM__) \
|
||||
SD_REG_BITS_ENUM(ERROR_INTERRUPT_STATUS_ENABLE_COMMAND_TIMEOUT_ERROR, __ENUM__), \
|
||||
SD_REG_BITS_ENUM(ERROR_INTERRUPT_STATUS_ENABLE_COMMAND_CRC_ERROR, __ENUM__), \
|
||||
SD_REG_BITS_ENUM(ERROR_INTERRUPT_STATUS_ENABLE_COMMAND_END_BIT_ERROR, __ENUM__), \
|
||||
SD_REG_BITS_ENUM(ERROR_INTERRUPT_STATUS_ENABLE_COMMAND_INDEX_ERROR, __ENUM__), \
|
||||
SD_REG_BITS_ENUM(ERROR_INTERRUPT_STATUS_ENABLE_DATA_TIMEOUT_ERROR, __ENUM__), \
|
||||
SD_REG_BITS_ENUM(ERROR_INTERRUPT_STATUS_ENABLE_DATA_CRC_ERROR, __ENUM__), \
|
||||
SD_REG_BITS_ENUM(ERROR_INTERRUPT_STATUS_ENABLE_DATA_END_BIT_ERROR, __ENUM__), \
|
||||
SD_REG_BITS_ENUM(ERROR_INTERRUPT_STATUS_ENABLE_AUTO_CMD_ERROR, __ENUM__)
|
||||
SD_REG_BITS_ENUM(ERROR_INTERRUPT_COMMAND_TIMEOUT_ERROR, __ENUM__), \
|
||||
SD_REG_BITS_ENUM(ERROR_INTERRUPT_COMMAND_CRC_ERROR, __ENUM__), \
|
||||
SD_REG_BITS_ENUM(ERROR_INTERRUPT_COMMAND_END_BIT_ERROR, __ENUM__), \
|
||||
SD_REG_BITS_ENUM(ERROR_INTERRUPT_COMMAND_INDEX_ERROR, __ENUM__), \
|
||||
SD_REG_BITS_ENUM(ERROR_INTERRUPT_DATA_TIMEOUT_ERROR, __ENUM__), \
|
||||
SD_REG_BITS_ENUM(ERROR_INTERRUPT_DATA_CRC_ERROR, __ENUM__), \
|
||||
SD_REG_BITS_ENUM(ERROR_INTERRUPT_DATA_END_BIT_ERROR, __ENUM__), \
|
||||
SD_REG_BITS_ENUM(ERROR_INTERRUPT_AUTO_CMD_ERROR, __ENUM__)
|
||||
|
||||
|
||||
DEFINE_SD_REG_THREE_BIT_ENUM(HOST_CONTROL2_UHS_MODE_SELECT, 0, SDR12, SDR25, SDR50, SDR104, DDR50, HS400, RSVD6, UHS_II);
|
||||
|
||||
constexpr inline auto SD_HOST_STANDARD_HOST_CONTROL2_UHS_MODE_SELECT_HS200 = SD_HOST_STANDARD_HOST_CONTROL2_UHS_MODE_SELECT_SDR104;
|
||||
|
||||
DEFINE_SD_REG_BIT_ENUM(HOST_CONTROL2_1_8V_SIGNALING_ENABLE, 3, 3_3V_SIGNALING, 1_8V_SIGNALING);
|
||||
DEFINE_SD_REG_BIT_ENUM(HOST_CONTROL2_EXECUTE_TUNING, 6, TUNING_COMPLETED, EXECUTE_TUNING);
|
||||
DEFINE_SD_REG_BIT_ENUM(HOST_CONTROL2_SAMPLING_CLOCK, 7, USING_FIXED_CLOCK, USING_TUNED_CLOCK);
|
||||
DEFINE_SD_REG_BIT_ENUM(HOST_CONTROL2_HOST_VERSION_4_ENABLE, 12, VERSION_300_COMPATIBLE, VERSION_4);
|
||||
DEFINE_SD_REG_BIT_ENUM(HOST_CONTROL2_64_BIT_ADDRESSING, 13, 32_BIT_ADDRESSING, 64_BIT_ADDRESSING);
|
||||
DEFINE_SD_REG_BIT_ENUM(HOST_CONTROL2_PRESET_VALUE_ENABLE, 15, HOST_DRIVER, AUTOMATIC_SELECTION);
|
||||
|
||||
DEFINE_SD_REG_BIT_ENUM(CAPABILITIES_64_BIT_SYSTEM_ADDRESS_SUPPORT_FOR_V3, 28, NOT_SUPPORTED, SUPPORTED);
|
||||
|
||||
}
|
||||
|
||||
@@ -0,0 +1,872 @@
|
||||
/*
|
||||
* Copyright (c) 2018-2020 Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#if defined(ATMOSPHERE_IS_STRATOSPHERE)
|
||||
#include <stratosphere.hpp>
|
||||
#elif defined(ATMOSPHERE_IS_MESOSPHERE)
|
||||
#include <mesosphere.hpp>
|
||||
#elif defined(ATMOSPHERE_IS_EXOSPHERE)
|
||||
#include <exosphere.hpp>
|
||||
#else
|
||||
#include <vapours.hpp>
|
||||
#endif
|
||||
#include "sdmmc_sdmmc_controller.board.nintendo_nx.hpp"
|
||||
#include "sdmmc_timer.hpp"
|
||||
|
||||
namespace ams::sdmmc::impl {
|
||||
|
||||
/* FOR REFERENCE: board-specific sdmmc registers. */
|
||||
//struct SdmmcRegisters {
|
||||
// /* Standard registers. */
|
||||
// volatile SdHostStandardRegisters sd_host_standard_registers;
|
||||
//
|
||||
// /* Vendor specific registers */
|
||||
// volatile uint32_t vendor_clock_cntrl;
|
||||
// volatile uint32_t vendor_sys_sw_cntrl;
|
||||
// volatile uint32_t vendor_err_intr_status;
|
||||
// volatile uint32_t vendor_cap_overrides;
|
||||
// volatile uint32_t vendor_boot_cntrl;
|
||||
// volatile uint32_t vendor_boot_ack_timeout;
|
||||
// volatile uint32_t vendor_boot_dat_timeout;
|
||||
// volatile uint32_t vendor_debounce_count;
|
||||
// volatile uint32_t vendor_misc_cntrl;
|
||||
// volatile uint32_t max_current_override;
|
||||
// volatile uint32_t max_current_override_hi;
|
||||
// volatile uint32_t _0x12c[0x20];
|
||||
// volatile uint32_t vendor_io_trim_cntrl;
|
||||
//
|
||||
// /* Start of sdmmc2/sdmmc4 only */
|
||||
// volatile uint32_t vendor_dllcal_cfg;
|
||||
// volatile uint32_t vendor_dll_ctrl0;
|
||||
// volatile uint32_t vendor_dll_ctrl1;
|
||||
// volatile uint32_t vendor_dllcal_cfg_sta;
|
||||
// /* End of sdmmc2/sdmmc4 only */
|
||||
//
|
||||
// volatile uint32_t vendor_tuning_cntrl0;
|
||||
// volatile uint32_t vendor_tuning_cntrl1;
|
||||
// volatile uint32_t vendor_tuning_status0;
|
||||
// volatile uint32_t vendor_tuning_status1;
|
||||
// volatile uint32_t vendor_clk_gate_hysteresis_count;
|
||||
// volatile uint32_t vendor_preset_val0;
|
||||
// volatile uint32_t vendor_preset_val1;
|
||||
// volatile uint32_t vendor_preset_val2;
|
||||
// volatile uint32_t sdmemcomppadctrl;
|
||||
// volatile uint32_t auto_cal_config;
|
||||
// volatile uint32_t auto_cal_interval;
|
||||
// volatile uint32_t auto_cal_status;
|
||||
// volatile uint32_t io_spare;
|
||||
// volatile uint32_t sdmmca_mccif_fifoctrl;
|
||||
// volatile uint32_t timeout_wcoal_sdmmca;
|
||||
// volatile uint32_t _0x1fc;
|
||||
//};
|
||||
|
||||
DEFINE_SD_REG_BIT_ENUM(VENDOR_CLOCK_CNTRL_SPI_MODE_CLKEN_OVERRIDE, 2, NORMAL, OVERRIDE);
|
||||
DEFINE_SD_REG(VENDOR_CLOCK_CNTRL_TAP_VAL, 16, 8);
|
||||
DEFINE_SD_REG(VENDOR_CLOCK_CNTRL_TRIM_VAL, 24, 5);
|
||||
|
||||
DEFINE_SD_REG(VENDOR_CAP_OVERRIDES_DQS_TRIM_VAL, 8, 6);
|
||||
|
||||
DEFINE_SD_REG(VENDOR_IO_TRIM_CNTRL_SEL_VREG, 2, 1);
|
||||
|
||||
DEFINE_SD_REG_BIT_ENUM(VENDOR_DLLCAL_CFG_CALIBRATE, 31, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_SD_REG_BIT_ENUM(VENDOR_DLLCAL_CFG_STA_DLL_CAL_ACTIVE, 31, DONE, RUNNING);
|
||||
|
||||
DEFINE_SD_REG(VENDOR_TUNING_CNTRL0_MUL_M, 6, 7);
|
||||
DEFINE_SD_REG_THREE_BIT_ENUM(VENDOR_TUNING_CNTRL0_NUM_TUNING_ITERATIONS, 13, TRIES_40, TRIES_64, TRIES_128, TRIES_192, TRIES_256, RESERVED5, RESERVED6, RESERVED7);
|
||||
DEFINE_SD_REG_BIT_ENUM(VENDOR_TUNING_CNTRL0_TAP_VALUE_UPDATED_BY_HW, 17, NOT_UPDATED_BY_HW, UPDATED_BY_HW);
|
||||
|
||||
DEFINE_SD_REG(SDMEMCOMPPADCTRL_SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL, 0, 4);
|
||||
DEFINE_SD_REG(SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD, 31, 1);
|
||||
|
||||
DEFINE_SD_REG(AUTO_CAL_CONFIG_AUTO_CAL_PU_OFFSET, 0, 7);
|
||||
DEFINE_SD_REG(AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET, 8, 7);
|
||||
DEFINE_SD_REG_BIT_ENUM(AUTO_CAL_CONFIG_AUTO_CAL_ENABLE, 29, DISABLED, ENABLED);
|
||||
DEFINE_SD_REG_BIT_ENUM(AUTO_CAL_CONFIG_AUTO_CAL_START, 31, DISABLED, ENABLED);
|
||||
|
||||
DEFINE_SD_REG(AUTO_CAL_STATUS_AUTO_CAL_PULLUP, 0, 7);
|
||||
DEFINE_SD_REG_BIT_ENUM(AUTO_CAL_STATUS_AUTO_CAL_ACTIVE, 31, INACTIVE, ACTIVE);
|
||||
|
||||
DEFINE_SD_REG_BIT_ENUM(IO_SPARE_SPARE_OUT_3, 19, TWO_CYCLE_DELAY, ONE_CYCLE_DELAY);
|
||||
|
||||
namespace {
|
||||
|
||||
constexpr inline u32 TuningCommandTimeoutMilliSeconds = 5;
|
||||
|
||||
constexpr void GetDividerSetting(u32 *out_target_clock_frequency_khz, u16 *out_x, SpeedMode speed_mode) {
|
||||
switch (speed_mode) {
|
||||
case SpeedMode_MmcIdentification:
|
||||
*out_target_clock_frequency_khz = 26000;
|
||||
*out_x = 66;
|
||||
break;
|
||||
case SpeedMode_MmcLegacySpeed:
|
||||
*out_target_clock_frequency_khz = 26000;
|
||||
*out_x = 1;
|
||||
break;
|
||||
case SpeedMode_MmcHighSpeed:
|
||||
*out_target_clock_frequency_khz = 52000;
|
||||
*out_x = 1;
|
||||
break;
|
||||
case SpeedMode_MmcHs200:
|
||||
*out_target_clock_frequency_khz = 200000;
|
||||
*out_x = 1;
|
||||
break;
|
||||
case SpeedMode_MmcHs400:
|
||||
*out_target_clock_frequency_khz = 200000;
|
||||
*out_x = 1;
|
||||
break;
|
||||
case SpeedMode_SdCardIdentification:
|
||||
*out_target_clock_frequency_khz = 25000;
|
||||
*out_x = 64;
|
||||
break;
|
||||
case SpeedMode_SdCardDefaultSpeed:
|
||||
*out_target_clock_frequency_khz = 25000;
|
||||
*out_x = 1;
|
||||
break;
|
||||
case SpeedMode_SdCardHighSpeed:
|
||||
*out_target_clock_frequency_khz = 50000;
|
||||
*out_x = 1;
|
||||
break;
|
||||
case SpeedMode_SdCardSdr12:
|
||||
*out_target_clock_frequency_khz = 25000;
|
||||
*out_x = 1;
|
||||
break;
|
||||
case SpeedMode_SdCardSdr50:
|
||||
*out_target_clock_frequency_khz = 100000;
|
||||
*out_x = 1;
|
||||
break;
|
||||
case SpeedMode_SdCardSdr104:
|
||||
*out_target_clock_frequency_khz = 200000;
|
||||
*out_x = 1;
|
||||
break;
|
||||
case SpeedMode_GcAsicFpgaSpeed:
|
||||
*out_target_clock_frequency_khz = 40800;
|
||||
*out_x = 1;
|
||||
break;
|
||||
case SpeedMode_GcAsicSpeed:
|
||||
*out_target_clock_frequency_khz = 200000;
|
||||
*out_x = 2;
|
||||
break;
|
||||
case SpeedMode_SdCardSdr25:
|
||||
case SpeedMode_SdCardDdr50:
|
||||
AMS_UNREACHABLE_DEFAULT_CASE();
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
namespace {
|
||||
|
||||
#if defined(AMS_SDMMC_THREAD_SAFE)
|
||||
constinit os::Mutex g_soc_mutex(false);
|
||||
|
||||
#define AMS_SDMMC_LOCK_SOC_MUTEX() std::scoped_lock lk(g_soc_mutex)
|
||||
|
||||
#else
|
||||
|
||||
#define AMS_SDMMC_LOCK_SOC_MUTEX()
|
||||
|
||||
#endif
|
||||
|
||||
constinit bool g_determined_soc = false;
|
||||
constinit bool g_is_soc_mariko = false;
|
||||
|
||||
}
|
||||
|
||||
bool IsSocMariko() {
|
||||
if (!g_determined_soc) {
|
||||
/* Ensure we have exclusive access to the soc variables. */
|
||||
AMS_SDMMC_LOCK_SOC_MUTEX();
|
||||
|
||||
/* Check the SocType. */
|
||||
#if defined(ATMOSPHERE_IS_EXOSPHERE)
|
||||
{
|
||||
g_is_soc_mariko = fuse::GetSocType() == fuse::SocType_Mariko;
|
||||
}
|
||||
#elif defined(ATMOSPHERE_IS_MESOSPHERE)
|
||||
{
|
||||
MESOSPHERE_TODO("Detect mariko via KSystemControl call?");
|
||||
}
|
||||
#elif defined(ATMOSPHERE_IS_STRATOSPHERE)
|
||||
{
|
||||
/* Connect to spl for the duration of our check. */
|
||||
spl::Initialize();
|
||||
ON_SCOPE_EXIT { spl::Finalize(); };
|
||||
|
||||
g_is_soc_mariko = spl::GetSocType() == spl::SocType_Mariko;
|
||||
}
|
||||
#else
|
||||
#error "Unknown execution context for ams::sdmmc::impl::IsSocMariko"
|
||||
#endif
|
||||
|
||||
/* Note that we determined the soc. */
|
||||
g_determined_soc = true;
|
||||
}
|
||||
|
||||
return g_is_soc_mariko;
|
||||
}
|
||||
|
||||
void SdmmcController::ReleaseReset(SpeedMode speed_mode) {
|
||||
/* Get the clock reset module. */
|
||||
const auto module = this->GetClockResetModule();
|
||||
|
||||
/* If the module is available, disable clock. */
|
||||
if (ClockResetController::IsAvailable(module)) {
|
||||
SdHostStandardController::DisableDeviceClock();
|
||||
SdHostStandardController::EnsureControl();
|
||||
}
|
||||
|
||||
/* Get the correct divider setting for the speed mode. */
|
||||
u32 target_clock_frequency_khz;
|
||||
u16 x;
|
||||
GetDividerSetting(std::addressof(target_clock_frequency_khz), std::addressof(x), speed_mode);
|
||||
|
||||
/* Release reset. */
|
||||
ClockResetController::ReleaseReset(module, target_clock_frequency_khz);
|
||||
}
|
||||
|
||||
void SdmmcController::AssertReset() {
|
||||
return ClockResetController::AssertReset(this->GetClockResetModule());
|
||||
}
|
||||
|
||||
Result SdmmcController::StartupCore(BusPower bus_power) {
|
||||
/* Set schmitt trigger. */
|
||||
this->SetSchmittTrigger(bus_power);
|
||||
|
||||
/* Select one-cycle delay version of cmd_oen. */
|
||||
reg::ReadWrite(this->sdmmc_registers->io_spare, SD_REG_BITS_ENUM(IO_SPARE_SPARE_OUT_3, ONE_CYCLE_DELAY));
|
||||
|
||||
/* Select regulated reference voltage for trimmer and DLL supply. */
|
||||
reg::ReadWrite(this->sdmmc_registers->vendor_io_trim_cntrl, SD_REG_BITS_VALUE(VENDOR_IO_TRIM_CNTRL_SEL_VREG, 0));
|
||||
|
||||
/* Configure outbound tap value. */
|
||||
reg::ReadWrite(this->sdmmc_registers->vendor_clock_cntrl, SD_REG_BITS_VALUE(VENDOR_CLOCK_CNTRL_TRIM_VAL, this->GetOutboundTapValue()));
|
||||
|
||||
/* Configure SPI_MODE_CLKEN_OVERRIDE. */
|
||||
reg::ReadWrite(this->sdmmc_registers->vendor_clock_cntrl, SD_REG_BITS_ENUM(VENDOR_CLOCK_CNTRL_SPI_MODE_CLKEN_OVERRIDE, NORMAL));
|
||||
|
||||
/* Set slew codes. */
|
||||
this->SetSlewCodes();
|
||||
|
||||
/* Set vref sel. */
|
||||
reg::ReadWrite(this->sdmmc_registers->sdmemcomppadctrl, SD_REG_BITS_VALUE(SDMEMCOMPPADCTRL_SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL, this->GetOutboundTapValue()));
|
||||
|
||||
/* Perform drive strength calibration at the new power. */
|
||||
this->SetDriveCodeOffsets(bus_power);
|
||||
this->CalibrateDriveStrength(bus_power);
|
||||
|
||||
/* Enable internal clock. */
|
||||
R_TRY(SdHostStandardController::EnableInternalClock());
|
||||
|
||||
return ResultSuccess();
|
||||
}
|
||||
|
||||
Result SdmmcController::SetClockTrimmer(SpeedMode speed_mode, u8 tap_value) {
|
||||
/* If speed mode is Hs400, set the dqs trim value. */
|
||||
if (speed_mode == SpeedMode_MmcHs400) {
|
||||
reg::ReadWrite(this->sdmmc_registers->vendor_cap_overrides, SD_REG_BITS_VALUE(VENDOR_CAP_OVERRIDES_DQS_TRIM_VAL, 40));
|
||||
}
|
||||
|
||||
/* Configure tap value as updated by software. */
|
||||
reg::ReadWrite(this->sdmmc_registers->vendor_tuning_cntrl0, SD_REG_BITS_ENUM(VENDOR_TUNING_CNTRL0_TAP_VALUE_UPDATED_BY_HW, NOT_UPDATED_BY_HW));
|
||||
|
||||
/* Set the inbound tap value. */
|
||||
reg::ReadWrite(this->sdmmc_registers->vendor_clock_cntrl, SD_REG_BITS_VALUE(VENDOR_CLOCK_CNTRL_TAP_VAL, tap_value));
|
||||
|
||||
/* Reset the cmd/dat line. */
|
||||
R_TRY(SdHostStandardController::ResetCmdDatLine());
|
||||
|
||||
return ResultSuccess();
|
||||
}
|
||||
|
||||
u8 SdmmcController::GetCurrentTapValue() {
|
||||
return static_cast<u8>(reg::GetValue(this->sdmmc_registers->vendor_clock_cntrl, SD_REG_BITS_MASK(VENDOR_CLOCK_CNTRL_TAP_VAL)));
|
||||
}
|
||||
|
||||
Result SdmmcController::CalibrateDll() {
|
||||
/* Check if we need to temporarily re-enable the device clock. */
|
||||
const bool clock_disabled = reg::HasValue(this->sdmmc_registers->sd_host_standard_registers.clock_control, SD_REG_BITS_ENUM(CLOCK_CONTROL_SD_CLOCK_ENABLE, DISABLE));
|
||||
|
||||
/* Ensure that the clock is enabled for the period we're using it. */
|
||||
if (clock_disabled) {
|
||||
/* Turn on the clock. */
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.clock_control, SD_REG_BITS_ENUM(CLOCK_CONTROL_SD_CLOCK_ENABLE, ENABLE));
|
||||
}
|
||||
ON_SCOPE_EXIT { if (clock_disabled) { reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.clock_control, SD_REG_BITS_ENUM(CLOCK_CONTROL_SD_CLOCK_ENABLE, DISABLE)); } };
|
||||
|
||||
/* Begin calibration. */
|
||||
reg::ReadWrite(this->sdmmc_registers->vendor_dllcal_cfg, SD_REG_BITS_ENUM(VENDOR_DLLCAL_CFG_CALIBRATE, ENABLE));
|
||||
|
||||
/* Wait up to 5ms for calibration to begin. */
|
||||
{
|
||||
ManualTimer timer(5);
|
||||
while (true) {
|
||||
/* If calibration is done, we're done. */
|
||||
if (!reg::HasValue(this->sdmmc_registers->vendor_dllcal_cfg, SD_REG_BITS_ENUM(VENDOR_DLLCAL_CFG_CALIBRATE, ENABLE))) {
|
||||
break;
|
||||
}
|
||||
|
||||
/* Otherwise, check if we've timed out. */
|
||||
R_UNLESS((timer.Update()), sdmmc::ResultSdmmcDllCalibrationSoftwareTimeout());
|
||||
}
|
||||
}
|
||||
|
||||
/* Wait up to 10ms for calibration to complete. */
|
||||
{
|
||||
ManualTimer timer(10);
|
||||
while (true) {
|
||||
/* If calibration is done, we're done. */
|
||||
if (reg::HasValue(this->sdmmc_registers->vendor_dllcal_cfg_sta, SD_REG_BITS_ENUM(VENDOR_DLLCAL_CFG_STA_DLL_CAL_ACTIVE, DONE))) {
|
||||
break;
|
||||
}
|
||||
|
||||
/* Otherwise, check if we've timed out. */
|
||||
R_UNLESS((timer.Update()), sdmmc::ResultSdmmcDllApplicationSoftwareTimeout());
|
||||
}
|
||||
}
|
||||
|
||||
return ResultSuccess();
|
||||
}
|
||||
|
||||
Result SdmmcController::SetSpeedModeWithTapValue(SpeedMode speed_mode, u8 tap_value) {
|
||||
/* Check if we need to temporarily disable the device clock. */
|
||||
const bool clock_enabled = reg::HasValue(this->sdmmc_registers->sd_host_standard_registers.clock_control, SD_REG_BITS_ENUM(CLOCK_CONTROL_SD_CLOCK_ENABLE, ENABLE));
|
||||
|
||||
/* Ensure that the clock is disabled for the period we're using it. */
|
||||
if (clock_enabled) {
|
||||
/* Turn off the clock. */
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.clock_control, SD_REG_BITS_ENUM(CLOCK_CONTROL_SD_CLOCK_ENABLE, DISABLE));
|
||||
}
|
||||
|
||||
/* Set clock trimmer. */
|
||||
/* NOTE: Nintendo does not re-enable the clock if this fails... */
|
||||
R_TRY(this->SetClockTrimmer(speed_mode, tap_value));
|
||||
|
||||
/* Configure for the desired speed mode. */
|
||||
switch (speed_mode) {
|
||||
case SpeedMode_MmcIdentification:
|
||||
case SpeedMode_SdCardIdentification:
|
||||
case SpeedMode_MmcLegacySpeed:
|
||||
case SpeedMode_SdCardDefaultSpeed:
|
||||
/* Set as normal speed, 3.3V. */
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.host_control, SD_REG_BITS_ENUM(HOST_CONTROL_HIGH_SPEED_ENABLE, NORMAL_SPEED));
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.host_control2, SD_REG_BITS_ENUM(HOST_CONTROL2_1_8V_SIGNALING_ENABLE, 3_3V_SIGNALING));
|
||||
break;
|
||||
case SpeedMode_MmcHighSpeed:
|
||||
case SpeedMode_SdCardHighSpeed:
|
||||
/* Set as high speed, 3.3V. */
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.host_control, SD_REG_BITS_ENUM(HOST_CONTROL_HIGH_SPEED_ENABLE, HIGH_SPEED));
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.host_control2, SD_REG_BITS_ENUM(HOST_CONTROL2_1_8V_SIGNALING_ENABLE, 3_3V_SIGNALING));
|
||||
break;
|
||||
case SpeedMode_MmcHs200:
|
||||
/* Set as HS200, 1.8V. */
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.host_control2, SD_REG_BITS_ENUM(HOST_CONTROL2_UHS_MODE_SELECT, HS200));
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.host_control2, SD_REG_BITS_ENUM(HOST_CONTROL2_1_8V_SIGNALING_ENABLE, 1_8V_SIGNALING));
|
||||
break;
|
||||
case SpeedMode_MmcHs400:
|
||||
/* Set as HS400, 1.8V. */
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.host_control2, SD_REG_BITS_ENUM(HOST_CONTROL2_UHS_MODE_SELECT, HS400));
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.host_control2, SD_REG_BITS_ENUM(HOST_CONTROL2_1_8V_SIGNALING_ENABLE, 1_8V_SIGNALING));
|
||||
break;
|
||||
case SpeedMode_SdCardSdr12:
|
||||
/* Set as SDR12, 1.8V. */
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.host_control2, SD_REG_BITS_ENUM(HOST_CONTROL2_UHS_MODE_SELECT, SDR12));
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.host_control2, SD_REG_BITS_ENUM(HOST_CONTROL2_1_8V_SIGNALING_ENABLE, 1_8V_SIGNALING));
|
||||
break;
|
||||
case SpeedMode_SdCardSdr50:
|
||||
case SpeedMode_SdCardSdr104:
|
||||
case SpeedMode_GcAsicFpgaSpeed:
|
||||
case SpeedMode_GcAsicSpeed:
|
||||
/* Set as SDR104, 1.8V. */
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.host_control2, SD_REG_BITS_ENUM(HOST_CONTROL2_UHS_MODE_SELECT, SDR104));
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.host_control2, SD_REG_BITS_ENUM(HOST_CONTROL2_1_8V_SIGNALING_ENABLE, 1_8V_SIGNALING));
|
||||
break;
|
||||
AMS_UNREACHABLE_DEFAULT_CASE();
|
||||
}
|
||||
SdHostStandardController::EnsureControl();
|
||||
|
||||
/* Get the divider setting. */
|
||||
u32 target_source_clock_frequency_khz;
|
||||
u16 x;
|
||||
GetDividerSetting(std::addressof(target_source_clock_frequency_khz), std::addressof(x), speed_mode);
|
||||
|
||||
/* Set the clock frequency. */
|
||||
u32 actual_source_clock_frequency_khz;
|
||||
ClockResetController::SetClockFrequencyKHz(std::addressof(actual_source_clock_frequency_khz), this->GetClockResetModule(), target_source_clock_frequency_khz);
|
||||
|
||||
/* Set the device clock frequency. */
|
||||
const u32 actual_device_clock_frequency_khz = util::DivideUp(actual_source_clock_frequency_khz, x);
|
||||
SdHostStandardController::SetDeviceClockFrequencyKHz(actual_device_clock_frequency_khz);
|
||||
|
||||
/* Check that the divider is correct. */
|
||||
AMS_ABORT_UNLESS((x == 1) || util::IsAligned(x, 2));
|
||||
|
||||
/* Write the divider val to clock control. */
|
||||
const u16 n = x / 2;
|
||||
const u16 upper_n = n >> 8;
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.clock_control, SD_REG_BITS_VALUE(CLOCK_CONTROL_SDCLK_FREQUENCY_SELECT, n),
|
||||
SD_REG_BITS_VALUE(CLOCK_CONTROL_UPPER_BITS_OF_SDCLK_FREQUENCY_SELECT, upper_n));
|
||||
|
||||
/* Re-enable the clock, if we should. */
|
||||
if (clock_enabled) {
|
||||
/* Turn on the clock. */
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.clock_control, SD_REG_BITS_ENUM(CLOCK_CONTROL_SD_CLOCK_ENABLE, ENABLE));
|
||||
}
|
||||
|
||||
/* If speed mode is Hs400, calibrate dll. */
|
||||
if (speed_mode == SpeedMode_MmcHs400) {
|
||||
R_TRY(this->CalibrateDll());
|
||||
}
|
||||
|
||||
/* Set the current speed mode. */
|
||||
this->current_speed_mode = speed_mode;
|
||||
|
||||
return ResultSuccess();
|
||||
}
|
||||
|
||||
Result SdmmcController::IssueTuningCommand(u32 command_index) {
|
||||
/* Check that we're not power saving enable. */
|
||||
AMS_ABORT_UNLESS(!SdHostStandardController::IsPowerSavingEnable());
|
||||
|
||||
/* Wait until command inhibit is done. */
|
||||
R_TRY(SdHostStandardController::WaitWhileCommandInhibit(true));
|
||||
|
||||
/* Set transfer for tuning. */
|
||||
SdHostStandardController::SetTransferForTuning();
|
||||
|
||||
/* If necessary, clear interrupt and enable buffer read ready signal. */
|
||||
#if defined(AMS_SDMMC_USE_OS_EVENTS)
|
||||
{
|
||||
this->ClearInterrupt();
|
||||
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.normal_signal_enable, SD_REG_BITS_ENUM(NORMAL_INTERRUPT_BUFFER_READ_READY, ENABLED));
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Set the buffer read ready enable, and read status to ensure it takes. */
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.normal_int_enable, SD_REG_BITS_ENUM(NORMAL_INTERRUPT_BUFFER_READ_READY, ENABLED));
|
||||
reg::Read(this->sdmmc_registers->sd_host_standard_registers.normal_int_status);
|
||||
|
||||
/* Issue command with clock disabled. */
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.clock_control, SD_REG_BITS_ENUM(CLOCK_CONTROL_SD_CLOCK_ENABLE, DISABLE));
|
||||
{
|
||||
SdHostStandardController::SetCommandForTuning(command_index);
|
||||
|
||||
SdHostStandardController::EnsureControl();
|
||||
WaitMicroSeconds(1);
|
||||
SdHostStandardController::AbortTransaction();
|
||||
}
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.clock_control, SD_REG_BITS_ENUM(CLOCK_CONTROL_SD_CLOCK_ENABLE, ENABLE));
|
||||
|
||||
/* When we're done waiting, ensure that we clean up appropriately. */
|
||||
ON_SCOPE_EXIT {
|
||||
/* Clear the buffer read ready signal, if we should. */
|
||||
#if defined(AMS_SDMMC_USE_OS_EVENTS)
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.normal_signal_enable, SD_REG_BITS_ENUM(NORMAL_INTERRUPT_BUFFER_READ_READY, MASKED));
|
||||
#endif
|
||||
|
||||
/* Clear the buffer read ready enable. */
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.normal_int_enable, SD_REG_BITS_ENUM(NORMAL_INTERRUPT_BUFFER_READ_READY, MASKED));
|
||||
|
||||
/* Wait 8 clocks to ensure configuration takes. */
|
||||
SdHostStandardController::EnsureControl();
|
||||
WaitClocks(8, SdHostStandardController::GetDeviceClockFrequencyKHz());
|
||||
};
|
||||
|
||||
/* Wait for the command to finish. */
|
||||
#if defined(AMS_SDMMC_USE_OS_EVENTS)
|
||||
{
|
||||
const auto result = SdHostStandardController::WaitInterrupt(TuningCommandTimeoutMilliSeconds);
|
||||
if (R_SUCCEEDED(result)) {
|
||||
/* If we succeeded, clear the interrupt. */
|
||||
reg::Write(this->sdmmc_registers->sd_host_standard_registers.normal_int_status, SD_REG_BITS_ENUM(NORMAL_INTERRUPT_BUFFER_READ_READY, ENABLED));
|
||||
this->ClearInterrupt();
|
||||
return ResultSuccess();
|
||||
} else if (sdmmc::ResultWaitInterruptSoftwareTimeout::Includes(result)) {
|
||||
SdHostStandardController::AbortTransaction();
|
||||
return sdmmc::ResultIssueTuningCommandSoftwareTimeout();
|
||||
} else {
|
||||
return result;
|
||||
}
|
||||
}
|
||||
#else
|
||||
{
|
||||
SdHostStandardController::EnsureControl();
|
||||
ManualTimer timer(TuningCommandTimeoutMilliSeconds);
|
||||
while (true) {
|
||||
/* Check if we received the interrupt. */
|
||||
if (reg::HasValue(this->sdmmc_registers->sd_host_standard_registers.normal_int_status, SD_REG_BITS_ENUM(NORMAL_INTERRUPT_BUFFER_READ_READY, ENABLED))) {
|
||||
/* If we did, acknowledge it. */
|
||||
reg::Write(this->sdmmc_registers->sd_host_standard_registers.normal_int_status, SD_REG_BITS_ENUM(NORMAL_INTERRUPT_BUFFER_READ_READY, ENABLED));
|
||||
return ResultSuccess();
|
||||
}
|
||||
|
||||
/* Otherwise, check if we timed out. */
|
||||
if (!timer.Update()) {
|
||||
SdHostStandardController::AbortTransaction();
|
||||
return sdmmc::ResultIssueTuningCommandSoftwareTimeout();
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void SdmmcController::SetDriveCodeOffsets(BusPower bus_power) {
|
||||
/* Get the offsets. */
|
||||
u8 pd, pu;
|
||||
this->GetAutoCalOffsets(std::addressof(pd), std::addressof(pu), bus_power);
|
||||
|
||||
/* Set the offsets. */
|
||||
reg::ReadWrite(this->sdmmc_registers->auto_cal_config, SD_REG_BITS_VALUE(AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET, pd),
|
||||
SD_REG_BITS_VALUE(AUTO_CAL_CONFIG_AUTO_CAL_PU_OFFSET, pu));
|
||||
}
|
||||
|
||||
void SdmmcController::CalibrateDriveStrength(BusPower bus_power) {
|
||||
/* Reset drive strength calibration status. */
|
||||
this->drive_strength_calibration_status = sdmmc::ResultDriveStrengthCalibrationNotCompleted();
|
||||
|
||||
/* Check if we need to temporarily disable the device clock. */
|
||||
const bool clock_enabled = reg::HasValue(this->sdmmc_registers->sd_host_standard_registers.clock_control, SD_REG_BITS_ENUM(CLOCK_CONTROL_SD_CLOCK_ENABLE, ENABLE));
|
||||
|
||||
/* Ensure that the clock is disabled for the period we're using it. */
|
||||
if (clock_enabled) {
|
||||
/* Turn off the clock. */
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.clock_control, SD_REG_BITS_ENUM(CLOCK_CONTROL_SD_CLOCK_ENABLE, DISABLE));
|
||||
}
|
||||
|
||||
/* Calibrate with the clock disabled. */
|
||||
{
|
||||
/* Set SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD. */
|
||||
if (reg::HasValue(this->sdmmc_registers->sdmemcomppadctrl, SD_REG_BITS_VALUE(SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD, 0))) {
|
||||
reg::ReadWrite(this->sdmmc_registers->sdmemcomppadctrl, SD_REG_BITS_VALUE(SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD, 1));
|
||||
SdHostStandardController::EnsureControl();
|
||||
WaitMicroSeconds(1);
|
||||
}
|
||||
|
||||
/* Calibrate with SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD set. */
|
||||
{
|
||||
/* Begin autocal. */
|
||||
reg::ReadWrite(this->sdmmc_registers->auto_cal_config, SD_REG_BITS_ENUM(AUTO_CAL_CONFIG_AUTO_CAL_START, ENABLED),
|
||||
SD_REG_BITS_ENUM(AUTO_CAL_CONFIG_AUTO_CAL_ENABLE, ENABLED));
|
||||
SdHostStandardController::EnsureControl();
|
||||
WaitMicroSeconds(2);
|
||||
|
||||
/* Wait up to 10ms for auto cal to complete. */
|
||||
ManualTimer timer(10);
|
||||
while (true) {
|
||||
/* Check if auto cal is inactive. */
|
||||
if (reg::HasValue(this->sdmmc_registers->auto_cal_status, SD_REG_BITS_ENUM(AUTO_CAL_STATUS_AUTO_CAL_ACTIVE, INACTIVE))) {
|
||||
/* Check the pullup status. */
|
||||
const u32 pullup = (reg::GetValue(this->sdmmc_registers->auto_cal_status, SD_REG_BITS_MASK(AUTO_CAL_STATUS_AUTO_CAL_PULLUP))) & 0x1F;
|
||||
if (pullup == 0x1F) {
|
||||
this->drive_strength_calibration_status = sdmmc::ResultSdmmcCompShortToGnd();
|
||||
}
|
||||
if (pullup == 0) {
|
||||
this->drive_strength_calibration_status = sdmmc::ResultSdmmcCompOpen();
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
/* Otherwise, check if we've timed out. */
|
||||
if (!timer.Update()) {
|
||||
this->drive_strength_calibration_status = sdmmc::ResultDriveStrengthCalibrationSoftwareTimeout();
|
||||
|
||||
this->SetDriveStrengthToDefaultValues(bus_power);
|
||||
reg::ReadWrite(this->sdmmc_registers->auto_cal_config, SD_REG_BITS_ENUM(AUTO_CAL_CONFIG_AUTO_CAL_ENABLE, DISABLED));
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD. */
|
||||
reg::ReadWrite(this->sdmmc_registers->sdmemcomppadctrl, SD_REG_BITS_VALUE(SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD, 0));
|
||||
}
|
||||
|
||||
/* Re-enable the clock, if we should. */
|
||||
if (clock_enabled) {
|
||||
/* Turn on the clock. */
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.clock_control, SD_REG_BITS_ENUM(CLOCK_CONTROL_SD_CLOCK_ENABLE, ENABLE));
|
||||
}
|
||||
|
||||
/* If calibration didn't receive a replacement error, set internal state to success. */
|
||||
if (sdmmc::ResultDriveStrengthCalibrationNotCompleted::Includes(this->drive_strength_calibration_status)) {
|
||||
this->drive_strength_calibration_status = ResultSuccess();
|
||||
}
|
||||
}
|
||||
|
||||
Result SdmmcController::Startup(BusPower bus_power, BusWidth bus_width, SpeedMode speed_mode, bool power_saving_enable) {
|
||||
/* Verify that we're awake. */
|
||||
AMS_ABORT_UNLESS(this->is_awake);
|
||||
|
||||
/* Release the controller from reset. */
|
||||
this->ReleaseReset(speed_mode);
|
||||
|
||||
/* Mark that we're not shutdown. */
|
||||
this->is_shutdown = false;
|
||||
|
||||
/* Power on the controller. */
|
||||
R_TRY(this->PowerOn(bus_power));
|
||||
|
||||
/* Start up for the specific power. */
|
||||
R_TRY(this->StartupCore(bus_power));
|
||||
|
||||
/* Set our current power/width/speed. */
|
||||
SdHostStandardController::SetBusWidth(bus_width);
|
||||
SdHostStandardController::SetBusPower(bus_power);
|
||||
R_TRY(this->SetSpeedMode(speed_mode));
|
||||
this->SetPowerSaving(power_saving_enable);
|
||||
|
||||
/* Enable clock to the device. */
|
||||
SdHostStandardController::EnableDeviceClock();
|
||||
|
||||
/* Ensure that we can control the device. */
|
||||
SdHostStandardController::EnsureControl();
|
||||
|
||||
return ResultSuccess();
|
||||
}
|
||||
|
||||
void SdmmcController::Shutdown() {
|
||||
/* If we're already shut down, there's nothing to do. */
|
||||
if (this->is_shutdown) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* If we're currently awake, we need to disable clock/power. */
|
||||
if (this->is_awake) {
|
||||
SdHostStandardController::DisableDeviceClock();
|
||||
SdHostStandardController::SetBusPower(BusPower_Off);
|
||||
SdHostStandardController::EnsureControl();
|
||||
}
|
||||
|
||||
/* Power off. */
|
||||
this->PowerOff();
|
||||
|
||||
/* If awake, assert reset. */
|
||||
if (this->is_awake) {
|
||||
this->AssertReset();
|
||||
}
|
||||
|
||||
/* Mark that we're shutdown. */
|
||||
this->is_shutdown = true;
|
||||
}
|
||||
|
||||
void SdmmcController::PutToSleep() {
|
||||
/* If we're already shut down or asleep, there's nothing to do. */
|
||||
if (this->is_shutdown || !this->is_awake) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* Save values before sleep. */
|
||||
this->bus_power_before_sleep = SdHostStandardController::GetBusPower();
|
||||
this->bus_width_before_sleep = SdHostStandardController::GetBusWidth();
|
||||
this->speed_mode_before_sleep = this->current_speed_mode;
|
||||
this->tap_value_before_sleep = this->GetCurrentTapValue();
|
||||
this->is_powersaving_enable_before_sleep = SdHostStandardController::IsPowerSavingEnable();
|
||||
|
||||
/* Disable clock/power to the device. */
|
||||
SdHostStandardController::DisableDeviceClock();
|
||||
SdHostStandardController::SetBusPower(BusPower_Off);
|
||||
SdHostStandardController::EnsureControl();
|
||||
|
||||
/* Assert reset. */
|
||||
this->AssertReset();
|
||||
|
||||
/* Mark that we're asleep. */
|
||||
this->is_awake = false;
|
||||
}
|
||||
|
||||
Result SdmmcController::Awaken() {
|
||||
/* If we're shut down, or if we're awake already, there's nothing to do. */
|
||||
R_SUCCEED_IF(this->is_shutdown);
|
||||
R_SUCCEED_IF(this->is_awake);
|
||||
|
||||
/* Mark that we're awake. */
|
||||
this->is_awake = true;
|
||||
|
||||
/* Clear pad parked status. */
|
||||
this->ClearPadParked();
|
||||
|
||||
/* Release reset. */
|
||||
this->ReleaseReset(this->speed_mode_before_sleep);
|
||||
|
||||
/* Start up for the correct power. */
|
||||
R_TRY(this->StartupCore(this->bus_power_before_sleep));
|
||||
|
||||
/* Configure values to what they were before sleep. */
|
||||
SdHostStandardController::SetBusWidth(this->bus_width_before_sleep);
|
||||
SdHostStandardController::SetBusPower(this->bus_power_before_sleep);
|
||||
R_TRY(this->SetSpeedModeWithTapValue(this->speed_mode_before_sleep, this->tap_value_before_sleep));
|
||||
this->SetPowerSaving(this->is_powersaving_enable_before_sleep);
|
||||
|
||||
/* Enable clock to the device. */
|
||||
SdHostStandardController::EnableDeviceClock();
|
||||
SdHostStandardController::EnsureControl();
|
||||
|
||||
return ResultSuccess();
|
||||
}
|
||||
|
||||
Result SdmmcController::SwitchToSdr12() {
|
||||
/* Disable clock. */
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.clock_control, SD_REG_BITS_ENUM(CLOCK_CONTROL_SD_CLOCK_ENABLE, DISABLE));
|
||||
|
||||
/* Check that the dat lines are all low. */
|
||||
R_UNLESS(reg::HasValue(this->sdmmc_registers->sd_host_standard_registers.present_state, SD_REG_BITS_VALUE(PRESENT_STATE_DAT0_3_LINE_SIGNAL_LEVEL, 0b0000)), sdmmc::ResultSdCardNotReadyToVoltageSwitch());
|
||||
|
||||
/* Set voltage to 1.8V. */
|
||||
SdHostStandardController::EnsureControl();
|
||||
R_TRY(this->LowerBusPower());
|
||||
this->SetSchmittTrigger(BusPower_1_8V);
|
||||
|
||||
/* Perform drive strength calibration at the new power. */
|
||||
this->SetDriveCodeOffsets(BusPower_1_8V);
|
||||
this->CalibrateDriveStrength(BusPower_1_8V);
|
||||
|
||||
/* Set the bus power in standard controller. */
|
||||
SdHostStandardController::SetBusPower(BusPower_1_8V);
|
||||
|
||||
/* Wait up to 5ms for the switch to take. */
|
||||
SdHostStandardController::EnsureControl();
|
||||
WaitMicroSeconds(5000);
|
||||
|
||||
/* Check that we switched to 1.8V. */
|
||||
R_UNLESS(reg::HasValue(this->sdmmc_registers->sd_host_standard_registers.host_control2, SD_REG_BITS_ENUM(HOST_CONTROL2_1_8V_SIGNALING_ENABLE, 1_8V_SIGNALING)), sdmmc::ResultSdHostStandardFailSwitchTo1_8V());
|
||||
|
||||
/* Enable clock, and wait 1ms. */
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.clock_control, SD_REG_BITS_ENUM(CLOCK_CONTROL_SD_CLOCK_ENABLE, DISABLE));
|
||||
SdHostStandardController::EnsureControl();
|
||||
WaitMicroSeconds(1000);
|
||||
|
||||
/* Check that the dat lines are all high. */
|
||||
R_UNLESS(reg::HasValue(this->sdmmc_registers->sd_host_standard_registers.present_state, SD_REG_BITS_VALUE(PRESENT_STATE_DAT0_3_LINE_SIGNAL_LEVEL, 0b1111)), sdmmc::ResultSdCardNotCompleteVoltageSwitch());
|
||||
|
||||
return ResultSuccess();
|
||||
}
|
||||
|
||||
Result SdmmcController::SetSpeedMode(SpeedMode speed_mode) {
|
||||
/* Get the tap value. */
|
||||
u8 tap_value;
|
||||
if (speed_mode == SpeedMode_MmcHs400) {
|
||||
AMS_ABORT_UNLESS(this->is_valid_tap_value_for_hs_400);
|
||||
tap_value = this->tap_value_for_hs_400;
|
||||
} else {
|
||||
tap_value = this->GetDefaultInboundTapValue();
|
||||
}
|
||||
|
||||
/* Set the speed mode. */
|
||||
R_TRY(this->SetSpeedModeWithTapValue(speed_mode, tap_value));
|
||||
|
||||
return ResultSuccess();
|
||||
}
|
||||
|
||||
void SdmmcController::SetPowerSaving(bool en) {
|
||||
/* If necessary, calibrate the drive strength. */
|
||||
if (this->IsNeedPeriodicDriveStrengthCalibration() && !en && SdHostStandardController::IsDeviceClockEnable()) {
|
||||
this->CalibrateDriveStrength(SdHostStandardController::GetBusPower());
|
||||
}
|
||||
|
||||
return SdHostStandardController::SetPowerSaving(en);
|
||||
}
|
||||
|
||||
void SdmmcController::EnableDeviceClock() {
|
||||
/* If necessary, calibrate the drive strength. */
|
||||
if (this->IsNeedPeriodicDriveStrengthCalibration() && !SdHostStandardController::IsPowerSavingEnable()) {
|
||||
this->CalibrateDriveStrength(SdHostStandardController::GetBusPower());
|
||||
}
|
||||
|
||||
return SdHostStandardController::EnableDeviceClock();
|
||||
}
|
||||
|
||||
Result SdmmcController::IssueCommand(const Command *command, TransferData *xfer_data, u32 *out_num_transferred_blocks) {
|
||||
/* If necessary, calibrate the drive strength. */
|
||||
if (this->IsNeedPeriodicDriveStrengthCalibration() && SdHostStandardController::IsPowerSavingEnable()) {
|
||||
this->CalibrateDriveStrength(SdHostStandardController::GetBusPower());
|
||||
}
|
||||
|
||||
return SdHostStandardController::IssueCommand(command, xfer_data, out_num_transferred_blocks);
|
||||
}
|
||||
|
||||
Result SdmmcController::IssueStopTransmissionCommand(u32 *out_response) {
|
||||
/* If necessary, calibrate the drive strength. */
|
||||
if (this->IsNeedPeriodicDriveStrengthCalibration() && SdHostStandardController::IsPowerSavingEnable()) {
|
||||
this->CalibrateDriveStrength(SdHostStandardController::GetBusPower());
|
||||
}
|
||||
|
||||
return SdHostStandardController::IssueStopTransmissionCommand(out_response);
|
||||
}
|
||||
|
||||
Result SdmmcController::Tuning(SpeedMode speed_mode, u32 command_index) {
|
||||
/* Clear vendor tuning control 1. */
|
||||
reg::Write(this->sdmmc_registers->vendor_tuning_cntrl1, 0);
|
||||
|
||||
/* Determine/configure the number of tries. */
|
||||
int num_tries;
|
||||
switch (speed_mode) {
|
||||
case SpeedMode_MmcHs200:
|
||||
case SpeedMode_MmcHs400:
|
||||
case SpeedMode_SdCardSdr104:
|
||||
num_tries = 128;
|
||||
reg::ReadWrite(this->sdmmc_registers->vendor_tuning_cntrl0, SD_REG_BITS_ENUM(VENDOR_TUNING_CNTRL0_NUM_TUNING_ITERATIONS, TRIES_128));
|
||||
break;
|
||||
case SpeedMode_SdCardSdr50:
|
||||
case SpeedMode_GcAsicFpgaSpeed:
|
||||
case SpeedMode_GcAsicSpeed:
|
||||
num_tries = 256;
|
||||
reg::ReadWrite(this->sdmmc_registers->vendor_tuning_cntrl0, SD_REG_BITS_ENUM(VENDOR_TUNING_CNTRL0_NUM_TUNING_ITERATIONS, TRIES_256));
|
||||
break;
|
||||
AMS_UNREACHABLE_DEFAULT_CASE();
|
||||
}
|
||||
|
||||
/* Configure the multiplier. */
|
||||
reg::ReadWrite(this->sdmmc_registers->vendor_tuning_cntrl0, SD_REG_BITS_VALUE(VENDOR_TUNING_CNTRL0_MUL_M, 1));
|
||||
|
||||
/* Configure tap value to be updated by hardware. */
|
||||
reg::ReadWrite(this->sdmmc_registers->vendor_tuning_cntrl0, SD_REG_BITS_ENUM(VENDOR_TUNING_CNTRL0_TAP_VALUE_UPDATED_BY_HW, UPDATED_BY_HW));
|
||||
|
||||
/* Configure to execute tuning. */
|
||||
reg::ReadWrite(this->sdmmc_registers->sd_host_standard_registers.host_control2, SD_REG_BITS_ENUM(HOST_CONTROL2_EXECUTE_TUNING, EXECUTE_TUNING));
|
||||
|
||||
/* Perform tuning num_tries times. */
|
||||
for (int i = 0; /* ... */; ++i) {
|
||||
/* Check if we've been removed. */
|
||||
R_TRY(this->CheckRemoved());
|
||||
|
||||
/* Issue the command. */
|
||||
this->IssueTuningCommand(command_index);
|
||||
|
||||
/* Check if tuning is done. */
|
||||
if (i >= num_tries) {
|
||||
break;
|
||||
}
|
||||
++i;
|
||||
|
||||
if (reg::HasValue(this->sdmmc_registers->sd_host_standard_registers.host_control2, SD_REG_BITS_ENUM(HOST_CONTROL2_EXECUTE_TUNING, TUNING_COMPLETED))) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check if we're using the tuned clock. */
|
||||
R_UNLESS(reg::HasValue(this->sdmmc_registers->sd_host_standard_registers.host_control2, SD_REG_BITS_ENUM(HOST_CONTROL2_SAMPLING_CLOCK, USING_TUNED_CLOCK)), sdmmc::ResultTuningFailed());
|
||||
|
||||
return ResultSuccess();
|
||||
}
|
||||
|
||||
void SdmmcController::SaveTuningStatusForHs400() {
|
||||
/* Save the current tap value. */
|
||||
this->tap_value_for_hs_400 = GetCurrentTapValue();
|
||||
this->is_valid_tap_value_for_hs_400 = true;
|
||||
}
|
||||
|
||||
}
|
||||
@@ -24,6 +24,9 @@ namespace ams::sdmmc::impl {
|
||||
|
||||
constexpr inline size_t SdmmcRegistersSize = 0x200;
|
||||
|
||||
constexpr inline dd::PhysicalAddress ApbMiscRegistersPhysicalAddress = UINT64_C(0x70000000);
|
||||
constexpr inline size_t ApbMiscRegistersSize = 16_KB;
|
||||
|
||||
class SdmmcController : public SdHostStandardController {
|
||||
private:
|
||||
struct SdmmcRegisters {
|
||||
@@ -72,37 +75,303 @@ namespace ams::sdmmc::impl {
|
||||
static_assert(sizeof(SdmmcRegisters) == SdmmcRegistersSize);
|
||||
private:
|
||||
SdmmcRegisters *sdmmc_registers;
|
||||
/* TODO */
|
||||
bool is_shutdown;
|
||||
bool is_awake;
|
||||
SpeedMode current_speed_mode;
|
||||
BusPower bus_power_before_sleep;
|
||||
BusWidth bus_width_before_sleep;
|
||||
SpeedMode speed_mode_before_sleep;
|
||||
u8 tap_value_before_sleep;
|
||||
bool is_powersaving_enable_before_sleep;
|
||||
u8 tap_value_for_hs_400;
|
||||
bool is_valid_tap_value_for_hs_400;
|
||||
Result drive_strength_calibration_status;
|
||||
private:
|
||||
void ReleaseReset(SpeedMode speed_mode);
|
||||
void AssertReset();
|
||||
Result StartupCore(BusPower bus_power);
|
||||
Result SetClockTrimmer(SpeedMode speed_mode, u8 tap_value);
|
||||
u8 GetCurrentTapValue();
|
||||
Result CalibrateDll();
|
||||
Result SetSpeedModeWithTapValue(SpeedMode speed_mode, u8 tap_value);
|
||||
Result IssueTuningCommand(u32 command_index);
|
||||
protected:
|
||||
void SetDriveCodeOffsets(BusPower bus_power);
|
||||
void CalibrateDriveStrength(BusPower bus_power);
|
||||
|
||||
virtual void SetPad() = 0;
|
||||
|
||||
virtual ClockResetController::Module GetClockResetModule() const = 0;
|
||||
|
||||
#if defined(AMS_SDMMC_USE_OS_EVENTS)
|
||||
virtual int GetInterruptNumber() const = 0;
|
||||
virtual os::InterruptEventType *GetInterruptEvent() const = 0;
|
||||
#endif
|
||||
|
||||
virtual bool IsNeedPeriodicDriveStrengthCalibration() = 0;
|
||||
virtual void ClearPadParked() = 0;
|
||||
virtual Result PowerOn(BusPower bus_power) = 0;
|
||||
virtual void PowerOff() = 0;
|
||||
virtual Result LowerBusPower() = 0;
|
||||
virtual void SetSchmittTrigger(BusPower bus_power) = 0;
|
||||
virtual u8 GetOutboundTapValue() const = 0;
|
||||
virtual u8 GetDefaultInboundTapValue() const = 0;
|
||||
virtual u8 GetVrefSelValue() const = 0;
|
||||
virtual void SetSlewCodes() = 0;
|
||||
virtual void GetAutoCalOffsets(u8 *out_auto_cal_pd_offset, u8 *out_auto_cal_pu_offset, BusPower bus_power) const = 0;
|
||||
virtual void SetDriveStrengthToDefaultValues(BusPower bus_power) = 0;
|
||||
public:
|
||||
explicit SdmmcController(dd::PhysicalAddress registers_phys_addr) : SdHostStandardController(registers_phys_addr, SdmmcRegistersSize) {
|
||||
/* Set sdmmc registers. */
|
||||
static_assert(offsetof(SdmmcRegisters, sd_host_standard_registers) == 0);
|
||||
this->sdmmc_registers = reinterpret_cast<SdmmcRegisters *>(this->registers);
|
||||
|
||||
this->is_shutdown = true;
|
||||
this->is_awake = true;
|
||||
this->is_valid_tap_value_for_hs_400 = false;
|
||||
this->drive_strength_calibration_status = sdmmc::ResultDriveStrengthCalibrationNotCompleted();
|
||||
this->tap_value_for_hs_400 = 0;
|
||||
this->current_speed_mode = SpeedMode_MmcIdentification;
|
||||
this->bus_power_before_sleep = BusPower_Off;
|
||||
this->bus_width_before_sleep = BusWidth_1Bit;
|
||||
this->speed_mode_before_sleep = SpeedMode_MmcIdentification;
|
||||
this->tap_value_before_sleep = 0;
|
||||
this->is_powersaving_enable_before_sleep = false;
|
||||
}
|
||||
|
||||
/* TODO */
|
||||
virtual void Initialize() override {
|
||||
/* Set pad. */
|
||||
this->SetPad();
|
||||
|
||||
/* Initialize our clock/reset module. */
|
||||
ClockResetController::Initialize(this->GetClockResetModule());
|
||||
|
||||
/* If necessary, initialize our interrupt event. */
|
||||
#if defined(AMS_SDMMC_USE_OS_EVENTS)
|
||||
{
|
||||
os::InterruptEventType *interrupt_event = this->GetInterruptEvent();
|
||||
os::InitializeInterruptEvent(interrupt_event, this->GetInterruptNumber(), os::EventClearMode_ManualClear);
|
||||
SdHostStandardController::PreSetInterruptEvent(interrupt_event);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Perform base initialization. */
|
||||
SdHostStandardController::Initialize();
|
||||
}
|
||||
|
||||
virtual void Finalize() override {
|
||||
/* Perform base finalization. */
|
||||
SdHostStandardController::Finalize();
|
||||
|
||||
/* If necessary, finalize our interrupt event. */
|
||||
#if defined(AMS_SDMMC_USE_OS_EVENTS)
|
||||
{
|
||||
os::FinalizeInterruptEvent(this->GetInterruptEvent());
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Finalize our clock/reset module. */
|
||||
ClockResetController::Finalize(this->GetClockResetModule());
|
||||
}
|
||||
|
||||
virtual Result Startup(BusPower bus_power, BusWidth bus_width, SpeedMode speed_mode, bool power_saving_enable) override;
|
||||
virtual void Shutdown() override;
|
||||
virtual void PutToSleep() override;
|
||||
virtual Result Awaken() override;
|
||||
virtual Result SwitchToSdr12() override;
|
||||
virtual Result SetSpeedMode(SpeedMode speed_mode) override;
|
||||
|
||||
virtual SpeedMode GetSpeedMode() const override {
|
||||
return this->current_speed_mode;
|
||||
}
|
||||
|
||||
virtual void SetPowerSaving(bool en) override;
|
||||
virtual void EnableDeviceClock() override;
|
||||
|
||||
virtual Result IssueCommand(const Command *command, TransferData *xfer_data, u32 *out_num_transferred_blocks) override;
|
||||
virtual Result IssueStopTransmissionCommand(u32 *out_response) override;
|
||||
|
||||
virtual bool IsSupportedTuning() const override {
|
||||
return true;
|
||||
}
|
||||
|
||||
virtual Result Tuning(SpeedMode speed_mode, u32 command_index) override;
|
||||
virtual void SaveTuningStatusForHs400() override;
|
||||
|
||||
virtual Result GetInternalStatus() const override {
|
||||
return this->drive_strength_calibration_status;
|
||||
}
|
||||
};
|
||||
|
||||
class Sdmmc2And4Controller : public SdmmcController {
|
||||
/* TODO */
|
||||
protected:
|
||||
virtual bool IsNeedPeriodicDriveStrengthCalibration() override {
|
||||
return false;
|
||||
}
|
||||
|
||||
virtual Result PowerOn(BusPower bus_power) override {
|
||||
/* Power for SDMMC2/4 is assumed on, so we don't need to do anything. */
|
||||
AMS_UNUSED(bus_power);
|
||||
return ResultSuccess();
|
||||
}
|
||||
|
||||
virtual void PowerOff() override {
|
||||
/* Power for SDMMC2/4 is assumed on, so we don't need to do anything. */
|
||||
}
|
||||
|
||||
virtual Result LowerBusPower() override {
|
||||
AMS_ABORT("Sdmmc2And4Controller cannot lower bus power\n");
|
||||
}
|
||||
|
||||
virtual void SetSchmittTrigger(BusPower bus_power) override {
|
||||
/* Do nothing. */
|
||||
AMS_UNUSED(bus_power);
|
||||
}
|
||||
|
||||
virtual u8 GetOutboundTapValue() const override {
|
||||
if (IsSocMariko()) {
|
||||
return 0xD;
|
||||
} else {
|
||||
return 0x8;
|
||||
}
|
||||
}
|
||||
|
||||
virtual u8 GetDefaultInboundTapValue() const override {
|
||||
if (IsSocMariko()) {
|
||||
return 0xB;
|
||||
} else {
|
||||
return 0x0;
|
||||
}
|
||||
}
|
||||
|
||||
virtual u8 GetVrefSelValue() const override {
|
||||
return 0x7;
|
||||
}
|
||||
|
||||
virtual void SetSlewCodes() override {
|
||||
/* Do nothing. */
|
||||
}
|
||||
|
||||
virtual void GetAutoCalOffsets(u8 *out_auto_cal_pd_offset, u8 *out_auto_cal_pu_offset, BusPower bus_power) const override {
|
||||
/* Ensure that we can write the offsets. */
|
||||
AMS_ABORT_UNLESS(out_auto_cal_pd_offset != nullptr);
|
||||
AMS_ABORT_UNLESS(out_auto_cal_pu_offset != nullptr);
|
||||
|
||||
/* Sdmmc2And4Controller only supports 1.8v. */
|
||||
AMS_ABORT_UNLESS(bus_power == BusPower_1_8V);
|
||||
|
||||
/* Set the offsets. */
|
||||
*out_auto_cal_pd_offset = 5;
|
||||
*out_auto_cal_pu_offset = 5;
|
||||
}
|
||||
public:
|
||||
explicit Sdmmc2And4Controller(dd::PhysicalAddress registers_phys_addr) : SdmmcController(registers_phys_addr) {
|
||||
/* ... */
|
||||
}
|
||||
|
||||
/* TODO */
|
||||
virtual bool IsSupportedBusPower(BusPower bus_power) const override {
|
||||
switch (bus_power) {
|
||||
case BusPower_Off: return true;
|
||||
case BusPower_1_8V: return true;
|
||||
case BusPower_3_3V: return false;
|
||||
AMS_UNREACHABLE_DEFAULT_CASE();
|
||||
}
|
||||
}
|
||||
|
||||
virtual bool IsSupportedBusWidth(BusWidth bus_width) const override {
|
||||
switch (bus_width) {
|
||||
case BusWidth_1Bit: return true;
|
||||
case BusWidth_4Bit: return true;
|
||||
case BusWidth_8Bit: return true;
|
||||
AMS_UNREACHABLE_DEFAULT_CASE();
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
constexpr inline dd::PhysicalAddress Sdmmc4RegistersPhysicalAddress = UINT64_C(0x700B0600);
|
||||
|
||||
class Sdmmc4Controller : public Sdmmc2And4Controller {
|
||||
/* TODO */
|
||||
private:
|
||||
#if defined(AMS_SDMMC_USE_OS_EVENTS)
|
||||
static constinit inline os::InterruptEventType s_interrupt_event{};
|
||||
#endif
|
||||
protected:
|
||||
virtual void SetPad() override {
|
||||
if (IsSocMariko()) {
|
||||
/* Get the apb registers address. */
|
||||
const uintptr_t apb_address = dd::QueryIoMapping(ApbMiscRegistersPhysicalAddress, ApbMiscRegistersSize);
|
||||
|
||||
/* Enable Schmitt Trigger in emmc4 iobrick. */
|
||||
reg::ReadWrite(apb_address + APB_MISC_GP_EMMC4_PAD_CFGPADCTRL, APB_MISC_REG_BITS_ENUM(GP_EMMC4_PAD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_E_SCH, ENABLE));
|
||||
|
||||
/* Clear CMD_PULLU, CLK_PULLD, DQS_PULLD. */
|
||||
reg::ReadWrite(apb_address + APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL, APB_MISC_REG_BITS_VALUE(GP_EMMC4_PAD_PUPD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLU, 0),
|
||||
APB_MISC_REG_BITS_VALUE(GP_EMMC4_PAD_PUPD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLD, 0),
|
||||
APB_MISC_REG_BITS_VALUE(GP_EMMC4_PAD_PUPD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLD, 0));
|
||||
|
||||
/* Read again to be sure our config takes. */
|
||||
reg::Read(apb_address + APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL);
|
||||
} else {
|
||||
/* On Erista, we can just leave the reset value intact. */
|
||||
}
|
||||
}
|
||||
|
||||
virtual ClockResetController::Module GetClockResetModule() const override {
|
||||
return ClockResetController::Module_Sdmmc4;
|
||||
}
|
||||
|
||||
#if defined(AMS_SDMMC_USE_OS_EVENTS)
|
||||
virtual int GetInterruptNumber() const override {
|
||||
return 63;
|
||||
}
|
||||
|
||||
virtual os::InterruptEventType *GetInterruptEvent() const override {
|
||||
return std::addressof(s_interrupt_event);
|
||||
}
|
||||
#endif
|
||||
|
||||
virtual void ClearPadParked() override {
|
||||
/* Get the apb registers address. */
|
||||
const uintptr_t apb_address = dd::QueryIoMapping(ApbMiscRegistersPhysicalAddress, ApbMiscRegistersSize);
|
||||
|
||||
/* Clear all MISC2PMC_EMMC4_*_PARK bits. */
|
||||
reg::ReadWrite(apb_address + APB_MISC_GP_EMMC4_PAD_CFGPADCTRL, APB_MISC_REG_BITS_VALUE(GP_EMMC4_PAD_CFGPADCTRL_MISC2PMC_EMMC4_ALL_PARK, 0));
|
||||
|
||||
/* Read to be sure our config takes. */
|
||||
reg::Read(apb_address + APB_MISC_GP_EMMC4_PAD_CFGPADCTRL);
|
||||
}
|
||||
|
||||
virtual void SetDriveStrengthToDefaultValues(BusPower bus_power) override {
|
||||
/* SDMMC4 only supports 1.8v. */
|
||||
AMS_ABORT_UNLESS(bus_power == BusPower_1_8V);
|
||||
|
||||
/* Ensure that we can control registers. */
|
||||
SdHostStandardController::EnsureControl();
|
||||
|
||||
/* Get the apb registers address. */
|
||||
const uintptr_t apb_address = dd::QueryIoMapping(ApbMiscRegistersPhysicalAddress, ApbMiscRegistersSize);
|
||||
|
||||
/* Determine the drv up/down values. */
|
||||
u8 drvdn, drvup;
|
||||
if (IsSocMariko()) {
|
||||
drvdn = 0xA;
|
||||
drvup = 0xA;
|
||||
} else {
|
||||
drvdn = 0x10;
|
||||
drvup = 0x10;
|
||||
}
|
||||
|
||||
/* Write the drv up/down values to APB_MISC_GP_EMMC4_PAD_CFGPADCTRL. */
|
||||
reg::ReadWrite(apb_address + APB_MISC_GP_EMMC4_PAD_CFGPADCTRL, APB_MISC_REG_BITS_VALUE(GP_EMMC4_PAD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_DRVDN_COMP, drvdn),
|
||||
APB_MISC_REG_BITS_VALUE(GP_EMMC4_PAD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_DRVUP_COMP, drvup));
|
||||
|
||||
/* Read to be sure our config takes. */
|
||||
reg::Read(apb_address + APB_MISC_GP_EMMC4_PAD_CFGPADCTRL);
|
||||
}
|
||||
public:
|
||||
Sdmmc4Controller() : Sdmmc2And4Controller(Sdmmc4RegistersPhysicalAddress) {
|
||||
/* ... */
|
||||
}
|
||||
|
||||
/* TODO */
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user