thermosphere: guest mem rewrite
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TuxSH
240
thermosphere/src/hvisor_guest_memory.cpp
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240
thermosphere/src/hvisor_guest_memory.cpp
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/*
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* Copyright (c) 2019-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hvisor_virtual_gic.hpp"
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#include "hvisor_safe_io_copy.hpp"
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#include "cpu/hvisor_cpu_caches.hpp"
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#include "cpu/hvisor_cpu_interrupt_mask_guard.hpp"
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using namespace ams::hvisor;
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using namespace ams::hvisor::cpu;
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namespace {
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template<typename T>
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T ReadBufferValue(const void *buf, size_t off)
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{
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static_assert(std::is_unsigned_v<T> && sizeof(T) <= 4);
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T ret;
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std::memcpy(&ret, reinterpret_cast<const u8 *>(buf) + off, sizeof(T));
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return ret;
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}
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template<typename T>
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void WriteBufferValue(void *buf, size_t off, T val)
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{
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static_assert(std::is_unsigned_v<T> && sizeof(T) <= 4);
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std::memcpy(reinterpret_cast<u8 *>(buf) + off, T, sizeof(T));
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}
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size_t GuestReadWriteGicd(size_t offset, size_t size, void *readBuf, const void *writeBuf)
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{
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auto &vgic = VirtualGic::GetInstance();
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if (readBuf != nullptr) {
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size_t readOffset = 0;
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size_t rem = size;
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while (rem > 0) {
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if ((offset + readOffset) % 4 == 0 && rem >= 4) {
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// All accesses of this kind are valid
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WriteBufferValue<u32>(readBuf, readOffset, vgic.ReadGicdRegister(offset + readOffset, 4));
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readOffset += 4;
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rem -= 4;
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} else if ((offset + readOffset) % 2 == 0 && rem >= 2) {
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// All accesses of this kind would be translated to ldrh and are thus invalid. Abort.
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return readOffset;
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} else if (VirtualGic::ValidateGicdRegisterAccess(offset + readOffset, 1)) {
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// Valid byte access
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WriteBufferValue<u8>(readBuf, readOffset, vgic.ReadGicdRegister(offset + readOffset, 1));
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readOffset += 1;
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rem -= 1;
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} else {
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// Invalid byte access
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return readOffset;
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}
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}
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}
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if (writeBuf != nullptr) {
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size_t writeOffset = 0;
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size_t rem = size;
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while (rem > 0) {
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if ((offset + writeOffset) % 4 == 0 && rem >= 4) {
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// All accesses of this kind are valid
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vgic.WriteGicdRegister(ReadBufferValue<u32>(writeBuf, writeOffset), offset + writeOffset, 4);
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writeOffset += 4;
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rem -= 4;
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} else if ((offset + writeOffset) % 2 == 0 && rem >= 2) {
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// All accesses of this kind would be translated to ldrh and are thus invalid. Abort.
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return writeOffset;
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} else if (VirtualGic::ValidateGicdRegisterAccess(offset + writeOffset, 1)) {
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// Valid byte access
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vgic.WriteGicdRegister(ReadBufferValue<u8>(writeBuf, writeOffset), offset + writeOffset, 1);
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writeOffset += 1;
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rem -= 1;
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} else {
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// Invalid byte access
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return writeOffset;
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}
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}
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}
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return size;
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}
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size_t GuestReadWriteDeviceMemory(void *addr, size_t size, void *readBuf, const void *writeBuf)
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{
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if (readBuf != nullptr) {
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size_t sz = SafeIoCopy(readBuf, addr, size);
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if (sz < size) {
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return sz;
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}
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}
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if (writeBuf != nullptr) {
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size_t sz = SafeIoCopy(addr, writeBuf, size);
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if (sz < size) {
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return sz;
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}
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}
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// Translation tables must be on Normal memory & Device memory isn't cacheable, so we don't have
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// that kind of thing to handle...
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return size;
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}
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size_t GuestReadWriteNormalMemory(void *addr, size_t size, void *readBuf, const void *writeBuf)
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{
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if (readBuf != nullptr) {
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std::memcpy(readBuf, addr, size);
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}
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if (writeBuf != nullptr) {
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std::memcpy(addr, writeBuf, size);
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// We may have written to executable memory or to translation tables...
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// & the page may have various aliases.
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// We need to ensure cache & TLB coherency.
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CleanDataCacheRangePoU(addr, size);
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u32 policy = GetInstructionCachePolicy();
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if (policy == 1 || policy == 2) {
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// AVIVT, VIVT
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InvalidateInstructionCache();
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} else {
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// VPIPT, PIPT
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// Ez coherency, just do range operations...
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InvalidateInstructionCacheRangePoU(addr, size);
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}
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TlbInvalidateEl1();
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dsb();
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isb();
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}
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return size;
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}
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size_t GuestReadWriteMemoryPage(uintptr_t addr, size_t size, void *readBuf, const void *writeBuf)
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{
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InterruptMaskGuard ig{};
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size_t offset = addr & 0xFFFul;
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// Translate the VA, stages 1&2
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__asm__ __volatile__ ("at s12e1r, %0" :: "r"(addr) : "memory");
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u64 par = THERMOSPHERE_GET_SYSREG(par_el1);
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if (par & PAR_F) {
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// The translation failed. Why?
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if (par & PAR_S) {
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// Stage 2 fault. Could be an attempt to access the GICD, let's see what the IPA is...
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__asm__ __volatile__ ("at s1e1r, %0" :: "r"(addr) : "memory");
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par = THERMOSPHERE_GET_SYSREG(par_el1);
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if ((par & PAR_F) != 0 || (par & PAR_PA_MASK) != VirtualGic::gicdPhysicalAddress) {
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// The guest doesn't have access to it...
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// Read as 0, write ignored
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if (readBuf != NULL) {
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std::memset(readBuf, 0, size);
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}
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} else {
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// GICD mmio
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size = GuestReadWriteGicd(offset, size, readBuf, writeBuf);
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}
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} else {
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// Oops, couldn't read/write anything (stage 1 fault)
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size = 0;
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}
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} else {
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/*
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Translation didn't fail.
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To avoid "B2.8 Mismatched memory attributes" we must use the same effective
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attributes & shareability as the guest.
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Note that par_el1 reports the effective shareablity of device and noncacheable memory as inner shareable.
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In fact, the VMSAv8-64 section in the Armv8 ARM reads:
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"The shareability field is only relevant if the memory is a Normal Cacheable memory type. All Device and Normal
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Non-cacheable memory regions are always treated as Outer Shareable, regardless of the translation table
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shareability attributes."
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There's one corner case where we can't avoid it: another core is running,
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changes the attributes (other than permissions) of the page, and issues
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a broadcasting TLB maintenance instructions and/or accesses the page with the altered
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attribute itself. We don't handle this corner case -- just don't read/write that kind of memory...
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*/
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u64 memAttribs = (par >> PAR_ATTR_SHIFT) & PAR_ATTR_MASK;
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u64 shrb = (par >> PAR_SH_SHIFT) & PAR_SH_MASK;
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uintptr_t pa = par & PAR_PA_MASK;
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uintptr_t va = MemoryMap::MapGuestPage(pa, memAttribs, shrb);
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void *vaddr = reinterpret_cast<void *>(va + offset);
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if (memAttribs & 0xF0) {
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// Normal memory, or unpredictable
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size = GuestReadWriteNormalMemory(vaddr, size, readBuf, writeBuf);
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} else {
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// Device memory, or unpredictable
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size = GuestReadWriteDeviceMemory(vaddr, size, readBuf, writeBuf);
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}
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MemoryMap::UnmapGuestPage();
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}
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return size;
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}
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}
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namespace ams::hvisor {
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size_t GuestReadWriteMemory(uintptr_t addr, size_t size, void *readBuf, const void *writeBuf)
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{
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uintptr_t curAddr = addr;
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size_t remainingAmount = size;
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u8 *rb8 = reinterpret_cast<u8 *>(readBuf);
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const u8 *wb8 = reinterpret_cast<const u8 *>(writeBuf);
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while (remainingAmount > 0) {
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size_t expectedAmount = ((curAddr & ~0xFFFul) + 0x1000) - curAddr;
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expectedAmount = expectedAmount > remainingAmount ? remainingAmount : expectedAmount;
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size_t actualAmount = GuestReadWriteMemoryPage(curAddr, expectedAmount, rb8, wb8);
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curAddr += actualAmount;
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rb8 += actualAmount;
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wb8 += actualAmount;
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remainingAmount -= actualAmount;
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if (actualAmount != expectedAmount) {
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break;
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}
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}
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return curAddr - addr;
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}
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}
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