exo2: implement warmboot firmware
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@@ -50,6 +50,7 @@
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#define APBDEV_PMC_WAKE2_LVL (0x164)
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#define APBDEV_PMC_WAKE2_STATUS (0x168)
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#define APBDEV_PMC_AUTO_WAKE2_LVL_MASK (0x170)
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#define APBDEV_PMC_OSC_EDPD_OVER (0x1A4)
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#define APBDEV_PMC_CLK_OUT_CNTRL (0x1A8)
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#define APBDEV_PMC_IO_DPD_REQ (0x1B8)
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#define APBDEV_PMC_IO_DPD_STATUS (0x1BC)
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@@ -59,6 +60,7 @@
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#define APBDEV_PMC_SCRATCH45 (0x234)
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#define APBDEV_PMC_SCRATCH46 (0x238)
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#define APBDEV_PMC_TSC_MULT (0x2B4)
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#define APBDEV_PMC_STICKY_BITS (0x2C0)
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#define APBDEV_PMC_WEAK_BIAS (0x2C8)
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#define APBDEV_PMC_GPU_RG_CNTRL (0x2D4)
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#define APBDEV_PMC_CNTRL2 (0x440)
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@@ -162,6 +164,8 @@ enum APBDEV_PMC_PWRGATE_TOGGLE_PARTID : u8 {
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APBDEV_PMC_PWRGATE_TOGGLE_PARTID_VE2 = 29,
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};
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DEFINE_PMC_REG_BIT_ENUM(REMOVE_CLAMPING_COMMAND_CRAIL, 0, DISABLE, ENABLE);
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enum APBDEV_PMC_PWRGATE_STATUS_STATUS {
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APBDEV_PMC_PWRGATE_STATUS_STATUS_OFF = 0,
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APBDEV_PMC_PWRGATE_STATUS_STATUS_ON = 1,
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@@ -221,4 +225,11 @@ DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_XUSBC, 22, DISABLE, ENABLE);
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DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_VIC, 23, DISABLE, ENABLE);
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DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_IRAM, 24, DISABLE, ENABLE);
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DEFINE_PMC_REG(OSC_EDPD_OVER_XOFS, 1, 6);
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DEFINE_PMC_REG_BIT_ENUM(STICKY_BITS_HDA_LPBK_DIS, 0, DISABLE, ENABLE);
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DEFINE_PMC_REG_BIT_ENUM(STICKY_BITS_JTAG_STS, 6, ENABLE, DISABLE);
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DEFINE_PMC_REG_BIT_ENUM(CNTRL2_WAKE_DET_EN, 9, DISABLE, ENABLE);
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DEFINE_PMC_REG_BIT_ENUM(SEC_DISABLE2_WRITE21, 26, OFF, ON);
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