exo2: implement warmboot firmware
This commit is contained in:
Michael Scire
@@ -29,14 +29,51 @@
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#define DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
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#define CLK_RST_CONTROLLER_RST_SOURCE (0x000)
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#define CLK_RST_CONTROLLER_RST_SOURCE (0x000)
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#define CLK_RST_CONTROLLER_MISC_CLK_ENB (0x048)
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#define CLK_RST_CONTROLLER_MISC_CLK_ENB (0x048)
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#define CLK_RST_CONTROLLER_OSC_CTRL (0x050)
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#define CLK_RST_CONTROLLER_PLLX_BASE (0x0E0)
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#define CLK_RST_CONTROLLER_CCLKG_BURST_POLICY (0x368)
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#define CLK_RST_CONTROLLER_SUPER_CCLKG_DIVIDER (0x36C)
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#define CLK_RST_CONTROLLER_CCLKLP_BURST_POLICY (0x370)
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#define CLK_RST_CONTROLLER_SUPER_CCLKLP_DIVIDER (0x374)
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#define CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2 (0x388)
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#define CLK_RST_CONTROLLER_SPARE_REG0 (0x55C)
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA (0x0F8)
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB (0x0FC)
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC (0x3A0)
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD (0x3A4)
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#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE (0x554)
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DEFINE_CLK_RST_REG(MISC_CLK_ENB_CFG_ALL_VISIBLE, 28, 1);
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DEFINE_CLK_RST_REG_BIT_ENUM(OSC_CTRL_XOE, 0, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG(OSC_CTRL_XOFS, 4, 6);
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DEFINE_CLK_RST_REG_BIT_ENUM(PLLX_BASE_PLLX_ENABLE, 30, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIVISOR, 0, 8);
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DEFINE_CLK_RST_REG(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIVIDEND, 8, 8);
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DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIS_FROM_CPU_IRQ, 24, NO_IMPACT, DISABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIS_FROM_COP_IRQ, 25, NO_IMPACT, DISABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIS_FROM_CPU_FIQ, 26, NO_IMPACT, DISABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIS_FROM_COP_FIQ, 27, NO_IMPACT, DISABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLKG_DIVIDER_SUPER_CDIV_ENB, 31, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLKLP_DIVIDER_SUPER_CDIV_ENB, 31, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(CCLK_BURST_POLICY_CWAKEUP_IDLE_SOURCE, 0, CLKM, RSVD1, CLKS, RSVD3, PLLP_OUT0, PLLP_OUT4, RSVD6, RSVD7, PLLX_OUT0_LJ, DVFS_CPU_CLK, RSVD10, RSVD11, RSVD12, RSVD13, PLLX_OUT0, DVFS_CPU_CLK_LJ);
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DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(CCLK_BURST_POLICY_CWAKEUP_RUN_SOURCE, 4, CLKM, RSVD1, CLKS, RSVD3, PLLP_OUT0, PLLP_OUT4, RSVD6, RSVD7, PLLX_OUT0_LJ, DVFS_CPU_CLK, RSVD10, RSVD11, RSVD12, RSVD13, PLLX_OUT0, DVFS_CPU_CLK_LJ);
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DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(CCLK_BURST_POLICY_CWAKEUP_IRQ_SOURCE, 8, CLKM, RSVD1, CLKS, RSVD3, PLLP_OUT0, PLLP_OUT4, RSVD6, RSVD7, PLLX_OUT0_LJ, DVFS_CPU_CLK, RSVD10, RSVD11, RSVD12, RSVD13, PLLX_OUT0, DVFS_CPU_CLK_LJ);
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DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(CCLK_BURST_POLICY_CWAKEUP_FIQ_SOURCE, 12, CLKM, RSVD1, CLKS, RSVD3, PLLP_OUT0, PLLP_OUT4, RSVD6, RSVD7, PLLX_OUT0_LJ, DVFS_CPU_CLK, RSVD10, RSVD11, RSVD12, RSVD13, PLLX_OUT0, DVFS_CPU_CLK_LJ);
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DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(CCLK_BURST_POLICY_CPU_STATE, 28, STDBY, IDLE, RUN, RSVD3, IRQ, RSVD5, RSVD6, RSVD7, FIQ, RSVD9, RSVD10, RSVD11, RSVD12, RSVD13, RSVD14, RSVD15);
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DEFINE_CLK_RST_REG(CPU_SOFTRST_CTRL2_CAR2PMC_CPU_ACK_WIDTH, 0, 12);
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DEFINE_CLK_RST_REG_TWO_BIT_ENUM(SPARE_REG0_CLK_M_DIVISOR, 2, CLK_M_DIVISOR1, CLK_M_DIVISOR2, CLK_M_DIVISOR3, CLK_M_DIVISOR4);
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/* RST_DEVICES */
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#define CLK_RST_CONTROLLER_RST_DEVICES_L (0x004)
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#define CLK_RST_CONTROLLER_RST_DEVICES_H (0x008)
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@@ -56,18 +93,45 @@ DEFINE_CLK_RST_REG(MISC_CLK_ENB_CFG_ALL_VISIBLE, 28, 1);
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_W (0x364)
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/* CLK_SOURCE */
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 (0x124)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 (0x128)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA (0x178)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB (0x17C)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC (0x1A0)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON (0x3E8)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 (0x124)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 (0x128)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA (0x178)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB (0x17C)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC (0x1A0)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT (0x3B4)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON (0x3E8)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF (0x62C)
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#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_SOC (0x630)
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/* RST_DEV_*_SET */
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#define CLK_RST_CONTROLLER_RST_DEV_L_SET (0x300)
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#define CLK_RST_CONTROLLER_RST_DEV_H_SET (0x308)
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#define CLK_RST_CONTROLLER_RST_DEV_U_SET (0x310)
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#define CLK_RST_CONTROLLER_RST_DEV_V_SET (0x430)
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/* RST_DEV_*_CLR */
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#define CLK_RST_CONTROLLER_RST_DEV_L_CLR (0x304)
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#define CLK_RST_CONTROLLER_RST_DEV_H_CLR (0x30C)
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#define CLK_RST_CONTROLLER_RST_DEV_U_CLR (0x314)
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#define CLK_RST_CONTROLLER_RST_DEV_V_CLR (0x434)
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/* CLK_ENB_*_SET */
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#define CLK_RST_CONTROLLER_CLK_ENB_L_SET (0x320)
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#define CLK_RST_CONTROLLER_CLK_ENB_H_SET (0x328)
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#define CLK_RST_CONTROLLER_CLK_ENB_U_SET (0x330)
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#define CLK_RST_CONTROLLER_CLK_ENB_V_SET (0x440)
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#define CLK_RST_CONTROLLER_CLK_ENB_W_SET (0x448)
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#define CLK_RST_CONTROLLER_CLK_ENB_X_SET (0x284)
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#define CLK_RST_CONTROLLER_CLK_ENB_Y_SET (0x29C)
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/* CLK_ENB_*_CLR */
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#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR (0x324)
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#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR (0x32C)
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#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR (0x334)
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#define CLK_RST_CONTROLLER_CLK_ENB_X_CLR (0x288)
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#define CLK_RST_CONTROLLER_CLK_ENB_Y_CLR (0x2A0)
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#define CLK_RST_CONTROLLER_CLK_ENB_V_CLR (0x444)
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#define CLK_RST_CONTROLLER_CLK_ENB_W_CLR (0x44C)
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/* CLK_ENB_*_INDEX */
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#define CLK_RST_CONTROLLER_CLK_ENB_I2C1_INDEX (0x0C)
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@@ -95,14 +159,92 @@ DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_SDMMC3_LEGACY_TMCLK_OVR_ON, 30, O
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DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_SDMMC4_LEGACY_TMCLK_OVR_ON, 31, OFF, ON);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_I2C1_I2C1_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
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DEFINE_CLK_RST_REG(CLK_SOURCE_I2C1_I2C1_CLK_DIVISOR, 0, 8);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_I2C5_I2C5_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
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DEFINE_CLK_RST_REG(CLK_SOURCE_I2C5_I2C5_CLK_DIVISOR, 0, 8);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTA_UARTA_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTB_UARTB_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTC_UARTC_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_MSELECT_MSELECT_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT2, PLLC4_OUT1, CLK_S, CLK_M, PLLC4_OUT0);
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DEFINE_CLK_RST_REG(CLK_SOURCE_MSELECT_MSELECT_CLK_DIVISOR, 0, 8);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_ACTMON_ACTMON_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, CLK_S, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
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DEFINE_CLK_RST_REG(CLK_SOURCE_DVFS_REF_DVFS_REF_DIVISOR, 0, 8);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_DVFS_REF_DVFS_REF_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
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DEFINE_CLK_RST_REG(CLK_SOURCE_DVFS_SOC_DVFS_SOC_DIVISOR, 0, 8);
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DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_DVFS_SOC_DVFS_SOC_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
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DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_L_SET_SET_COP_RST, 1, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_L_CLR_CLR_COP_RST, 1, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CPURESET0, 0, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CPURESET1, 1, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CPURESET2, 2, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CPURESET3, 3, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET0, 16, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET1, 17, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET2, 18, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET3, 19, DISABLE, ENABLE);
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DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_NONCPURESET, 29, DISABLE, ENABLE);
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/* TODO: Actually include all devices. */
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#define CLK_RST_FOREACH_DEVICE(HANDLER) \
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HANDLER(L, CPU, 0, 0) \
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HANDLER(L, RTC, 0, 4) \
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HANDLER(L, TMR, 0, 5) \
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HANDLER(L, GPIO, 0, 8) \
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HANDLER(L, CACHE2, 0, 31) \
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HANDLER(H, MEM, 1, 0) \
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HANDLER(H, PMC, 1, 6) \
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HANDLER(H, FUSE, 1, 7) \
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HANDLER(H, I2C5, 1, 15) \
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HANDLER(H, EMC, 1, 25) \
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HANDLER(U, CSITE, 2, 9) \
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HANDLER(U, IRAMA, 2, 20) \
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HANDLER(U, IRAMB, 2, 21) \
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HANDLER(U, IRAMC, 2, 22) \
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HANDLER(U, IRAMD, 2, 23) \
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HANDLER(U, CRAM2, 2, 24) \
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HANDLER(V, CPUG, 3, 0) \
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HANDLER(V, MSELECT, 3, 3) \
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HANDLER(V, SPDIF_DOUBLER, 3, 22) \
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HANDLER(V, TZRAM, 3, 30) \
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HANDLER(V, SE, 3, 31) \
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HANDLER(W, PCIERX0, 4, 2) \
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HANDLER(W, PCIERX1, 4, 3) \
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HANDLER(W, PCIERX2, 4, 4) \
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HANDLER(W, PCIERX3, 4, 5) \
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HANDLER(W, PCIERX4, 4, 6) \
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HANDLER(W, PCIERX5, 4, 7) \
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HANDLER(W, ENTROPY, 4, 21) \
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HANDLER(W, DVFS, 4, 27) \
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HANDLER(W, MC1, 4, 30) \
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HANDLER(X, MC_CAPA, 5, 7) \
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HANDLER(X, MC_CBPA, 5, 8) \
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HANDLER(X, MC_CPU, 5, 9) \
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HANDLER(X, MC_BBC, 5, 10) \
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HANDLER(X, EMC_DLL, 5, 14) \
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HANDLER(X, GPU, 5, 24) \
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HANDLER(X, DBGAPB, 5, 25) \
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HANDLER(X, PLLG_REF, 5, 29) \
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HANDLER(Y, MC_CCPA, 6, 8) \
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HANDLER(Y, MC_CDPA, 6, 9) \
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HANDLER(Y, PLLP_OUT_CPU, 6, 31)
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#define CLK_RST_DEFINE_SET_CLR_REG(REGISTER, DEVICE, REGISTER_INDEX, DEVICE_INDEX) \
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DEFINE_CLK_RST_REG_BIT_ENUM(CLK_ENB_##REGISTER##_SET_SET_CLK_ENB_##DEVICE, DEVICE_INDEX, DISABLE, ENABLE); \
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DEFINE_CLK_RST_REG_BIT_ENUM(CLK_ENB_##REGISTER##_CLR_CLR_CLK_ENB_##DEVICE, DEVICE_INDEX, DISABLE, ENABLE); \
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DEFINE_CLK_RST_REG_BIT_ENUM(CLK_ENB_##REGISTER##_CLK_ENB_##DEVICE, DEVICE_INDEX, DISABLE, ENABLE); \
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DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_##REGISTER##_SET_SET_##DEVICE##_RST, DEVICE_INDEX, DISABLE, ENABLE); \
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DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_##REGISTER##_CLR_CLR_##DEVICE##_RST, DEVICE_INDEX, DISABLE, ENABLE); \
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DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_##REGISTER##_##DEVICE##_RST, DEVICE_INDEX, DISABLE, ENABLE);
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CLK_RST_FOREACH_DEVICE(CLK_RST_DEFINE_SET_CLR_REG)
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#undef CLK_RST_DEFINE_SET_CLR_REG
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