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thermosphere: trap set/way dcache access

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note: qemu does not implement the trap
This commit is contained in:
TuxSH
2020-01-15 17:30:25 +00:00
parent 114cdc5aa4
commit 2753b6cf8f
6 changed files with 92 additions and 4 deletions
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13
thermosphere/src/sysreg_traps.c
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@@ -16,7 +16,7 @@
#include "sysreg_traps.h"
#include "guest_timers.h"
#include "software_breakpoints.h"
#include "caches.h"
static inline u64 doSystemRegisterRead(const ExceptionStackFrame *frame, u32 normalizedIss)
{
@@ -43,7 +43,7 @@ static inline u64 doSystemRegisterRead(const ExceptionStackFrame *frame, u32 nor
val = currentCoreCtx->emulPtimerCval;
break;
}
// NOTE: We should trap ID_AA64* register to lie to the guest about e.g. MemTag but it would take too much space
default: {
// We shouldn't have trapped on other registers other than debug regs
// and we want the latter as RA0/WI
@@ -74,6 +74,15 @@ static inline void doSystemRegisterWrite(ExceptionStackFrame *frame, u32 normali
writeEmulatedPhysicalCompareValue(frame, val);
break;
}
case ENCODE_SYSREG_ISS(DC_CSW):
case ENCODE_SYSREG_ISS(DC_CISW): {
cacheHandleTrappedSetWayOperation(false);
break;
}
case ENCODE_SYSREG_ISS(DC_ISW): {
cacheHandleTrappedSetWayOperation(true);
break;
}
default: {
// We shouldn't have trapped on other registers other than debug regs