kern: SvcUnmapPhysicalMemory, cleanup thread pinning

libraries/libmesosphere/source/arch/arm64/kern_exception_handlers.cpp

@@ -145,15 +145,15 @@ namespace ams::kern::arch::arm64 {
         {
             const bool is_user_mode = (context->psr & 0xF) == 0;
             if (is_user_mode) {
-                /* Handle any changes needed to the user preemption state. */
-                if (GetCurrentThread().GetUserPreemptionState() != 0 && GetCurrentProcess().GetPreemptionStatePinnedThread(GetCurrentCoreId()) == nullptr) {
+                /* If the user disable count is set, we may need to pin the current thread. */
+                if (GetCurrentThread().GetUserDisableCount() != 0 && GetCurrentProcess().GetPinnedThread(GetCurrentCoreId()) == nullptr) {
                     KScopedSchedulerLock lk;
 
-                    /* Note the preemption state in process. */
-                    GetCurrentProcess().SetPreemptionState();
+                    /* Pin the current thread. */
+                    GetCurrentProcess().PinCurrentThread();
 
-                    /* Set the kernel preemption state flag. */
-                    GetCurrentThread().SetKernelPreemptionState(1);
+                    /* Set the interrupt flag for the thread. */
+                    GetCurrentThread().SetInterruptFlag();
                 }
 
                 /* Enable interrupts while we process the usermode exception. */

libraries/libmesosphere/source/arch/arm64/svc/kern_svc_handlers_asm.s

@@ -31,6 +31,7 @@ _ZN3ams4kern4arch5arm6412SvcHandler64Ev:
     mrs     x9, elr_el1
     mrs     x10, spsr_el1
     mrs     x11, tpidr_el0
+    mrs     x18, tpidr_el1
 
     /* Save callee-saved registers. */
     stp     x19, x20, [sp, #(8 * 19)]
@@ -63,8 +64,8 @@ _ZN3ams4kern4arch5arm6412SvcHandler64Ev:
     tst     x10, #1
     b.eq    3f
 
-    /* Check if our preemption state allows us to call SVCs. */
-    mrs     x10, tpidrro_el0
+    /* Check if our disable count allows us to call SVCs. */
+    ldr     x10, [x18, #0x30]
     ldrh    w10, [x10, #0x100]
     cbz     w10, 1f
 
@@ -83,7 +84,6 @@ _ZN3ams4kern4arch5arm6412SvcHandler64Ev:
     strb    w8,  [sp, #(0x120 + 0x11)]
 
     /* Invoke the SVC handler. */
-    mrs     x18, tpidr_el1
     msr     daifclr, #2
     blr     x11
     msr     daifset, #2
@@ -211,6 +211,7 @@ _ZN3ams4kern4arch5arm6412SvcHandler32Ev:
     mrs     x17, elr_el1
     mrs     x20, spsr_el1
     mrs     x19, tpidr_el0
+    mrs     x18, tpidr_el1
     stp     x17, x20, [sp, #(8 * 32)]
     str     x19,      [sp, #(8 * 34)]
 
@@ -239,8 +240,8 @@ _ZN3ams4kern4arch5arm6412SvcHandler32Ev:
     tst     x17, #1
     b.eq    3f
 
-    /* Check if our preemption state allows us to call SVCs. */
-    mrs     x15, tpidrro_el0
+    /* Check if our disable count allows us to call SVCs. */
+    ldr     x15, [x18, #0x30]
     ldrh    w15, [x15, #0x100]
     cbz     w15, 1f
 
@@ -259,7 +260,6 @@ _ZN3ams4kern4arch5arm6412SvcHandler32Ev:
     strb    w16, [sp, #(0x120 + 0x11)]
 
     /* Invoke the SVC handler. */
-    mrs     x18, tpidr_el1
     msr     daifclr, #2
     blr     x19
     msr     daifset, #2