thermosphere: use barriers and caches *properly*. Cache code refactoring

- set/way cache ops create losses of coherency, do not broadcast and are only meant to be used on boot, period.

Cache ops by VA are **the only way** to do data cache maintenance.

Fix a bug where the L2 cache was evicted by each core. It shouldn't have.

- Cleaning dcache to PoU and invalidating icache to PoU, by VA is sufficient for self-modifying code

- Since we operate within a single cluster and don't do DMA, we almost always operate within the inner shareability domain

(commit untested on real hw)

thermosphere/src/initSystem.c

@@ -42,6 +42,9 @@ static void initSysregs(void)
     SET_SYSREG(cntkctl_el1,     0x00000003);    // Don't trap anything for now; event streams disabled
     SET_SYSREG(cntp_ctl_el0,    0x00000000);
     SET_SYSREG(cntv_ctl_el0,    0x00000000);
+
+    __dsb();
+    __isb();
 }
 
 void initSystem(u32 coreId, bool isBootCore, u64 argument)
@@ -49,9 +52,6 @@ void initSystem(u32 coreId, bool isBootCore, u64 argument)
     coreCtxInit(coreId, isBootCore, argument);
     initSysregs();
 
-    __dsb_sy();
-    __isb();
-
     if (isBootCore) {
         if (!currentCoreCtx->warmboot) {
             memset(__bss_start__, 0, __end__ - __bss_start__);