Minor information update regarding previously unknown mysteries
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@@ -35,6 +35,14 @@
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#define MC_SMMU_PTB_DATA 0x20
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#define MC_SMMU_TLB_FLUSH 0x30
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#define MC_SMMU_PTC_FLUSH 0x34
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#define MC_SMMU_ASID_SECURITY 0x38
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#define MC_SMMU_ASID_SECURITY_1 0x3c
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#define MC_SMMU_ASID_SECURITY_2 0x9e0
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#define MC_SMMU_ASID_SECURITY_3 0x9e4
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#define MC_SMMU_ASID_SECURITY_4 0x9e8
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#define MC_SMMU_ASID_SECURITY_5 0x9ec
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#define MC_SMMU_ASID_SECURITY_6 0x9f0
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#define MC_SMMU_ASID_SECURITY_7 0x9f4
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#define MC_SMMU_AFI_ASID 0x238
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#define MC_SMMU_AVPC_ASID 0x23c
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#define MC_SMMU_PPCS1_ASID 0x298
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@@ -140,28 +140,26 @@ void bootup_misc_mmio(void) {
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APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0 = sec_disable_2;
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}
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/* Reset Translation Enable Registers. */
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/* Reset Translation Enable registers. */
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MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_0) = 0xFFFFFFFF;
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MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_1) = 0xFFFFFFFF;
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MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_2) = 0xFFFFFFFF;
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MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_3) = 0xFFFFFFFF;
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MAKE_MC_REG(MC_SMMU_TRANSLATION_ENABLE_4) = 0xFFFFFFFF;
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/* TODO: What are these MC reg writes? */
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/* Set SMMU ASID security registers. */
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if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_400) {
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MAKE_MC_REG(0x038) = 0xE;
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MAKE_MC_REG(MC_SMMU_ASID_SECURITY) = 0xE;
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} else {
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MAKE_MC_REG(0x038) = 0x0;
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MAKE_MC_REG(MC_SMMU_ASID_SECURITY) = 0x0;
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}
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MAKE_MC_REG(0x03C) = 0;
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/* MISC registers. */
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MAKE_MC_REG(0x9E0) = 0;
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MAKE_MC_REG(0x9E4) = 0;
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MAKE_MC_REG(0x9E8) = 0;
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MAKE_MC_REG(0x9EC) = 0;
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MAKE_MC_REG(0x9F0) = 0;
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MAKE_MC_REG(0x9F4) = 0;
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MAKE_MC_REG(MC_SMMU_ASID_SECURITY_1) = 0;
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MAKE_MC_REG(MC_SMMU_ASID_SECURITY_2) = 0;
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MAKE_MC_REG(MC_SMMU_ASID_SECURITY_3) = 0;
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MAKE_MC_REG(MC_SMMU_ASID_SECURITY_4) = 0;
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MAKE_MC_REG(MC_SMMU_ASID_SECURITY_5) = 0;
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MAKE_MC_REG(MC_SMMU_ASID_SECURITY_6) = 0;
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MAKE_MC_REG(MC_SMMU_ASID_SECURITY_7) = 0;
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if (exosphere_get_target_firmware() >= ATMOSPHERE_TARGET_FIRMWARE_400) {
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MAKE_MC_REG(MC_SMMU_PTB_ASID) = 0;
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@@ -40,6 +40,14 @@ static inline uintptr_t get_mc_base(void) {
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#define MC_SMMU_PTB_DATA 0x20
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#define MC_SMMU_TLB_FLUSH 0x30
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#define MC_SMMU_PTC_FLUSH 0x34
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#define MC_SMMU_ASID_SECURITY 0x38
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#define MC_SMMU_ASID_SECURITY_1 0x3c
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#define MC_SMMU_ASID_SECURITY_2 0x9e0
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#define MC_SMMU_ASID_SECURITY_3 0x9e4
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#define MC_SMMU_ASID_SECURITY_4 0x9e8
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#define MC_SMMU_ASID_SECURITY_5 0x9ec
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#define MC_SMMU_ASID_SECURITY_6 0x9f0
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#define MC_SMMU_ASID_SECURITY_7 0x9f4
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#define MC_SMMU_AFI_ASID 0x238
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#define MC_SMMU_AVPC_ASID 0x23c
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#define MC_SMMU_PPCS1_ASID 0x298
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