thermosphère: C++ gdb/regs
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TuxSH
226
thermosphere/src/gdb/hvisor_gdb_regs.cpp
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226
thermosphere/src/gdb/hvisor_gdb_regs.cpp
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/*
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* Copyright (c) 2019-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* This file is part of Luma3DS.
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* Copyright (C) 2016-2019 Aurora Wright, TuxSH
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*
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* SPDX-License-Identifier: (MIT OR GPL-2.0-or-later)
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*/
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#include "hvisor_gdb_defines_internal.hpp"
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#include "hvisor_gdb_packet_data.hpp"
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#include "../exceptions.h"
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#include "../fpu.h"
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namespace {
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auto GetRegisterPointerAndSize(unsigned long id, ExceptionStackFrame *frame, FpuRegisterCache *fpuRegCache)
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{
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void *outPtr = nullptr;
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size_t outSz = 0;
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switch (id) {
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case 0 ... 30:
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outPtr = &frame->x[id];
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outSz = 8;
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break;
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case 31:
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outPtr = exceptionGetSpPtr(frame);
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outSz = 8;
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break;
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case 32:
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outPtr = &frame->spsr_el2;
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outSz = 4;
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break;
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case 33 ... 64:
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outPtr = &fpuRegCache->q[id - 33];
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outSz = 16;
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break;
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case 65:
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outPtr = &fpuRegCache->fpsr;
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outSz = 4;
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break;
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case 66:
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outPtr = &fpuRegCache->fpcr;
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outSz = 4;
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break;
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default:
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__builtin_unreachable();
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break;
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}
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return std::tuple{outPtr, outSz};
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}
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}
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namespace ams::hvisor::gdb {
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// Note: GDB treats cpsr, fpsr, fpcr as 32-bit integers...
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GDB_DEFINE_HANDLER(ReadRegisters)
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{
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ENSURE(m_selectedCoreId == currentCoreCtx->coreId);
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ExceptionStackFrame *frame = currentCoreCtx->guestFrame;
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FpuRegisterCache *fpuRegCache = fpuReadRegisters();
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char *buf = GetInPlaceOutputBuffer();
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size_t n = 0;
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struct {
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u64 sp;
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u64 pc;
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u32 cpsr;
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} cpuSprs = {
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.sp = *exceptionGetSpPtr(frame),
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.pc = frame->elr_el2,
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.cpsr = static_cast<u32>(frame->spsr_el2),
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};
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u32 fpuSprs[2] = {
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static_cast<u32>(fpuRegCache->fpsr),
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static_cast<u32>(fpuRegCache->fpcr),
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};
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n += EncodeHex(buf + n, frame->x, sizeof(frame->x));
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n += EncodeHex(buf + n, &cpuSprs, 8+8+4);
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n += EncodeHex(buf + n, fpuRegCache->q, sizeof(fpuRegCache->q));
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n += EncodeHex(buf + n, fpuSprs, sizeof(fpuSprs));
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return SendPacket(std::string_view{buf, n});
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}
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GDB_DEFINE_HANDLER(WriteRegisters)
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{
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ENSURE(m_selectedCoreId == currentCoreCtx->coreId);
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ExceptionStackFrame *frame = currentCoreCtx->guestFrame;
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FpuRegisterCache *fpuRegCache = fpuGetRegisterCache();
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char *tmp = GetWorkBuffer();
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size_t n = 0;
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struct {
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u64 sp;
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u64 pc;
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u32 cpsr;
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} cpuSprs;
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u32 fpuSprs[2];
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struct {
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void *dst;
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size_t sz;
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} infos[4] = {
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{ frame->x, sizeof(frame->x) },
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{ &cpuSprs, 8+8+4 },
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{ fpuRegCache->q, sizeof(fpuRegCache->q) },
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{ fpuSprs, sizeof(fpuSprs) },
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};
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// Parse & return on error
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for (const auto &info: infos) {
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// Fuck std::string_view.substr throwing exceptions
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if (DecodeHex(tmp + n, m_commandData.data(), info.sz) != info.sz) {
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return ReplyErrno(EILSEQ);
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}
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m_commandData.remove_prefix(2 * info.sz);
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n += info.sz;
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}
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// Copy. Note: we don't check if cpsr (spsr_el2) was modified to return to EL2...
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n = 0;
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for (const auto &info: infos) {
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std::copy(tmp + n, tmp + n + info.sz, info.dst);
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n += info.sz;
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}
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*exceptionGetSpPtr(frame) = cpuSprs.sp;
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frame->elr_el2 = cpuSprs.pc;
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frame->spsr_el2 = cpuSprs.cpsr;
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fpuRegCache->fpsr = fpuSprs[0];
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fpuRegCache->fpcr = fpuSprs[1];
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fpuCommitRegisters();
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return ReplyOk();
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}
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GDB_DEFINE_HANDLER(ReadRegister)
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{
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ENSURE(m_selectedCoreId == currentCoreCtx->coreId);
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ExceptionStackFrame *frame = currentCoreCtx->guestFrame;
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FpuRegisterCache *fpuRegCache = nullptr;
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auto [nread, gdbRegNum] = ParseHexIntegerList<1>(m_commandData);
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if (nread == 0) {
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return ReplyErrno(EILSEQ);
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}
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// Check the register number
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if (gdbRegNum >= 31 + 3 + 32 + 2) {
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return ReplyErrno(EINVAL);
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}
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if (gdbRegNum > 31 + 3) {
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// FPU register -- must read the FPU registers first
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fpuRegCache = fpuReadRegisters();
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}
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return std::apply(SendHexPacket, GetRegisterPointerAndSize(gdbRegNum, frame, fpuRegCache));
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}
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GDB_DEFINE_HANDLER(WriteRegister)
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{
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ENSURE(m_selectedCoreId == currentCoreCtx->coreId);
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char *tmp = GetWorkBuffer();
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ExceptionStackFrame *frame = currentCoreCtx->guestFrame;
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FpuRegisterCache *fpuRegCache = fpuGetRegisterCache();
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auto [nread, gdbRegNum] = ParseHexIntegerList<1>(m_commandData, '=');
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if (nread == 0) {
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return ReplyErrno(EILSEQ);
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}
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m_commandData.remove_prefix(nread);
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// Check the register number
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if (gdbRegNum >= 31 + 3 + 32 + 2) {
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return ReplyErrno(EINVAL);
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}
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auto [regPtr, sz] = GetRegisterPointerAndSize(gdbRegNum, frame, fpuRegCache);
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// Decode, check for errors
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if (m_commandData.size() != 2 * sz || DecodeHex(tmp, m_commandData) != sz) {
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return ReplyErrno(EILSEQ);
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}
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std::copy(tmp, tmp + sz, regPtr);
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if (gdbRegNum > 31 + 3) {
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// FPU register -- must commit the FPU registers
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fpuCommitRegisters();
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}
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return ReplyOk();
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}
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}
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