exo2: implement the first half of SmcCpuSuspend

libraries/libexosphere/include/exosphere/clkrst.hpp

@@ -27,6 +27,7 @@ namespace ams::clkrst {
     void EnableUartCClock();
     void EnableActmonClock();
     void EnableI2c1Clock();
+    void EnableI2c5Clock();
 
     void DisableI2c1Clock();
 

libraries/libexosphere/include/exosphere/flow.hpp

@@ -25,5 +25,6 @@ namespace ams::flow {
     void SetCpuCsr(int core, u32 enable_ext);
     void SetHaltCpuEvents(int core, bool resume_on_irq);
     void SetCc4Ctrl(int core, u32 value);
+    void ClearL2FlushControl();
 
 }

libraries/libexosphere/include/exosphere/pmc.hpp

@@ -36,6 +36,8 @@ namespace ams::pmc {
     void SetRegisterAddress(uintptr_t address);
 
     void InitializeRandomScratch();
+    void EnableWakeEventDetection();
+    void ConfigureForSc7Entry();
 
     void LockSecureRegister(SecureRegister reg);
 

libraries/libexosphere/include/exosphere/pmic.hpp

@@ -29,5 +29,7 @@ namespace ams::pmic {
 
     void EnableVddCpu(Regulator regulator);
     void DisableVddCpu(Regulator regulator);
+    void EnableSleep();
+    bool IsAcOk();
 
 }

libraries/libexosphere/include/exosphere/tegra/tegra_flow_ctlr.hpp

@@ -18,6 +18,7 @@
 
 
 #define FLOW_CTLR_FLOW_DBG_QUAL        (0x050)
+#define FLOW_CTLR_L2FLUSH_CONTROL      (0x094)
 #define FLOW_CTLR_BPMP_CLUSTER_CONTROL (0x098)
 
 #define FLOW_CTLR_CPU0_CSR             (0x008)

libraries/libexosphere/include/exosphere/tegra/tegra_pmc.hpp

@@ -212,3 +212,5 @@ DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_XUSBB, 21, DISABLE, ENABLE);
 DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_XUSBC, 22, DISABLE, ENABLE);
 DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_VIC,   23, DISABLE, ENABLE);
 DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_IRAM,  24, DISABLE, ENABLE);
+
+DEFINE_PMC_REG_BIT_ENUM(CNTRL2_WAKE_DET_EN, 9, DISABLE, ENABLE);