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kernel_ldr::cpu: prevent reordering around barrier instructions

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Michael Scire authored and SciresM committed 2019-12-31 00:46:09 -08:00
1 parent 879f8a5147
commit a85e20bcea
1 file changed
+4 -4
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libraries/libmesosphere/include/mesosphere/arch/arm64/kern_cpu.hpp
+4 -4
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@@ -21,19 +21,19 @@ namespace ams::kern::arm64::cpu {
/* Helpers for managing memory state. */ /* Helpers for managing memory state. */
ALWAYS_INLINE void DataSynchronizationBarrier() { ALWAYS_INLINE void DataSynchronizationBarrier() {
__asm__ __volatile__("dsb sy"); __asm__ __volatile__("dsb sy" ::: "memory");
} }
ALWAYS_INLINE void DataSynchronizationBarrierInnerShareable() { ALWAYS_INLINE void DataSynchronizationBarrierInnerShareable() {
__asm__ __volatile__("dsb ish"); __asm__ __volatile__("dsb ish" ::: "memory");
} }
ALWAYS_INLINE void DataMemoryBarrier() { ALWAYS_INLINE void DataMemoryBarrier() {
__asm__ __volatile__("dmb sy"); __asm__ __volatile__("dmb sy" ::: "memory");
} }
ALWAYS_INLINE void InstructionMemoryBarrier() { ALWAYS_INLINE void InstructionMemoryBarrier() {
__asm__ __volatile__("isb"); __asm__ __volatile__("isb" ::: "memory");
} }
ALWAYS_INLINE void EnsureInstructionConsistency() { ALWAYS_INLINE void EnsureInstructionConsistency() {