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git subrepo pull --force emummc

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subrepo:
  subdir:   "emummc"
  merged:   "2fc47cbb8"
upstream:
  origin:   "https://github.com/lulle2007200/emuMMC.git"
  branch:   "develop"
  commit:   "2fc47cbb8"
git-subrepo:
  version:  "0.4.9"
  origin:   "https://github.com/ingydotnet/git-subrepo.git"
  commit:   "30db3b8"
This commit is contained in:
lulle2007200
2025-05-12 14:22:12 +02:00
parent 0188898af4
commit 92c599f0f0
342 changed files with 106677 additions and 974 deletions
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227
emummc/source/fatal/bdk/storage/emmc.c vendored Normal file
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/*
* Copyright (c) 2018 naehrwert
* Copyright (c) 2019-2024 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <string.h>
#include "emmc.h"
#include <mem/heap.h>
#include <soc/fuse.h>
#include <storage/mbr_gpt.h>
#include <utils/list.h>
static u16 emmc_errors[3] = { 0 }; // Init and Read/Write errors.
static u32 emmc_mode = EMMC_MMC_HS400;
sdmmc_t emmc_sdmmc;
sdmmc_storage_t emmc_storage;
FATFS emmc_fs;
#ifdef BDK_EMUMMC_ENABLE
int emummc_storage_read(u32 sector, u32 num_sectors, void *buf);
int emummc_storage_write(u32 sector, u32 num_sectors, void *buf);
#endif
void emmc_error_count_increment(u8 type)
{
switch (type)
{
case EMMC_ERROR_INIT_FAIL:
emmc_errors[0]++;
break;
case EMMC_ERROR_RW_FAIL:
emmc_errors[1]++;
break;
case EMMC_ERROR_RW_RETRY:
emmc_errors[2]++;
break;
}
}
u16 *emmc_get_error_count()
{
return emmc_errors;
}
u32 emmc_get_mode()
{
return emmc_mode;
}
void emmc_end() { sdmmc_storage_end(&emmc_storage); }
int emmc_init_retry(bool power_cycle)
{
u32 bus_width = SDMMC_BUS_WIDTH_8;
u32 type = SDHCI_TIMING_MMC_HS400;
// Power cycle SD eMMC.
if (power_cycle)
{
emmc_mode--;
emmc_end();
}
// Get init parameters.
switch (emmc_mode)
{
case EMMC_INIT_FAIL: // Reset to max.
return 0;
case EMMC_1BIT_HS52:
bus_width = SDMMC_BUS_WIDTH_1;
type = SDHCI_TIMING_MMC_HS52;
break;
case EMMC_8BIT_HS52:
type = SDHCI_TIMING_MMC_HS52;
break;
case EMMC_MMC_HS200:
type = SDHCI_TIMING_MMC_HS200;
break;
case EMMC_MMC_HS400:
type = SDHCI_TIMING_MMC_HS400;
break;
default:
emmc_mode = EMMC_MMC_HS400;
}
return sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, bus_width, type);
}
bool emmc_initialize(bool power_cycle)
{
// Reset mode in case of previous failure.
if (emmc_mode == EMMC_INIT_FAIL)
emmc_mode = EMMC_MMC_HS400;
if (power_cycle)
emmc_end();
int res = !emmc_init_retry(false);
while (true)
{
if (!res)
return true;
else
{
emmc_errors[EMMC_ERROR_INIT_FAIL]++;
if (emmc_mode == EMMC_INIT_FAIL)
break;
else
res = !emmc_init_retry(true);
}
}
emmc_end();
return false;
}
int emmc_set_partition(u32 partition) { return sdmmc_storage_set_mmc_partition(&emmc_storage, partition); }
void emmc_gpt_parse(link_t *gpt)
{
gpt_t *gpt_buf = (gpt_t *)zalloc(GPT_NUM_BLOCKS * EMMC_BLOCKSIZE);
#ifdef BDK_EMUMMC_ENABLE
emummc_storage_read(GPT_FIRST_LBA, GPT_NUM_BLOCKS, gpt_buf);
#else
sdmmc_storage_read(&emmc_storage, GPT_FIRST_LBA, GPT_NUM_BLOCKS, gpt_buf);
#endif
// Check if no GPT or more than max allowed entries.
if (memcmp(&gpt_buf->header.signature, "EFI PART", 8) || gpt_buf->header.num_part_ents > 128)
goto out;
for (u32 i = 0; i < gpt_buf->header.num_part_ents; i++)
{
emmc_part_t *part = (emmc_part_t *)zalloc(sizeof(emmc_part_t));
if (gpt_buf->entries[i].lba_start < gpt_buf->header.first_use_lba)
continue;
part->index = i;
part->lba_start = gpt_buf->entries[i].lba_start;
part->lba_end = gpt_buf->entries[i].lba_end;
part->attrs = gpt_buf->entries[i].attrs;
// ASCII conversion. Copy only the LSByte of the UTF-16LE name.
for (u32 j = 0; j < 36; j++)
part->name[j] = gpt_buf->entries[i].name[j];
part->name[35] = 0;
list_append(gpt, &part->link);
}
out:
free(gpt_buf);
}
void emmc_gpt_free(link_t *gpt)
{
LIST_FOREACH_SAFE(iter, gpt)
free(CONTAINER_OF(iter, emmc_part_t, link));
}
emmc_part_t *emmc_part_find(link_t *gpt, const char *name)
{
LIST_FOREACH_ENTRY(emmc_part_t, part, gpt, link)
if (!strcmp(part->name, name))
return part;
return NULL;
}
int emmc_part_read(emmc_part_t *part, u32 sector_off, u32 num_sectors, void *buf)
{
// The last LBA is inclusive.
if (part->lba_start + sector_off > part->lba_end)
return 0;
#ifdef BDK_EMUMMC_ENABLE
return emummc_storage_read(part->lba_start + sector_off, num_sectors, buf);
#else
return sdmmc_storage_read(&emmc_storage, part->lba_start + sector_off, num_sectors, buf);
#endif
}
int emmc_part_write(emmc_part_t *part, u32 sector_off, u32 num_sectors, void *buf)
{
// The last LBA is inclusive.
if (part->lba_start + sector_off > part->lba_end)
return 0;
#ifdef BDK_EMUMMC_ENABLE
return emummc_storage_write(part->lba_start + sector_off, num_sectors, buf);
#else
return sdmmc_storage_write(&emmc_storage, part->lba_start + sector_off, num_sectors, buf);
#endif
}
void nx_emmc_get_autorcm_masks(u8 *mod0, u8 *mod1)
{
if (fuse_read_hw_state() == FUSE_NX_HW_STATE_PROD)
{
*mod0 = 0xF7;
*mod1 = 0x86;
}
else
{
*mod0 = 0x37;
*mod1 = 0x84;
}
}

77
emummc/source/fatal/bdk/storage/emmc.h vendored Normal file
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/*
* Copyright (c) 2018 naehrwert
* Copyright (c) 2019-2022 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _EMMC_H_
#define _EMMC_H_
#include <storage/sdmmc.h>
#include <utils/types.h>
#include <utils/list.h>
#include <libs/fatfs/ff.h>
#define GPT_FIRST_LBA 1
#define GPT_NUM_BLOCKS 33
#define EMMC_BLOCKSIZE SDMMC_DAT_BLOCKSIZE
enum
{
EMMC_INIT_FAIL = 0,
EMMC_1BIT_HS52 = 1,
EMMC_8BIT_HS52 = 2,
EMMC_MMC_HS200 = 3,
EMMC_MMC_HS400 = 4,
};
enum
{
EMMC_ERROR_INIT_FAIL = 0,
EMMC_ERROR_RW_FAIL = 1,
EMMC_ERROR_RW_RETRY = 2
};
typedef struct _emmc_part_t
{
u32 index;
u32 lba_start;
u32 lba_end;
u64 attrs;
char name[37];
link_t link;
} emmc_part_t;
extern sdmmc_t emmc_sdmmc;
extern sdmmc_storage_t emmc_storage;
extern FATFS emmc_fs;
void emmc_error_count_increment(u8 type);
u16 *emmc_get_error_count();
u32 emmc_get_mode();
int emmc_init_retry(bool power_cycle);
bool emmc_initialize(bool power_cycle);
int emmc_set_partition(u32 partition);
void emmc_end();
void emmc_gpt_parse(link_t *gpt);
void emmc_gpt_free(link_t *gpt);
emmc_part_t *emmc_part_find(link_t *gpt, const char *name);
int emmc_part_read(emmc_part_t *part, u32 sector_off, u32 num_sectors, void *buf);
int emmc_part_write(emmc_part_t *part, u32 sector_off, u32 num_sectors, void *buf);
void nx_emmc_get_autorcm_masks(u8 *mod0, u8 *mod1);
#endif

84
emummc/source/fatal/bdk/storage/mbr_gpt.h vendored Normal file
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/*
* Copyright (c) 2018 naehrwert
* Copyright (c) 2019 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef MBR_GPT_H
#define MBR_GPT_H
#include <utils/types.h>
typedef struct _mbr_chs_t
{
u8 head;
u8 sector;
u8 cylinder;
} __attribute__((packed)) mbr_chs_t;
typedef struct _mbr_part_t
{
u8 status;
mbr_chs_t start_sct_chs;
u8 type;
mbr_chs_t end_sct_chs;
u32 start_sct;
u32 size_sct;
} __attribute__((packed)) mbr_part_t;
typedef struct _mbr_t
{
/* 0x000 */ u8 bootstrap[440];
/* 0x1B8 */ u32 signature;
/* 0x1BC */ u16 copy_protected;
/* 0x1BE */ mbr_part_t partitions[4];
/* 0x1FE */ u16 boot_signature;
} __attribute__((packed)) mbr_t;
typedef struct _gpt_entry_t
{
/* 0x00 */ u8 type_guid[0x10];
/* 0x10 */ u8 part_guid[0x10];
/* 0x20 */ u64 lba_start;
/* 0x28 */ u64 lba_end;
/* 0x30 */ u64 attrs;
/* 0x38 */ u16 name[36];
} gpt_entry_t;
typedef struct _gpt_header_t
{
/* 0x00 */ u64 signature; // "EFI PART"
/* 0x08 */ u32 revision;
/* 0x0C */ u32 size;
/* 0x10 */ u32 crc32;
/* 0x14 */ u32 res1;
/* 0x18 */ u64 my_lba;
/* 0x20 */ u64 alt_lba;
/* 0x28 */ u64 first_use_lba;
/* 0x30 */ u64 last_use_lba;
/* 0x38 */ u8 disk_guid[0x10];
/* 0x48 */ u64 part_ent_lba;
/* 0x50 */ u32 num_part_ents;
/* 0x54 */ u32 part_ent_size;
/* 0x58 */ u32 part_ents_crc32;
/* 0x5C */ u8 res2[420]; // Used as first 3 partition entries backup for HOS.
} gpt_header_t;
typedef struct _gpt_t
{
gpt_header_t header;
gpt_entry_t entries[128];
} gpt_t;
#endif

454
emummc/source/fatal/bdk/storage/mmc.h vendored Normal file
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/*
* Header for MultiMediaCard (MMC)
*
* Copyright 2002 Hewlett-Packard Company
* Copyright 2018-2021 CTCaer
*
* Use consistent with the GNU GPL is permitted,
* provided that this copyright notice is
* preserved in its entirety in all copies and derived works.
*
* HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
* AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
* FITNESS FOR ANY PARTICULAR PURPOSE.
*
* Many thanks to Alessandro Rubini and Jonathan Corbet!
*
* Based strongly on code by:
*
* Author: Yong-iL Joh <tolkien@mizi.com>
*
* Author: Andrew Christian
* 15 May 2002
*/
#ifndef MMC_H
#define MMC_H
/* Standard MMC commands (4.1) type argument response */
/* class 1 */
#define MMC_GO_IDLE_STATE 0 /* bc */
#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
#define MMC_ALL_SEND_CID 2 /* bcr R2 */
#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
#define MMC_SET_DSR 4 /* bc [31:16] RCA */
#define MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */
#define MMC_SWITCH 6 /* ac [31:0] See below R1b */
#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
#define MMC_SEND_EXT_CSD 8 /* adtc R1 */
#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
#define MMC_STOP_TRANSMISSION 12 /* ac R1b */
#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
#define MMC_BUS_TEST_R 14 /* adtc R1 */
#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
#define MMC_BUS_TEST_W 19 /* adtc R1 */
#define MMC_SPI_READ_OCR 58 /* spi spi_R3 */
#define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */
/* class 2 */
#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
#define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */
#define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */
/* class 3 */
#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
/* class 4 */
#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
#define MMC_PROGRAM_CID 26 /* adtc R1 */
#define MMC_PROGRAM_CSD 27 /* adtc R1 */
/* class 6 */
#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
/* class 5 */
#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
#define MMC_ERASE 38 /* ac R1b */
/* class 9 */
#define MMC_FAST_IO 39 /* ac <Complex> R4 */
#define MMC_GO_IRQ_STATE 40 /* bcr R5 */
/* class 7 */
#define MMC_LOCK_UNLOCK 42 /* adtc R1b */
/* class 8 */
#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */
#define MMC_VENDOR_60_CMD 60 /* Vendor Defined */
#define MMC_VENDOR_61_CMD 61 /* Vendor Defined */
#define MMC_VENDOR_62_CMD 62 /* Vendor Defined */
#define MMC_VENDOR_63_CMD 63 /* Vendor Defined */
/* class 11 */
#define MMC_QUE_TASK_PARAMS 44 /* ac [20:16] task id R1 */
#define MMC_QUE_TASK_ADDR 45 /* ac [31:0] data addr R1 */
#define MMC_EXECUTE_READ_TASK 46 /* adtc [20:16] task id R1 */
#define MMC_EXECUTE_WRITE_TASK 47 /* adtc [20:16] task id R1 */
#define MMC_CMDQ_TASK_MGMT 48 /* ac [20:16] task id R1b */
/*
* MMC_SWITCH argument format:
*
* [31:26] Always 0
* [25:24] Access Mode
* [23:16] Location of target Byte in EXT_CSD
* [15:08] Value Byte
* [07:03] Always 0
* [02:00] Command Set
*/
/*
* MMC status in R1, for native mode (SPI bits are different)
* Type
* e : error bit
* s : status bit
* r : detected and set for the actual command response
* x : detected and set during command execution. the host must poll
* the card by sending status command in order to read these bits.
* Clear condition
* a : according to the card state
* b : always related to the previous command. Reception of a valid
* command will clear it (with a delay of one command)
* c : clear by read
*/
#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
#define R1_ERASE_PARAM (1 << 27) /* ex, c */
#define R1_WP_VIOLATION (1 << 26) /* erx, c */
#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
#define R1_CC_ERROR (1 << 20) /* erx, c */
#define R1_ERROR (1 << 19) /* erx, c */
#define R1_UNDERRUN (1 << 18) /* ex, c */
#define R1_OVERRUN (1 << 17) /* ex, c */
#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
#define R1_ERASE_RESET (1 << 13) /* sr, c */
#define R1_STATUS(x) ((x) & 0xFFFFE000)
#define R1_CURRENT_STATE(x) (((x) & 0x00001E00) >> 9) /* sx, b (4 bits) */
#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
#define R1_SWITCH_ERROR (1 << 7) /* sx, c */
#define R1_EXCEPTION_EVENT (1 << 6) /* sr, a */
#define R1_APP_CMD (1 << 5) /* sr, c */
#define R1_SKIP_STATE_CHECK (1 << 4) /* Custom state to skip expected state check */
#define R1_AKE_SEQ_ERROR (1 << 3)
/* R1_CURRENT_STATE 12:9 */
#define R1_STATE(x) ((x) << 9)
#define R1_STATE_IDLE 0
#define R1_STATE_READY 1
#define R1_STATE_IDENT 2
#define R1_STATE_STBY 3
#define R1_STATE_TRAN 4
#define R1_STATE_DATA 5
#define R1_STATE_RCV 6
#define R1_STATE_PRG 7
#define R1_STATE_DIS 8
/*
* MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS
* R1 is the low order byte; R2 is the next highest byte, when present.
*/
#define R1_SPI_IDLE (1 << 0)
#define R1_SPI_ERASE_RESET (1 << 1)
#define R1_SPI_ILLEGAL_COMMAND (1 << 2)
#define R1_SPI_COM_CRC (1 << 3)
#define R1_SPI_ERASE_SEQ (1 << 4)
#define R1_SPI_ADDRESS (1 << 5)
#define R1_SPI_PARAMETER (1 << 6)
/* R1 bit 7 is always zero */
#define R2_SPI_CARD_LOCKED (1 << 8)
#define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */
#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
#define R2_SPI_ERROR (1 << 10)
#define R2_SPI_CC_ERROR (1 << 11)
#define R2_SPI_CARD_ECC_ERROR (1 << 12)
#define R2_SPI_WP_VIOLATION (1 << 13)
#define R2_SPI_ERASE_PARAM (1 << 14)
#define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */
#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
/*
* OCR bits are mostly in host.h
*/
#define MMC_CARD_VDD_18 (1 << 7) /* Card VDD voltage 1.8 */
#define MMC_CARD_VDD_27_34 (0x7F << 15) /* Card VDD voltage 2.7 ~ 3.4 */
#define MMC_CARD_CCS (1 << 30) /* Card Capacity status bit */
#define MMC_CARD_BUSY (1 << 31) /* Card Power up status bit */
/*
* Card Command Classes (CCC)
*/
#define CCC_BASIC (1<<0) /* (0) Basic protocol functions */
/* (CMD0,1,2,3,4,7,9,10,12,13,15) */
/* (and for SPI, CMD58,59) */
#define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */
/* (CMD11) */
#define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */
/* (CMD16,17,18) */
#define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */
/* (CMD20) */
#define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */
/* (CMD16,24,25,26,27) */
#define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */
/* (CMD32,33,34,35,36,37,38,39) */
#define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */
/* (CMD28,29,30) */
#define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */
/* (CMD16,CMD42) */
#define CCC_APP_SPEC (1<<8) /* (8) Application specific */
/* (CMD55,56,57,ACMD*) */
#define CCC_IO_MODE (1<<9) /* (9) I/O mode */
/* (CMD5,39,40,52,53) */
#define CCC_SWITCH (1<<10) /* (10) High speed switch */
/* (CMD6,34,35,36,37,50) */
/* (11) Reserved */
/* (CMD?) */
/*
* CSD field definitions
*/
#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */
#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
#define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */
#define CSD_STRUCT_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */
#define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */
#define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */
#define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */
#define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */
#define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */
/*
* EXT_CSD fields
*/
#define EXT_CSD_CMDQ_MODE_EN 15 /* R/W */
#define EXT_CSD_FLUSH_CACHE 32 /* W */
#define EXT_CSD_CACHE_CTRL 33 /* R/W */
#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
#define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */
#define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */
#define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */
#define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */
#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */
#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
#define EXT_CSD_PARTITION_SETTING_COMPLETED 155 /* R/W */
#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* RO, 3 bytes */
#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */
#define EXT_CSD_HPI_MGMT 161 /* R/W */
#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
#define EXT_CSD_BKOPS_EN 163 /* R/W */
#define EXT_CSD_BKOPS_START 164 /* W */
#define EXT_CSD_SANITIZE_START 165 /* W */
#define EXT_CSD_WR_REL_PARAM 166 /* RO */
#define EXT_CSD_RPMB_MULT 168 /* RO */
#define EXT_CSD_FW_CONFIG 169 /* R/W */
#define EXT_CSD_BOOT_WP 173 /* R/W */
#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
#define EXT_CSD_PART_CONFIG 179 /* R/W */
#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
#define EXT_CSD_BUS_WIDTH 183 /* R/W */
#define EXT_CSD_STROBE_SUPPORT 184 /* RO */
#define EXT_CSD_HS_TIMING 185 /* R/W */
#define EXT_CSD_POWER_CLASS 187 /* R/W */
#define EXT_CSD_REV 192 /* RO */
#define EXT_CSD_STRUCTURE 194 /* RO */
#define EXT_CSD_CARD_TYPE 196 /* RO */
#define EXT_CSD_DRIVER_STRENGTH 197 /* RO */
#define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */
#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
#define EXT_CSD_PWR_CL_52_195 200 /* RO */
#define EXT_CSD_PWR_CL_26_195 201 /* RO */
#define EXT_CSD_PWR_CL_52_360 202 /* RO */
#define EXT_CSD_PWR_CL_26_360 203 /* RO */
#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
#define EXT_CSD_S_A_TIMEOUT 217 /* RO */
#define EXT_CSD_REL_WR_SEC_C 222 /* RO */
#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
#define EXT_CSD_BOOT_MULT 226 /* RO */
#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
#define EXT_CSD_TRIM_MULT 232 /* RO */
#define EXT_CSD_PWR_CL_200_195 236 /* RO */
#define EXT_CSD_PWR_CL_200_360 237 /* RO */
#define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */
#define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */
#define EXT_CSD_BKOPS_STATUS 246 /* RO */
#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */
#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
#define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */
#define EXT_CSD_FIRMWARE_VERSION 254 /* RO, 8 bytes */
#define EXT_CSD_DEVICE_VERSION 262 /* RO, 2 bytes */
#define EXT_CSD_PRE_EOL_INFO 267 /* RO */
#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A 268 /* RO */
#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B 269 /* RO */
#define EXT_CSD_CMDQ_DEPTH 307 /* RO */
#define EXT_CSD_CMDQ_SUPPORT 308 /* RO */
#define EXT_CSD_SUPPORTED_MODE 493 /* RO */
#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */
#define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */
#define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */
#define EXT_CSD_MAX_PACKED_READS 501 /* RO */
#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
#define EXT_CSD_HPI_FEATURES 503 /* RO */
/*
* EXT_CSD field definitions
*/
#define EXT_CSD_WR_REL_PARAM_EN (1<<2)
#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40)
#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10)
#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04)
#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01)
#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7)
#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1)
#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3)
#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4)
#define EXT_CSD_PART_SETTING_COMPLETED (0x1)
#define EXT_CSD_PART_SUPPORT_PART_EN (0x1)
#define EXT_CSD_CMD_SET_NORMAL (1<<0)
#define EXT_CSD_CMD_SET_SECURE (1<<1)
#define EXT_CSD_CMD_SET_CPSECURE (1<<2)
#define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */
#define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */
#define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | \
EXT_CSD_CARD_TYPE_HS_52)
#define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */
/* DDR mode @1.8V or 3V I/O */
#define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */
/* DDR mode @1.2V I/O */
#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
| EXT_CSD_CARD_TYPE_DDR_1_2V)
#define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */
#define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */
/* SDR mode @1.2V I/O */
#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
EXT_CSD_CARD_TYPE_HS200_1_2V)
#define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */
#define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */
#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
EXT_CSD_CARD_TYPE_HS400_1_2V)
#define EXT_CSD_CARD_TYPE_HS400ES (1<<8) /* Card can run at HS400ES */
#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
#define EXT_CSD_BUS_WIDTH_STROBE (1<<7) /* Enhanced strobe mode */
#define EXT_CSD_TIMING_BC 0 /* Backwards compatility */
#define EXT_CSD_TIMING_HS 1 /* High speed */
#define EXT_CSD_TIMING_HS200 2 /* HS200 */
#define EXT_CSD_TIMING_HS400 3 /* HS400 */
#define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */
#define EXT_CSD_SEC_ER_EN (1<<0)
#define EXT_CSD_SEC_BD_BLK_EN (1<<2)
#define EXT_CSD_SEC_GB_CL_EN (1<<4)
#define EXT_CSD_SEC_SANITIZE (1<<6) /* v4.5 only */
#define EXT_CSD_RST_N_EN_MASK 0x3
#define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */
#define EXT_CSD_NO_POWER_NOTIFICATION 0
#define EXT_CSD_POWER_ON 1
#define EXT_CSD_POWER_OFF_SHORT 2
#define EXT_CSD_POWER_OFF_LONG 3
#define EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */
#define EXT_CSD_PWR_CL_4BIT_MASK 0x0F /* 8 bit PWR CLS */
#define EXT_CSD_PWR_CL_8BIT_SHIFT 4
#define EXT_CSD_PWR_CL_4BIT_SHIFT 0
#define EXT_CSD_PACKED_EVENT_EN (1<<3)
/*
* EXCEPTION_EVENT_STATUS field
*/
#define EXT_CSD_URGENT_BKOPS (1<<0)
#define EXT_CSD_DYNCAP_NEEDED (1<<1)
#define EXT_CSD_SYSPOOL_EXHAUSTED (1<<2)
#define EXT_CSD_PACKED_FAILURE (1<<3)
#define EXT_CSD_PACKED_GENERIC_ERROR (1<<0)
#define EXT_CSD_PACKED_INDEXED_ERROR (1<<1)
/*
* BKOPS status level
*/
#define EXT_CSD_BKOPS_OK 0x0
#define EXT_CSD_BKOPS_NON_CRITICAL 0x1
#define EXT_CSD_BKOPS_PERF_IMPACTED 0x2
#define EXT_CSD_BKOPS_CRITICAL 0x3
/*
* BKOPS modes
*/
#define EXT_CSD_MANUAL_BKOPS_MASK 0x01
#define EXT_CSD_AUTO_BKOPS_MASK 0x02
/*
* Command Queue
*/
#define EXT_CSD_CMDQ_MODE_ENABLED (1<<0)
#define EXT_CSD_CMDQ_DEPTH_MASK 0x1F
#define EXT_CSD_CMDQ_SUPPORTED (1<<0)
/*
* MMC_SWITCH access modes
*/
#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */
#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */
#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
/*
* Erase/trim/discard
*/
#define MMC_ERASE_ARG 0x00000000
#define MMC_SECURE_ERASE_ARG 0x80000000
#define MMC_TRIM_ARG 0x00000001
#define MMC_DISCARD_ARG 0x00000003
#define MMC_SECURE_TRIM1_ARG 0x80000001
#define MMC_SECURE_TRIM2_ARG 0x80008000
#define MMC_SECURE_ARGS 0x80000000
#define MMC_TRIM_ARGS 0x00008001
/*
* Vendor definitions and structs
*/
#define MMC_SANDISK_HEALTH_REPORT 0x96C9D71C
#endif /* MMC_H */

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/*
* eMMC BIS driver for Nintendo Switch
*
* Copyright (c) 2019-2020 shchmue
* Copyright (c) 2019-2022 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <string.h>
#include <memory_map.h>
#include <mem/heap.h>
#include <sec/se.h>
#include <storage/emmc.h>
#include <storage/sd.h>
#include <storage/sdmmc.h>
#include <utils/types.h>
#define BIS_CLUSTER_SECTORS 32
#define BIS_CLUSTER_SIZE 16384
#define BIS_CACHE_MAX_ENTRIES 16384
#define BIS_CACHE_LOOKUP_TBL_EMPTY_ENTRY -1
typedef struct _cluster_cache_t
{
u32 cluster_idx; // Index of the cluster in the partition.
bool dirty; // Has been modified without write-back flag.
u8 data[BIS_CLUSTER_SIZE]; // The cached cluster itself. Aligned to 8 bytes for DMA engine.
} cluster_cache_t;
typedef struct _bis_cache_t
{
bool full;
bool enabled;
u32 dirty_cnt;
u32 top_idx;
u8 dma_buff[BIS_CLUSTER_SIZE]; // Aligned to 8 bytes for DMA engine.
cluster_cache_t clusters[];
} bis_cache_t;
static u8 ks_crypt = 0;
static u8 ks_tweak = 0;
static u32 emu_offset = 0;
static emmc_part_t *system_part = NULL;
static u32 *cache_lookup_tbl = (u32 *)NX_BIS_LOOKUP_ADDR;
static bis_cache_t *bis_cache = (bis_cache_t *)NX_BIS_CACHE_ADDR;
static int nx_emmc_bis_write_block(u32 sector, u32 count, void *buff, bool flush)
{
if (!system_part)
return 3; // Not ready.
int res;
u8 tweak[SE_KEY_128_SIZE] __attribute__((aligned(4)));
u32 cluster = sector / BIS_CLUSTER_SECTORS;
u32 aligned_sector = cluster * BIS_CLUSTER_SECTORS;
u32 sector_in_cluster = sector % BIS_CLUSTER_SECTORS;
u32 lookup_idx = cache_lookup_tbl[cluster];
bool is_cached = lookup_idx != (u32)BIS_CACHE_LOOKUP_TBL_EMPTY_ENTRY;
// Write to cached cluster.
if (is_cached)
{
if (buff)
memcpy(bis_cache->clusters[lookup_idx].data + sector_in_cluster * EMMC_BLOCKSIZE, buff, count * EMMC_BLOCKSIZE);
else
buff = bis_cache->clusters[lookup_idx].data;
if (!bis_cache->clusters[lookup_idx].dirty)
bis_cache->dirty_cnt++;
bis_cache->clusters[lookup_idx].dirty = true;
if (!flush)
return 0; // Success.
// Reset args to trigger a full cluster flush to emmc.
sector_in_cluster = 0;
sector = aligned_sector;
count = BIS_CLUSTER_SECTORS;
}
// Encrypt cluster.
if (!se_aes_xts_crypt_sec_nx(ks_tweak, ks_crypt, ENCRYPT, cluster, tweak, true, sector_in_cluster, bis_cache->dma_buff, buff, count * EMMC_BLOCKSIZE))
return 1; // Encryption error.
// If not reading from cache, do a regular read and decrypt.
if (!emu_offset)
res = emmc_part_write(system_part, sector, count, bis_cache->dma_buff);
else
res = sdmmc_storage_write(&sd_storage, emu_offset + system_part->lba_start + sector, count, bis_cache->dma_buff);
if (!res)
return 1; // R/W error.
// Mark cache entry not dirty if write succeeds.
if (is_cached)
{
bis_cache->clusters[lookup_idx].dirty = false;
bis_cache->dirty_cnt--;
}
return 0; // Success.
}
static void _nx_emmc_bis_cluster_cache_init(bool enable_cache)
{
u32 cache_lookup_tbl_size = (system_part->lba_end - system_part->lba_start + 1) / BIS_CLUSTER_SECTORS * sizeof(*cache_lookup_tbl);
// Clear cache header.
memset(bis_cache, 0, sizeof(bis_cache_t));
// Clear cluster lookup table.
memset(cache_lookup_tbl, BIS_CACHE_LOOKUP_TBL_EMPTY_ENTRY, cache_lookup_tbl_size);
// Enable cache.
bis_cache->enabled = enable_cache;
}
static void _nx_emmc_bis_flush_cache()
{
if (!bis_cache->enabled || !bis_cache->dirty_cnt)
return;
for (u32 i = 0; i < bis_cache->top_idx && bis_cache->dirty_cnt; i++)
{
if (bis_cache->clusters[i].dirty) {
nx_emmc_bis_write_block(bis_cache->clusters[i].cluster_idx * BIS_CLUSTER_SECTORS, BIS_CLUSTER_SECTORS, NULL, true);
bis_cache->dirty_cnt--;
}
}
_nx_emmc_bis_cluster_cache_init(true);
}
static int nx_emmc_bis_read_block_normal(u32 sector, u32 count, void *buff)
{
static u32 prev_cluster = -1;
static u32 prev_sector = 0;
static u8 tweak[SE_KEY_128_SIZE] __attribute__((aligned(4)));
int res;
bool regen_tweak = true;
u32 tweak_exp = 0;
u32 cluster = sector / BIS_CLUSTER_SECTORS;
u32 sector_in_cluster = sector % BIS_CLUSTER_SECTORS;
// If not reading from cache, do a regular read and decrypt.
if (!emu_offset)
res = emmc_part_read(system_part, sector, count, bis_cache->dma_buff);
else
res = sdmmc_storage_read(&sd_storage, emu_offset + system_part->lba_start + sector, count, bis_cache->dma_buff);
if (!res)
return 1; // R/W error.
if (prev_cluster != cluster) // Sector in different cluster than last read.
{
prev_cluster = cluster;
tweak_exp = sector_in_cluster;
}
else if (sector > prev_sector) // Sector in same cluster and past last sector.
{
// Calculates the new tweak using the saved one, reducing expensive _gf256_mul_x_le calls.
tweak_exp = sector - prev_sector - 1;
regen_tweak = false;
}
else // Sector in same cluster and before or same as last sector.
tweak_exp = sector_in_cluster;
// Maximum one cluster (1 XTS crypto block 16KB).
if (!se_aes_xts_crypt_sec_nx(ks_tweak, ks_crypt, DECRYPT, prev_cluster, tweak, regen_tweak, tweak_exp, buff, bis_cache->dma_buff, count * EMMC_BLOCKSIZE))
return 1; // R/W error.
prev_sector = sector + count - 1;
return 0; // Success.
}
static int nx_emmc_bis_read_block_cached(u32 sector, u32 count, void *buff)
{
int res;
u8 cache_tweak[SE_KEY_128_SIZE] __attribute__((aligned(4)));
u32 cluster = sector / BIS_CLUSTER_SECTORS;
u32 cluster_sector = cluster * BIS_CLUSTER_SECTORS;
u32 sector_in_cluster = sector % BIS_CLUSTER_SECTORS;
u32 lookup_idx = cache_lookup_tbl[cluster];
// Read from cached cluster.
if (lookup_idx != (u32)BIS_CACHE_LOOKUP_TBL_EMPTY_ENTRY)
{
memcpy(buff, bis_cache->clusters[lookup_idx].data + sector_in_cluster * EMMC_BLOCKSIZE, count * EMMC_BLOCKSIZE);
return 0; // Success.
}
// Flush cache if full.
if (bis_cache->top_idx >= BIS_CACHE_MAX_ENTRIES)
_nx_emmc_bis_flush_cache();
// Set new cached cluster parameters.
bis_cache->clusters[bis_cache->top_idx].cluster_idx = cluster;
bis_cache->clusters[bis_cache->top_idx].dirty = false;
cache_lookup_tbl[cluster] = bis_cache->top_idx;
// Read the whole cluster the sector resides in.
if (!emu_offset)
res = emmc_part_read(system_part, cluster_sector, BIS_CLUSTER_SECTORS, bis_cache->dma_buff);
else
res = sdmmc_storage_read(&sd_storage, emu_offset + system_part->lba_start + cluster_sector, BIS_CLUSTER_SECTORS, bis_cache->dma_buff);
if (!res)
return 1; // R/W error.
// Decrypt cluster.
if (!se_aes_xts_crypt_sec_nx(ks_tweak, ks_crypt, DECRYPT, cluster, cache_tweak, true, 0, bis_cache->dma_buff, bis_cache->dma_buff, BIS_CLUSTER_SIZE))
return 1; // Decryption error.
// Copy to cluster cache.
memcpy(bis_cache->clusters[bis_cache->top_idx].data, bis_cache->dma_buff, BIS_CLUSTER_SIZE);
memcpy(buff, bis_cache->dma_buff + sector_in_cluster * EMMC_BLOCKSIZE, count * EMMC_BLOCKSIZE);
// Increment cache count.
bis_cache->top_idx++;
return 0; // Success.
}
static int nx_emmc_bis_read_block(u32 sector, u32 count, void *buff)
{
if (!system_part)
return 3; // Not ready.
if (bis_cache->enabled)
return nx_emmc_bis_read_block_cached(sector, count, buff);
else
return nx_emmc_bis_read_block_normal(sector, count, buff);
}
int nx_emmc_bis_read(u32 sector, u32 count, void *buff)
{
u8 *buf = (u8 *)buff;
u32 curr_sct = sector;
while (count)
{
// Get sector index in cluster and use it as boundary check.
u32 cnt_max = (curr_sct % BIS_CLUSTER_SECTORS);
cnt_max = BIS_CLUSTER_SECTORS - cnt_max;
u32 sct_cnt = MIN(count, cnt_max); // Only allow cluster sized access.
if (nx_emmc_bis_read_block(curr_sct, sct_cnt, buf))
return 0;
count -= sct_cnt;
curr_sct += sct_cnt;
buf += sct_cnt * EMMC_BLOCKSIZE;
}
return 1;
}
int nx_emmc_bis_write(u32 sector, u32 count, void *buff)
{
u8 *buf = (u8 *)buff;
u32 curr_sct = sector;
while (count)
{
// Get sector index in cluster and use it as boundary check.
u32 cnt_max = (curr_sct % BIS_CLUSTER_SECTORS);
cnt_max = BIS_CLUSTER_SECTORS - cnt_max;
u32 sct_cnt = MIN(count, cnt_max); // Only allow cluster sized access.
if (nx_emmc_bis_write_block(curr_sct, sct_cnt, buf, false))
return 0;
count -= sct_cnt;
curr_sct += sct_cnt;
buf += sct_cnt * EMMC_BLOCKSIZE;
}
return 1;
}
void nx_emmc_bis_init(emmc_part_t *part, bool enable_cache, u32 emummc_offset)
{
system_part = part;
emu_offset = emummc_offset;
_nx_emmc_bis_cluster_cache_init(enable_cache);
if (!strcmp(part->name, "PRODINFO") || !strcmp(part->name, "PRODINFOF"))
{
ks_crypt = 0;
ks_tweak = 1;
}
else if (!strcmp(part->name, "SAFE"))
{
ks_crypt = 2;
ks_tweak = 3;
}
else if (!strcmp(part->name, "SYSTEM") || !strcmp(part->name, "USER"))
{
ks_crypt = 4;
ks_tweak = 5;
}
else
system_part = NULL;
}
void nx_emmc_bis_end()
{
_nx_emmc_bis_flush_cache();
system_part = NULL;
}

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/*
* Copyright (c) 2019 shchmue
* Copyright (c) 2019 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef NX_EMMC_BIS_H
#define NX_EMMC_BIS_H
#include <storage/emmc.h>
#include <storage/sdmmc.h>
typedef struct _nx_emmc_cal0_spk_t
{
u16 unk0;
u16 unk1;
u16 eq_bw_lop;
u16 eq_gn_lop;
u16 eq_fc_bp1;
u16 eq_bw_bp1;
u16 eq_gn_bp1;
u16 eq_fc_bp2;
u16 eq_bw_bp2;
u16 eq_gn_bp2;
u16 eq_fc_bp3;
u16 eq_bw_bp3;
u16 eq_gn_bp3;
u16 eq_fc_bp4;
u16 eq_bw_bp4;
u16 eq_gn_bp4;
u16 eq_fc_hip1;
u16 eq_gn_hip1;
u16 eq_fc_hip2;
u16 eq_bw_hip2;
u16 eq_gn_hip2;
u16 eq_pre_vol;
u16 eq_pst_vol;
u16 eq_ctrl2;
u16 eq_ctrl1;
u16 drc_agc_2;
u16 drc_agc_3;
u16 drc_agc_1;
u16 spk_vol;
u16 hp_vol;
u16 dac1_min_vol_spk;
u16 dac1_max_vol_spk;
u16 dac1_min_vol_hp;
u16 dac1_max_vol_hp;
u16 in1_in2;
u16 adc_vol_min;
u16 adc_vol_max;
u8 unk4[16];
} __attribute__((packed)) nx_emmc_cal0_spk_t;
typedef struct _nx_emmc_cal0_t
{
u32 magic; // 'CAL0'.
u32 version;
u32 body_size;
u16 model;
u16 update_cnt;
u8 pad_crc16_0[0x10];
u8 body_sha256[0x20];
char cfg_id1[0x1E];
u8 crc16_pad1[2];
u8 rsvd0[0x20];
u32 wlan_cc_num;
u32 wlan_cc_last;
char wlan_cc[128][3];
u8 crc16_pad2[8];
u8 wlan_mac[6];
u8 crc16_pad3[2];
u8 rsvd1[8];
u8 bd_mac[6];
u8 crc16_pad4[2];
u8 rsvd2[8];
u16 acc_offset[3];
u8 crc16_pad5[2];
u16 acc_scale[3];
u8 crc16_pad6[2];
u16 gyro_offset[3];
u8 crc16_pad7[2];
u16 gyro_scale[3];
u8 crc16_pad8[2];
char serial_number[0x18];
u8 crc16_pad9[8];
u8 ecc_p256_device_key[0x30];
u8 crc16_pad10[0x10];
u8 ecc_p256_device_cert[0x180];
u8 crc16_pad11[0x10];
u8 ecc_p233_device_key[0x30];
u8 crc16_pad12[0x10];
u8 ecc_p33_device_cert[0x180];
u8 crc16_pad13[0x10];
u8 ecc_p256_ticket_key[0x30];
u8 crc16_pad14[0x10];
u8 ecc_p256_ticket_cert[0x180];
u8 crc16_pad15[0x10];
u8 ecc_p233_ticket_key[0x30];
u8 crc16_pad16[0x10];
u8 ecc_p33_ticket_cert[0x180];
u8 crc16_pad17[0x10];
u8 ssl_key[0x110];
u8 crc16_pad18[0x10];
u32 ssl_cert_size;
u8 crc16_pad19[0xC];
u8 ssl_cert[0x800];
u8 ssl_sha256[0x20];
u8 random_number[0x1000];
u8 random_number_sha256[0x20];
u8 gc_key[0x110];
u8 crc16_pad20[0x10];
u8 gc_cert[0x400];
u8 gc_cert_sha256[0x20];
u8 rsa2048_eticket_key[0x220];
u8 crc16_pad21[0x10];
u8 rsa2048_eticket_cert[0x240];
u8 crc16_pad22[0x10];
char battery_lot[0x1E];
u8 crc16_pad23[2];
nx_emmc_cal0_spk_t spk_cal;
u8 spk_cal_rsvd[0x800 - sizeof(nx_emmc_cal0_spk_t)];
u8 crc16_pad24[0x10];
u32 region_code;
u8 crc16_pad25[0xC];
u8 amiibo_key[0x50];
u8 crc16_pad26[0x10];
u8 amiibo_ecqv_cert[0x14];
u8 crc16_pad27[0xC];
u8 amiibo_ecqdsa_cert[0x70];
u8 crc16_pad28[0x10];
u8 amiibo_ecqv_bls_key[0x40];
u8 crc16_pad29[0x10];
u8 amiibo_ecqv_bls_cert[0x20];
u8 crc16_pad30[0x10];
u8 amiibo_ecqv_bls_root_cert[0x90];
u8 crc16_pad31[0x10];
u32 product_model; // 1: Nx, 2: Copper, 4: Hoag.
u8 crc16_pad32[0xC];
u8 home_menu_scheme_main_color[6];
u8 crc16_pad33[0xA];
u32 lcd_bl_brightness_mapping[3]; // Floats. Normally 100%, 0% and 2%.
u8 crc16_pad34[0x4];
u8 ext_ecc_b233_device_key[0x50];
u8 crc16_pad35[0x10];
u8 ext_ecc_p256_eticket_key[0x50];
u8 crc16_pad36[0x10];
u8 ext_ecc_b233_eticket_key[0x50];
u8 crc16_pad37[0x10];
u8 ext_ecc_rsa2048_eticket_key[0x240];
u8 crc16_pad38[0x10];
u8 ext_ssl_key[0x130];
u8 crc16_pad39[0x10];
u8 ext_gc_key[0x130];
u8 crc16_pad40[0x10];
u32 lcd_vendor;
u8 crc16_pad41[0xC];
// 5.0.0 and up.
u8 ext_rsa2048_device_key[0x240];
u8 crc16_pad42[0x10];
u8 rsa2048_device_cert[0x240];
u8 crc16_pad43[0x10];
u8 usbc_pwr_src_circuit_ver;
u8 crc16_pad44[0xF];
// 9.0.0 and up.
u32 home_menu_scheme_sub_color;
u8 crc16_pad45[0xC];
u32 home_menu_scheme_bezel_color;
u8 crc16_pad46[0xC];
u32 home_menu_scheme_main_color1;
u8 crc16_pad47[0xC];
u32 home_menu_scheme_main_color2;
u8 crc16_pad48[0xC];
u32 home_menu_scheme_main_color3;
u8 crc16_pad49[0xC];
u8 analog_stick_type_l;
u8 crc16_pad50[0xF];
u8 analog_stick_param_l[0x12];
u8 crc16_pad51[0xE];
u8 analog_stick_cal_l[0x9];
u8 crc16_pad52[0x7];
u8 analog_stick_type_r;
u8 crc16_pad53[0xF];
u8 analog_stick_param_r[0x12];
u8 crc16_pad54[0xE];
u8 analog_stick_cal_r[0x9];
u8 crc16_pad55[0x7];
u8 console_6axis_sensor_type;
u8 crc16_pad56[0xF];
u8 console_6axis_sensor_hor_off[0x6];
u8 crc16_pad57[0xA];
// 6.0.0 and up.
u8 battery_ver;
u8 crc16_pad58[0xF];
// 10.0.0 and up.
u8 touch_ic_vendor_id;
u8 crc16_pad59[0xF];
// 9.0.0 and up.
u32 color_model;
u8 crc16_pad60[0xC];
// 10.0.0 and up.
u8 console_6axis_sensor_mount_type;
} __attribute__((packed)) nx_emmc_cal0_t;
int nx_emmc_bis_read(u32 sector, u32 count, void *buff);
int nx_emmc_bis_write(u32 sector, u32 count, void *buff);
void nx_emmc_bis_init(emmc_part_t *part, bool enable_cache, u32 emummc_offset);
void nx_emmc_bis_end();
#endif

86
emummc/source/fatal/bdk/storage/ramdisk.c vendored Normal file
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/*
* Ramdisk driver for Tegra X1
*
* Copyright (c) 2019-2021 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <string.h>
#include "ramdisk.h"
#include <libs/fatfs/diskio.h>
#include <libs/fatfs/ff.h>
#include <mem/heap.h>
#include <utils/types.h>
#include <memory_map.h>
static u32 disk_size = 0;
int ram_disk_init(void *ram_fs, u32 ramdisk_size)
{
int res = 0;
disk_size = ramdisk_size;
FATFS *ram_fatfs = (FATFS *)ram_fs;
// If ramdisk is not raw, format it.
if (ram_fs)
{
u8 *buf = malloc(0x400000);
// Set ramdisk size.
ramdisk_size >>= 9;
disk_set_info(DRIVE_RAM, SET_SECTOR_COUNT, &ramdisk_size);
// Unmount ramdisk.
f_mount(NULL, "ram:", 1);
// Format as exFAT w/ 32KB cluster with no MBR.
res = f_mkfs("ram:", FM_EXFAT | FM_SFD, RAMDISK_CLUSTER_SZ, buf, 0x400000);
// Mount ramdisk.
if (!res)
res = f_mount(ram_fatfs, "ram:", 1);
free(buf);
}
return res;
}
int ram_disk_read(u32 sector, u32 sector_count, void *buf)
{
u32 sector_off = RAM_DISK_ADDR + (sector << 9);
u32 bytes_count = sector_count << 9;
if ((sector_off - RAM_DISK_ADDR) > disk_size)
return 1;
memcpy(buf, (void *)sector_off, bytes_count);
return 0;
}
int ram_disk_write(u32 sector, u32 sector_count, const void *buf)
{
u32 sector_off = RAM_DISK_ADDR + (sector << 9);
u32 bytes_count = sector_count << 9;
if ((sector_off - RAM_DISK_ADDR) > disk_size)
return 1;
memcpy((void *)sector_off, buf, bytes_count);
return 0;
}

30
emummc/source/fatal/bdk/storage/ramdisk.h vendored Normal file
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/*
* Ramdisk driver for Tegra X1
*
* Copyright (c) 2019-2021 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef RAM_DISK_H
#define RAM_DISK_H
#include <utils/types.h>
#define RAMDISK_CLUSTER_SZ 32768
int ram_disk_init(void *ram_fs, u32 ramdisk_size);
int ram_disk_read(u32 sector, u32 sector_count, void *buf);
int ram_disk_write(u32 sector, u32 sector_count, const void *buf);
#endif

295
emummc/source/fatal/bdk/storage/sd.c vendored Normal file
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/*
* Copyright (c) 2018 naehrwert
* Copyright (c) 2018-2023 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <storage/sd.h>
#include <storage/sdmmc.h>
#include <storage/sdmmc_driver.h>
#include <gfx_utils.h>
#include <libs/fatfs/ff.h>
#include <mem/heap.h>
#ifndef BDK_SDMMC_UHS_DDR200_SUPPORT
#define SD_DEFAULT_SPEED SD_UHS_SDR104
#else
#define SD_DEFAULT_SPEED SD_UHS_DDR208
#endif
static bool sd_mounted = false;
static bool sd_init_done = false;
static bool insertion_event = false;
static u16 sd_errors[3] = { 0 }; // Init and Read/Write errors.
static u32 sd_mode = SD_DEFAULT_SPEED;
sdmmc_t sd_sdmmc;
sdmmc_storage_t sd_storage;
FATFS sd_fs;
void sd_error_count_increment(u8 type)
{
switch (type)
{
case SD_ERROR_INIT_FAIL:
sd_errors[0]++;
break;
case SD_ERROR_RW_FAIL:
sd_errors[1]++;
break;
case SD_ERROR_RW_RETRY:
sd_errors[2]++;
break;
}
}
u16 *sd_get_error_count()
{
return sd_errors;
}
bool sd_get_card_removed()
{
if (insertion_event && !sdmmc_get_sd_inserted())
return true;
return false;
}
bool sd_get_card_initialized()
{
return sd_init_done;
}
bool sd_get_card_mounted()
{
return sd_mounted;
}
u32 sd_get_mode()
{
return sd_mode;
}
int sd_init_retry(bool power_cycle)
{
u32 bus_width = SDMMC_BUS_WIDTH_4;
#ifndef BDK_SDMMC_UHS_DDR200_SUPPORT
u32 type = SDHCI_TIMING_UHS_SDR104;
#else
u32 type = SDHCI_TIMING_UHS_DDR200;
#endif
// Power cycle SD card.
if (power_cycle)
{
sd_mode--;
sdmmc_storage_end(&sd_storage);
}
// Get init parameters.
switch (sd_mode)
{
case SD_INIT_FAIL: // Reset to max.
return 0;
case SD_1BIT_HS25:
bus_width = SDMMC_BUS_WIDTH_1;
type = SDHCI_TIMING_SD_HS25;
break;
case SD_4BIT_HS25:
type = SDHCI_TIMING_SD_HS25;
break;
case SD_UHS_SDR82:
type = SDHCI_TIMING_UHS_SDR82;
break;
case SD_UHS_SDR104:
type = SDHCI_TIMING_UHS_SDR104;
break;
#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT
case SD_UHS_DDR208:
type = SDHCI_TIMING_UHS_DDR200;
break;
#endif
default:
sd_mode = SD_DEFAULT_SPEED;
break;
}
int res = sdmmc_storage_init_sd(&sd_storage, &sd_sdmmc, bus_width, type);
if (res)
{
sd_init_done = true;
insertion_event = true;
}
else
sd_init_done = false;
return res;
}
bool sd_initialize(bool power_cycle)
{
if (power_cycle)
sdmmc_storage_end(&sd_storage);
int res = !sd_init_retry(false);
while (true)
{
if (!res)
return true;
else if (!sdmmc_get_sd_inserted()) // SD Card is not inserted.
{
sd_mode = SD_DEFAULT_SPEED;
break;
}
else
{
sd_errors[SD_ERROR_INIT_FAIL]++;
if (sd_mode == SD_INIT_FAIL)
break;
else
res = !sd_init_retry(true);
}
}
sdmmc_storage_end(&sd_storage);
return false;
}
bool sd_mount()
{
if (sd_init_done && sd_mounted)
return true;
int res = 0;
if (!sd_init_done)
res = !sd_initialize(false);
if (res)
{
gfx_con.mute = false;
EPRINTF("Failed to init SD card.");
if (!sdmmc_get_sd_inserted())
EPRINTF("Make sure that it is inserted.");
else
EPRINTF("SD Card Reader is not properly seated!");
}
else
{
if (!sd_mounted)
res = f_mount(&sd_fs, "0:", 1); // Volume 0 is SD.
if (res == FR_OK)
{
sd_mounted = true;
return true;
}
else
{
gfx_con.mute = false;
EPRINTFARGS("Failed to mount SD card (FatFS Error %d).\nMake sure that a FAT partition exists..", res);
}
}
return false;
}
static void _sd_deinit(bool deinit)
{
if (deinit)
{
insertion_event = false;
if (sd_mode == SD_INIT_FAIL)
sd_mode = SD_DEFAULT_SPEED;
}
if (sd_init_done)
{
if (sd_mounted)
f_mount(NULL, "0:", 1); // Volume 0 is SD.
if (deinit)
{
sdmmc_storage_end(&sd_storage);
sd_init_done = false;
}
}
sd_mounted = false;
}
void sd_unmount() { _sd_deinit(false); }
void sd_end() { _sd_deinit(true); }
bool sd_is_gpt()
{
return sd_fs.part_type;
}
void *sd_file_read(const char *path, u32 *fsize)
{
FIL fp;
if (!sd_get_card_mounted())
return NULL;
if (f_open(&fp, path, FA_READ) != FR_OK)
return NULL;
u32 size = f_size(&fp);
if (fsize)
*fsize = size;
void *buf = malloc(size);
if (f_read(&fp, buf, size, NULL) != FR_OK)
{
free(buf);
f_close(&fp);
return NULL;
}
f_close(&fp);
return buf;
}
int sd_save_to_file(const void *buf, u32 size, const char *filename)
{
FIL fp;
u32 res = 0;
if (!sd_get_card_mounted())
return FR_DISK_ERR;
res = f_open(&fp, filename, FA_CREATE_ALWAYS | FA_WRITE);
if (res)
{
EPRINTFARGS("Error (%d) creating file\n%s.\n", res, filename);
return res;
}
f_write(&fp, buf, size, NULL);
f_close(&fp);
return 0;
}

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emummc/source/fatal/bdk/storage/sd.h vendored Normal file
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/*
* Copyright (c) 2018 naehrwert
* Copyright (c) 2018-2023 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SD_H
#define SD_H
#include <storage/sdmmc.h>
#include <storage/sdmmc_driver.h>
#include <libs/fatfs/ff.h>
#define SD_BLOCKSIZE SDMMC_DAT_BLOCKSIZE
enum
{
SD_INIT_FAIL = 0,
SD_1BIT_HS25 = 1,
SD_4BIT_HS25 = 2,
SD_UHS_SDR82 = 3,
SD_UHS_SDR104 = 4,
#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT
SD_UHS_DDR208 = 5
#endif
};
enum
{
SD_ERROR_INIT_FAIL = 0,
SD_ERROR_RW_FAIL = 1,
SD_ERROR_RW_RETRY = 2
};
extern sdmmc_t sd_sdmmc;
extern sdmmc_storage_t sd_storage;
extern FATFS sd_fs;
void sd_error_count_increment(u8 type);
u16 *sd_get_error_count();
bool sd_get_card_removed();
bool sd_get_card_initialized();
bool sd_get_card_mounted();
u32 sd_get_mode();
int sd_init_retry(bool power_cycle);
bool sd_initialize(bool power_cycle);
bool sd_mount();
void sd_unmount();
void sd_end();
bool sd_is_gpt();
void *sd_file_read(const char *path, u32 *fsize);
int sd_save_to_file(const void *buf, u32 size, const char *filename);
#endif

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emummc/source/fatal/bdk/storage/sd_def.h vendored Normal file
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/*
* Copyright (c) 2005-2007 Pierre Ossman, All Rights Reserved.
* Copyright (c) 2018-2023 CTCaer
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or (at
* your option) any later version.
*/
#ifndef SD_DEF_H
#define SD_DEF_H
/* SD commands type argument response */
/* class 0 */
/* This is basically the same command as for MMC with some quirks. */
#define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */
#define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */
#define SD_SWITCH_VOLTAGE 11 /* ac R1 */
/* class 10 */
#define SD_SWITCH 6 /* adtc [31:0] See below R1 */
/* class 5 */
#define SD_ERASE_WR_BLK_START 32 /* ac [31:0] data addr R1 */
#define SD_ERASE_WR_BLK_END 33 /* ac [31:0] data addr R1 */
/* Application commands */
#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
#define SD_APP_SD_STATUS 13 /* adtc R1 */
#define SD_APP_SEND_NUM_WR_BLKS 22 /* adtc R1 */
#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */
#define SD_APP_SET_CLR_CARD_DETECT 42 /* adtc R1 */
#define SD_APP_SEND_SCR 51 /* adtc R1 */
/* Application secure commands */
#define SD_APP_SECURE_READ_MULTI_BLOCK 18 /* adtc R1 */
#define SD_APP_SECURE_WRITE_MULTI_BLOCK 25 /* adtc R1 */
#define SD_APP_SECURE_WRITE_MKB 26 /* adtc R1 */
#define SD_APP_SECURE_ERASE 38 /* adtc R1b */
#define SD_APP_GET_MKB 43 /* adtc [31:0] See below R1 */
#define SD_APP_GET_MID 44 /* adtc R1 */
#define SD_APP_SET_CER_RN1 45 /* adtc R1 */
#define SD_APP_GET_CER_RN2 46 /* adtc R1 */
#define SD_APP_SET_CER_RES2 47 /* adtc R1 */
#define SD_APP_GET_CER_RES1 48 /* adtc R1 */
#define SD_APP_CHANGE_SECURE_AREA 49 /* adtc R1b */
/* OCR bit definitions */
#define SD_OCR_VDD_18 (1U << 7) /* VDD voltage 1.8 */
#define SD_VHS_27_36 (1U << 8) /* VDD voltage 2.7 ~ 3.6 */
#define SD_OCR_VDD_32_33 (1U << 20) /* VDD voltage 3.2 ~ 3.3 */
#define SD_OCR_S18R (1U << 24) /* 1.8V switching request */
#define SD_ROCR_S18A SD_OCR_S18R /* 1.8V switching accepted by card */
#define SD_OCR_XPC (1U << 28) /* SDXC power control */
#define SD_OCR_CCS (1U << 30) /* Card Capacity Status */
#define SD_OCR_BUSY (1U << 31) /* Card Power up Status */
/*
* SD_SWITCH argument format:
*
* [31] Check (0) or switch (1)
* [30:24] Reserved (0)
* [23:20] Function group 6
* [19:16] Function group 5
* [15:12] Function group 4
* [11:8] Function group 3
* [7:4] Function group 2
* [3:0] Function group 1
*/
/*
* SD_SEND_IF_COND argument format:
*
* [31:12] Reserved (0)
* [11:8] Host Voltage Supply Flags
* [7:0] Check Pattern (0xAA)
*/
/*
* SD_APP_GET_MKB argument format:
*
* [31:24] Number of blocks to read (512 block size)
* [23:16] MKB ID
* [15:0] Block offset
*/
/*
* SCR field definitions
*/
#define SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */
#define SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */
#define SCR_SPEC_VER_2 2 /* Implements system specification 2.00-3.0X */
#define SD_SCR_BUS_WIDTH_1 (1U << 0)
#define SD_SCR_BUS_WIDTH_4 (1U << 2)
/*
* SD bus widths
*/
#define SD_BUS_WIDTH_1 0
#define SD_BUS_WIDTH_4 2
/*
* SD bus speeds
*/
#define UHS_SDR12_BUS_SPEED 0
#define HIGH_SPEED_BUS_SPEED 1
#define UHS_SDR25_BUS_SPEED 1
#define UHS_SDR50_BUS_SPEED 2
#define UHS_SDR104_BUS_SPEED 3
#define UHS_DDR50_BUS_SPEED 4
#define HS400_BUS_SPEED 5
#define SD_MODE_HIGH_SPEED (1U << HIGH_SPEED_BUS_SPEED)
#define SD_MODE_UHS_SDR12 (1U << UHS_SDR12_BUS_SPEED)
#define SD_MODE_UHS_SDR25 (1U << UHS_SDR25_BUS_SPEED)
#define SD_MODE_UHS_SDR50 (1U << UHS_SDR50_BUS_SPEED)
#define SD_MODE_UHS_SDR104 (1U << UHS_SDR104_BUS_SPEED)
#define SD_MODE_UHS_DDR50 (1U << UHS_DDR50_BUS_SPEED)
#define SD_SET_DRIVER_TYPE_B 0
#define SD_SET_DRIVER_TYPE_A 1
#define SD_SET_DRIVER_TYPE_C 2
#define SD_SET_DRIVER_TYPE_D 3
#define SD_DRIVER_TYPE_B (1U << SD_SET_DRIVER_TYPE_B)
#define SD_DRIVER_TYPE_A (1U << SD_SET_DRIVER_TYPE_A)
#define SD_DRIVER_TYPE_C (1U << SD_SET_DRIVER_TYPE_C)
#define SD_DRIVER_TYPE_D (1U << SD_SET_DRIVER_TYPE_D)
#define SD_SET_POWER_LIMIT_0_72 0
#define SD_SET_POWER_LIMIT_1_44 1
#define SD_SET_POWER_LIMIT_2_16 2
#define SD_SET_POWER_LIMIT_2_88 3
#define SD_MAX_POWER_0_72 (1U << SD_SET_POWER_LIMIT_0_72)
#define SD_MAX_POWER_1_44 (1U << SD_SET_POWER_LIMIT_1_44)
#define SD_MAX_POWER_2_16 (1U << SD_SET_POWER_LIMIT_2_16)
#define SD_MAX_POWER_2_88 (1U << SD_SET_POWER_LIMIT_2_88)
#define SD_SET_CMD_SYSTEM_DEF 0
#define SD_SET_CMD_SYSTEM_MEC 1
#define SD_SET_CMD_SYSTEM_OTP 3
#define SD_SET_CMD_SYSTEM_OSD 3
#define SD_SET_CMD_SYSTEM_VND 14
#define UHS_DDR200_BUS_SPEED SD_SET_CMD_SYSTEM_VND
#define SD_CMD_SYSTEM_DEF (1U << SD_SET_CMD_SYSTEM_DEF)
#define SD_CMD_SYSTEM_MEC (1U << SD_SET_CMD_SYSTEM_MEC)
#define SD_CMD_SYSTEM_OTP (1U << SD_SET_CMD_SYSTEM_OTP)
#define SD_CMD_SYSTEM_OSD (1U << SD_SET_CMD_SYSTEM_OSD)
#define SD_CMD_SYSTEM_VND (1U << SD_SET_CMD_SYSTEM_VND)
#define SD_MODE_UHS_DDR200 SD_CMD_SYSTEM_VND
/*
* SD_SWITCH mode
*/
#define SD_SWITCH_CHECK 0
#define SD_SWITCH_SET 1
/*
* SD_SWITCH function groups
*/
#define SD_SWITCH_GRP_ACCESS 0
#define SD_SWITCH_GRP_CMDSYS 1
#define SD_SWITCH_GRP_DRVSTR 2
#define SD_SWITCH_GRP_PWRLIM 3
/*
* SD_SWITCH access modes
*/
#define SD_SWITCH_ACCESS_DEF 0
#define SD_SWITCH_ACCESS_HS 1
#endif /* SD_DEF_H */

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/*
* Copyright (c) 2018 naehrwert
* Copyright (c) 2018-2022 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _SDMMC_H_
#define _SDMMC_H_
#include <utils/types.h>
#include <storage/sd_def.h>
#include <storage/sdmmc_driver.h>
#define SDMMC_CMD_BLOCKSIZE 64
#define SDMMC_DAT_BLOCKSIZE 512
extern u32 sd_power_cycle_time_start;
typedef enum _sdmmc_type
{
MMC_SD = 0,
MMC_EMMC = 1,
EMMC_GPP = 0,
EMMC_BOOT0 = 1,
EMMC_BOOT1 = 2,
EMMC_RPMB = 3
} sdmmc_type;
typedef struct _mmc_sandisk_advanced_report_t
{
u32 power_inits;
u32 max_erase_cycles_sys;
u32 max_erase_cycles_slc;
u32 max_erase_cycles_mlc;
u32 min_erase_cycles_sys;
u32 min_erase_cycles_slc;
u32 min_erase_cycles_mlc;
u32 max_erase_cycles_euda;
u32 min_erase_cycles_euda;
u32 avg_erase_cycles_euda;
u32 read_reclaim_cnt_euda;
u32 bad_blocks_euda;
u32 pre_eol_euda;
u32 pre_eol_sys;
u32 pre_eol_mlc;
u32 uncorrectable_ecc;
u32 temperature_now;
u32 temperature_min;
u32 temperature_max;
u32 health_pct_euda;
u32 health_pct_sys;
u32 health_pct_mlc;
u32 unk0;
u32 unk1;
u32 unk2;
u32 reserved[78];
} mmc_sandisk_advanced_report_t;
typedef struct _mmc_sandisk_report_t
{
u32 avg_erase_cycles_sys;
u32 avg_erase_cycles_slc;
u32 avg_erase_cycles_mlc;
u32 read_reclaim_cnt_sys;
u32 read_reclaim_cnt_slc;
u32 read_reclaim_cnt_mlc;
u32 bad_blocks_factory;
u32 bad_blocks_sys;
u32 bad_blocks_slc;
u32 bad_blocks_mlc;
u32 fw_updates_cnt;
u8 fw_update_date[12];
u8 fw_update_time[8];
u32 total_writes_100mb;
u32 vdrops;
u32 vdroops;
u32 vdrops_failed_data_rec;
u32 vdrops_data_rec_ops;
u32 total_writes_slc_100mb;
u32 total_writes_mlc_100mb;
u32 mlc_bigfile_mode_limit_exceeded;
u32 avg_erase_cycles_hybrid;
mmc_sandisk_advanced_report_t advanced;
} mmc_sandisk_report_t;
typedef struct _mmc_cid
{
u32 manfid;
u8 prod_name[8];
u32 serial;
u16 oemid;
u16 year;
u8 prv;
u8 hwrev;
u8 fwrev;
u8 month;
} mmc_cid_t;
typedef struct _mmc_csd
{
u8 structure;
u8 mmca_vsn;
u16 cmdclass;
u32 c_size;
u32 r2w_factor;
u32 read_blkbits;
u32 capacity;
u8 write_protect;
u16 busspeed;
} mmc_csd_t;
typedef struct _mmc_ext_csd
{
//u8 bkops; /* background support bit */
//u8 bkops_en; /* manual bkops enable bit */
//u8 bkops_status; /* 246 */
u8 rev;
u8 ext_struct; /* 194 */
u8 card_type; /* 196 */
u8 pre_eol_info;
u8 dev_life_est_a;
u8 dev_life_est_b;
u8 boot_mult;
u8 rpmb_mult;
u16 dev_version;
u32 cache_size;
u32 max_enh_mult;
} mmc_ext_csd_t;
typedef struct _sd_scr
{
u8 sda_vsn;
u8 sda_spec3;
u8 bus_widths;
u8 cmds;
} sd_scr_t;
typedef struct _sd_ssr
{
u8 bus_width;
u8 speed_class;
u8 uhs_grade;
u8 video_class;
u8 app_class;
u8 au_size;
u8 uhs_au_size;
u32 protected_size;
} sd_ssr_t;
/*! SDMMC storage context. */
typedef struct _sdmmc_storage_t
{
sdmmc_t *sdmmc;
u32 rca;
int has_sector_access;
u32 sec_cnt;
int is_low_voltage;
u32 partition;
int initialized;
u32 card_power_limit;
u8 raw_cid[0x10];
u8 raw_csd[0x10];
u8 raw_scr[8];
u8 raw_ssr[0x40];
mmc_cid_t cid;
mmc_csd_t csd;
mmc_ext_csd_t ext_csd;
sd_scr_t scr;
sd_ssr_t ssr;
} sdmmc_storage_t;
typedef struct _sd_func_modes_t
{
u16 access_mode;
u16 cmd_system;
u16 driver_strength;
u16 power_limit;
} sd_func_modes_t;
int sdmmc_storage_end(sdmmc_storage_t *storage);
int sdmmc_storage_read(sdmmc_storage_t *storage, u32 sector, u32 num_sectors, void *buf);
int sdmmc_storage_write(sdmmc_storage_t *storage, u32 sector, u32 num_sectors, void *buf);
int sdmmc_storage_init_mmc(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 bus_width, u32 type);
int sdmmc_storage_set_mmc_partition(sdmmc_storage_t *storage, u32 partition);
void sdmmc_storage_init_wait_sd();
int sdmmc_storage_init_sd(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 bus_width, u32 type);
int sdmmc_storage_init_gc(sdmmc_storage_t *storage, sdmmc_t *sdmmc);
int sdmmc_storage_execute_vendor_cmd(sdmmc_storage_t *storage, u32 arg);
int sdmmc_storage_vendor_sandisk_report(sdmmc_storage_t *storage, void *buf);
int mmc_storage_get_ext_csd(sdmmc_storage_t *storage, void *buf);
int sd_storage_get_fmodes(sdmmc_storage_t *storage, u8 *buf, sd_func_modes_t *functions);
int sd_storage_get_scr(sdmmc_storage_t *storage, u8 *buf);
int sd_storage_get_ssr(sdmmc_storage_t *storage, u8 *buf);
u32 sd_storage_get_ssr_au(sdmmc_storage_t *storage);
#endif

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/*
* Copyright (c) 2018 naehrwert
* Copyright (c) 2018-2023 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _SDMMC_DRIVER_H_
#define _SDMMC_DRIVER_H_
#include <utils/types.h>
#include <storage/sdmmc_t210.h>
/*! SDMMC controller IDs. */
#define SDMMC_1 0 // Version 4.00.
#define SDMMC_2 1 // Version 5.0 + SW CQE + Enhanced Strobe.
#define SDMMC_3 2 // Version 4.00.
#define SDMMC_4 3 // Version 5.0 + SW CQE + Enhanced Strobe.
/*! SDMMC power types. */
#define SDMMC_POWER_OFF 0
#define SDMMC_POWER_1_8 1
#define SDMMC_POWER_3_3 2
/*! SDMMC response types. */
#define SDMMC_RSP_TYPE_0 0
#define SDMMC_RSP_TYPE_1 1
#define SDMMC_RSP_TYPE_2 2
#define SDMMC_RSP_TYPE_3 3
#define SDMMC_RSP_TYPE_4 4
#define SDMMC_RSP_TYPE_5 5
/*! SDMMC bus widths. */
#define SDMMC_BUS_WIDTH_1 0
#define SDMMC_BUS_WIDTH_4 1
#define SDMMC_BUS_WIDTH_8 2
/*! SDMMC mask interrupt status. */
#define SDMMC_MASKINT_MASKED 0
#define SDMMC_MASKINT_NOERROR 1
#define SDMMC_MASKINT_ERROR 2
/*! SDMMC present state. 0x24. */
#define SDHCI_CMD_INHIBIT BIT(0)
#define SDHCI_DATA_INHIBIT BIT(1)
#define SDHCI_DAT_LINE_ACTIVE BIT(2)
#define SDHCI_RETUNING_REQUEST BIT(3)
#define SDHCI_EMMC_LINE_LVL_MASK (0xFU << 4)
#define SDHCI_DATA_4_LVL BIT(4) // eMMC only.
#define SDHCI_DATA_5_LVL BIT(5) // eMMC only.
#define SDHCI_DATA_6_LVL BIT(6) // eMMC only.
#define SDHCI_DATA_7_LVL BIT(7) // eMMC only.
#define SDHCI_DOING_WRITE BIT(8)
#define SDHCI_DOING_READ BIT(9) // SD only.
#define SDHCI_SPACE_AVAILABLE BIT(10) // Write buffer empty.
#define SDHCI_DATA_AVAILABLE BIT(11) // Read buffer has data.
#define SDHCI_CARD_PRESENT BIT(16)
#define SDHCI_CD_STABLE BIT(17)
#define SDHCI_CD_LVL BIT(18)
#define SDHCI_WRITE_PROTECT BIT(19)
#define SDHCI_DATA_LVL_MASK 0xF00000
#define SDHCI_DATA_0_LVL BIT(20)
#define SDHCI_DATA_1_LVL BIT(21)
#define SDHCI_DATA_2_LVL BIT(22)
#define SDHCI_DATA_3_LVL BIT(23)
#define SDHCI_CMD_LVL BIT(24)
/*! SDMMC transfer mode. 0x0C. */
#define SDHCI_TRNS_DMA BIT(0)
#define SDHCI_TRNS_BLK_CNT_EN BIT(1)
#define SDHCI_TRNS_AUTO_CMD12 (1U << 2)
#define SDHCI_TRNS_AUTO_CMD23 (2U << 2)
#define SDHCI_TRNS_WRITE (0U << 4)
#define SDHCI_TRNS_READ BIT(4)
#define SDHCI_TRNS_MULTI BIT(5)
#define SDHCI_TRNS_RTYPE_R1 (0U << 6)
#define SDHCI_TRNS_RTYPE_R5 BIT(6)
#define SDHCI_TRNS_RSP_ERR_CHK BIT(7)
#define SDHCI_TRNS_RSP_INT_DIS BIT(8)
/*! SDMMC command. 0x0E. */
#define SDHCI_CMD_RESP_MASK 0x3
#define SDHCI_CMD_RESP_NO_RESP 0x0
#define SDHCI_CMD_RESP_LEN136 0x1
#define SDHCI_CMD_RESP_LEN48 0x2
#define SDHCI_CMD_RESP_LEN48_BUSY 0x3
#define SDHCI_CMD_CRC BIT(3)
#define SDHCI_CMD_INDEX BIT(4)
#define SDHCI_CMD_DATA BIT(5)
#define SDHCI_CMD_TYPE_NORMAL (0U << 6)
#define SDHCI_CMD_TYPE_SUSPEND (1U << 6)
#define SDHCI_CMD_TYPE_RESUME (2U << 6)
#define SDHCI_CMD_TYPE_ABORT (3U << 6)
#define SDHCI_CMD_IDX(cmd) ((cmd) << 8)
/*! SDMMC host control. 0x28. */
#define SDHCI_CTRL_LED BIT(0)
#define SDHCI_CTRL_4BITBUS BIT(1) // SD only.
#define SDHCI_CTRL_HISPD BIT(2) // SD only.
#define SDHCI_CTRL_DMA_MASK (3U << 3)
#define SDHCI_CTRL_SDMA (0U << 3)
#define SDHCI_CTRL_ADMA1 (1U << 3)
#define SDHCI_CTRL_ADMA32 (2U << 3)
#define SDHCI_CTRL_ADMA64 (3U << 3)
#define SDHCI_CTRL_8BITBUS BIT(5) // eMMC only (or UHS-II).
#define SDHCI_CTRL_CDTEST_INS BIT(6)
#define SDHCI_CTRL_CDTEST_EN BIT(7)
/*! SDMMC host control 2. 0x3E. */
#define SDHCI_CTRL_UHS_MASK 0x7
#define SDHCI_CTRL_VDD_180 BIT(3)
#define SDHCI_CTRL_DRV_TYPE_MASK (3U << 4)
#define SDHCI_CTRL_DRV_TYPE_B (0U << 4)
#define SDHCI_CTRL_DRV_TYPE_A (1U << 4)
#define SDHCI_CTRL_DRV_TYPE_C (2U << 4)
#define SDHCI_CTRL_DRV_TYPE_D (3U << 4)
#define SDHCI_CTRL_DRV_TYPE(type) ((type) << 4)
#define SDHCI_CTRL_EXEC_TUNING BIT(6)
#define SDHCI_CTRL_TUNED_CLK_SHIFT 7
#define SDHCI_CTRL_TUNED_CLK BIT(7)
#define SDHCI_HOST_VERSION_4_EN BIT(12)
#define SDHCI_ADDRESSING_64BIT_EN BIT(13)
#define SDHCI_CTRL_PRESET_VAL_EN BIT(15)
/*! SDMMC power control. 0x29. */
#define SDHCI_POWER_ON BIT(0)
#define SDHCI_POWER_180 (5U << 1)
#define SDHCI_POWER_300 (6U << 1)
#define SDHCI_POWER_330 (7U << 1)
#define SDHCI_POWER_MASK 0xF1 // UHS-II only.
/*! SDMMC clock control. 0x2C. */
#define SDHCI_CLOCK_INT_EN BIT(0) // Internal Clock.
#define SDHCI_CLOCK_INT_STABLE BIT(1) // Internal Clock Stable.
#define SDHCI_CLOCK_CARD_EN BIT(2)
#define SDHCI_PROG_CLOCK_MODE BIT(5)
#define SDHCI_DIV_HI_SHIFT 6
#define SDHCI_DIV_HI_MASK (3U << SDHCI_DIV_HI_SHIFT)
#define SDHCI_DIV_LO_SHIFT 8
#define SDHCI_DIV_MASK (0xFFU << SDHCI_DIV_LO_SHIFT)
/*! SDMMC software reset. 0x2F. */
#define SDHCI_RESET_ALL BIT(0)
#define SDHCI_RESET_CMD BIT(1)
#define SDHCI_RESET_DATA BIT(2)
/*! SDMMC interrupt status and control. 0x30/0x34. */
#define SDHCI_INT_RESPONSE BIT(0)
#define SDHCI_INT_DATA_END BIT(1)
#define SDHCI_INT_BLK_GAP BIT(2)
#define SDHCI_INT_DMA_END BIT(3)
#define SDHCI_INT_SPACE_AVAIL BIT(4) // Write buffer empty.
#define SDHCI_INT_DATA_AVAIL BIT(5) // Read buffer has data.
#define SDHCI_INT_CARD_INSERT BIT(6)
#define SDHCI_INT_CARD_REMOVE BIT(7)
#define SDHCI_INT_CARD_INT BIT(8)
#define SDHCI_INT_RETUNE BIT(12)
#define SDHCI_INT_ERROR BIT(15)
/*! SDMMC error interrupt status and control. 0x32/0x36. */
#define SDHCI_ERR_INT_TIMEOUT BIT(0)
#define SDHCI_ERR_INT_CRC BIT(1)
#define SDHCI_ERR_INT_END_BIT BIT(2)
#define SDHCI_ERR_INT_INDEX BIT(3)
#define SDHCI_ERR_INT_DATA_TIMEOUT BIT(4)
#define SDHCI_ERR_INT_DATA_CRC BIT(5)
#define SDHCI_ERR_INT_DATA_END_BIT BIT(6)
#define SDHCI_ERR_INT_BUS_POWER BIT(7)
#define SDHCI_ERR_INT_AUTO_CMD12 BIT(8)
#define SDHCI_ERR_INT_ADMA BIT(9)
#define SDHCI_ERR_INT_TUNE BIT(10)
#define SDHCI_ERR_INT_RSP BIT(11)
#define SDHCI_ERR_INT_TARGET_RSP BIT(12)
#define SDHCI_ERR_INT_SPI BIT(13)
#define SDHCI_ERR_INT_VND_BOOT_TMO BIT(14)
#define SDHCI_ERR_INT_VND_BOOT_ACK BIT(15)
#define SDHCI_ERR_INT_ALL_EXCEPT_ADMA_BUSPWR \
(SDHCI_ERR_INT_AUTO_CMD12 | SDHCI_ERR_INT_DATA_END_BIT | \
SDHCI_ERR_INT_DATA_CRC | SDHCI_ERR_INT_DATA_TIMEOUT | \
SDHCI_ERR_INT_INDEX | SDHCI_ERR_INT_END_BIT | \
SDHCI_ERR_INT_CRC | SDHCI_ERR_INT_TIMEOUT)
/*! Host Capability 1. 0x40. */
#define SDHCI_CAP_TM_CLK_FREQ_MASK 0x3F
#define SDHCI_CAP_TM_UNIT_MHZ BIT(7)
#define SDHCI_CAP_BASE_CLK_FREQ_MASK (0xFFU << 8)
#define SDHCI_CAP_MAX_BLK_LEN_MASK (3U << 16)
#define SDHCI_CAP_EMMC_8BIT BIT(18)
#define SDHCI_CAP_ADMA2 BIT(19)
#define SDHCI_CAP_HISPD BIT(21)
#define SDHCI_CAP_SDMA BIT(22)
#define SDHCI_CAP_SUSPEND_RESUME BIT(23)
#define SDHCI_CAP_3_3_V BIT(24)
#define SDHCI_CAP_3_0_V BIT(25)
#define SDHCI_CAP_1_8_V BIT(26)
#define SDHCI_CAP_64BIT BIT(28)
#define SDHCI_CAP_ASYNC_INT BIT(29)
#define SDHCI_CAP_SLOT_TYPE_MASK (3U << 30)
#define SDHCI_CAP_SLOT_TYPE_REMOVABLE (0U << 30)
#define SDHCI_CAP_SLOT_TYPE_EMBEDDED (1U << 30)
#define SDHCI_CAP_SLOT_TYPE_SHARED (2U << 30)
#define SDHCI_CAP_SLOT_TYPE_UHS2 (3U << 30)
/*! Host Capability 2. 0x44. */
#define SDHCI_CAP_SDR50 BIT(0)
#define SDHCI_CAP_SDR5104 BIT(1)
#define SDHCI_CAP_DDR50 BIT(2)
#define SDHCI_CAP_UHS2 BIT(3)
#define SDHCI_CAP_DRV_TYPE_A BIT(4)
#define SDHCI_CAP_DRV_TYPE_C BIT(5)
#define SDHCI_CAP_DRV_TYPE_D BIT(6)
#define SDHCI_CAP_RSP_TIMER_CNT_MASK (0xFU << 8)
#define SDHCI_CAP_SDR50_TUNING BIT(13)
#define SDHCI_CAP_RSP_MODES_MASK (3U << 14)
#define SDHCI_CAP_CLK_MULT (0xFFU << 16)
#define SDHCI_CAP_ADMA3 BIT(27)
#define SDHCI_CAP_VDD2_1_8V BIT(28)
/*! SDMMC max current. 0x48 */
#define SDHCI_MAX_CURRENT_3_3_V_MASK (0xFFU << 0)
#define SDHCI_MAX_CURRENT_3_0_V_MASK (0xFFU << 8)
#define SDHCI_MAX_CURRENT_1_8_V_MASK (0xFFU << 16)
#define SDHCI_MAX_CURRENT_MULTIPLIER 4
/*! SDMMC max current. 0x4C */
#define SDHCI_MAX_CURRENT_1_8_V_VDD2_MASK (0xFFU << 0)
/*! SD bus speeds. */
#define UHS_SDR12_BUS_SPEED 0
#define HIGH_SPEED_BUS_SPEED 1
#define UHS_SDR25_BUS_SPEED 1
#define UHS_SDR50_BUS_SPEED 2
#define UHS_SDR104_BUS_SPEED 3
#define UHS_DDR50_BUS_SPEED 4
#define HS400_BUS_SPEED 5
/*! SDMMC timmings. */
#define SDHCI_TIMING_MMC_ID 0
#define SDHCI_TIMING_MMC_LS26 1
#define SDHCI_TIMING_MMC_HS52 2
#define SDHCI_TIMING_MMC_HS200 3
#define SDHCI_TIMING_MMC_HS400 4
#define SDHCI_TIMING_SD_ID 5
#define SDHCI_TIMING_SD_DS12 6
#define SDHCI_TIMING_SD_HS25 7
#define SDHCI_TIMING_UHS_SDR12 8
#define SDHCI_TIMING_UHS_SDR25 9
#define SDHCI_TIMING_UHS_SDR50 10
#define SDHCI_TIMING_UHS_SDR104 11
#define SDHCI_TIMING_UHS_DDR50 12
// SDR104 with a 163.2MHz -> 81.6MHz clock.
#define SDHCI_TIMING_UHS_SDR82 13 // GC FPGA. Obsolete and Repurposed. MMC_HS50 -> SDR82.
#define SDHCI_TIMING_MMC_HS100 14 // GC ASIC.
#define SDHCI_TIMING_UHS_DDR200 15
/*! SDMMC Low power features. */
#define SDMMC_POWER_SAVE_DISABLE 0
#define SDMMC_POWER_SAVE_ENABLE 1
/*! Helper for SWITCH command argument. */
#define SDMMC_SWITCH(mode, index, value) (((mode) << 24) | ((index) << 16) | ((value) << 8))
#define HW_TAP_TUNING 0x100
#define INVALID_TAP 0x100
#define SAMPLING_WINDOW_SIZE_MIN 8
/*! SDMMC controller context. */
typedef struct _sdmmc_t
{
t210_sdmmc_t *regs;
u32 id;
u32 card_clock;
u32 clock_stopped;
int powersave_enabled;
int manual_cal;
int card_clock_enabled;
int venclkctl_set;
u32 venclkctl_tap;
u32 expected_rsp_type;
u32 dma_addr_next;
u32 rsp[4];
u32 rsp3;
int t210b01;
} sdmmc_t;
/*! SDMMC command. */
typedef struct _sdmmc_cmd_t
{
u16 cmd;
u32 arg;
u32 rsp_type;
u32 check_busy;
} sdmmc_cmd_t;
/*! SDMMC request. */
typedef struct _sdmmc_req_t
{
void *buf;
u32 blksize;
u32 num_sectors;
int is_write;
int is_multi_block;
int is_auto_stop_trn;
} sdmmc_req_t;
int sdmmc_get_io_power(sdmmc_t *sdmmc);
u32 sdmmc_get_bus_width(sdmmc_t *sdmmc);
void sdmmc_set_bus_width(sdmmc_t *sdmmc, u32 bus_width);
void sdmmc_save_tap_value(sdmmc_t *sdmmc);
void sdmmc_setup_drv_type(sdmmc_t *sdmmc, u32 type);
int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type);
void sdmmc_card_clock_powersave(sdmmc_t *sdmmc, int powersave_enable);
int sdmmc_get_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 size, u32 type);
int sdmmc_tuning_execute(sdmmc_t *sdmmc, u32 type, u32 cmd);
int sdmmc_stop_transmission(sdmmc_t *sdmmc, u32 *rsp);
bool sdmmc_get_sd_inserted();
int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type);
void sdmmc_end(sdmmc_t *sdmmc);
void sdmmc_init_cmd(sdmmc_cmd_t *cmdbuf, u16 cmd, u32 arg, u32 rsp_type, u32 check_busy);
int sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *blkcnt_out);
int sdmmc_enable_low_voltage(sdmmc_t *sdmmc);
#endif

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/*
* Copyright (c) 2018 naehrwert
* Copyright (c) 2018-2023 CTCaer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _SDMMC_T210_H_
#define _SDMMC_T210_H_
#include <assert.h>
#include <utils/types.h>
#define SDHCI_TEGRA_TUNING_TAP_HW_UPDATED BIT(17)
#define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31)
#define SDHCI_TEGRA_DLLCAL_ACTIVE BIT(31)
#define SDHCI_TEGRA_PADCTRL_E_INPUT_PWRD BIT(31)
#define SDHCI_TEGRA_PADCTRL_VREF_SEL_MASK 0xF
#define SDHCI_TEGRA_AUTOCAL_SLW_OVERRIDE BIT(28)
#define SDHCI_TEGRA_AUTOCAL_ENABLE BIT(29)
#define SDHCI_TEGRA_AUTOCAL_START BIT(31)
#define SDHCI_TEGRA_AUTOCAL_ACTIVE BIT(31)
typedef struct _t210_sdmmc_t
{
/* 0x00 */ vu32 sysad; // sdma system address.
/* 0x04 */ vu16 blksize;
/* 0x06 */ vu16 blkcnt;
/* 0x08 */ vu32 argument;
/* 0x0C */ vu16 trnmod;
/* 0x0E */ vu16 cmdreg;
/* 0x10 */ vu32 rspreg0;
/* 0x14 */ vu32 rspreg1;
/* 0x18 */ vu32 rspreg2;
/* 0x1C */ vu32 rspreg3;
/* 0x20 */ vu32 bdata; // Buffer data port.
/* 0x24 */ vu32 prnsts;
/* 0x28 */ vu8 hostctl;
/* 0x29 */ vu8 pwrcon;
/* 0x2A */ vu8 blkgap;
/* 0x2B */ vu8 wakcon;
/* 0x2C */ vu16 clkcon;
/* 0x2E */ vu8 timeoutcon;
/* 0x2F */ vu8 swrst;
/* 0x30 */ vu16 norintsts; // Normal interrupt status.
/* 0x32 */ vu16 errintsts; // Error interrupt status.
/* 0x34 */ vu16 norintstsen; // Enable irq status.
/* 0x36 */ vu16 errintstsen; // Enable irq status.
/* 0x38 */ vu16 norintsigen; // Enable irq signal to LIC/GIC.
/* 0x3A */ vu16 errintsigen; // Enable irq signal to LIC/GIC.
/* 0x3C */ vu16 acmd12errsts;
/* 0x3E */ vu16 hostctl2;
// CAP0: 0x376CD08C.
// 12 MHz timeout clock. 208 MHz max base clock. 512B max block length. 8-bit support.
// ADMA2 support. HS25 support. SDMA support. No suspend/resume support. 3.3/3.0/1.8V support.
// 64bit addressing for V3/V4 support. Async IRQ support. All report as removable.
/* 0x40 */ vu32 capareg;
// CAP1: 0x10002F73.
// SDR50/SDR104 support. No DDR50 support. Drive A/B/C/D support.
// Timer re-tuning info from other source. SDR50 requires re-tuning.
// Tuning uses timer and transfers should be 4MB limited.
// ADMA3 not supported. 1.8V VDD2 supported.
/* 0x44 */ vu32 capareg_hi;
/* 0x48 */ vu32 maxcurr; // Get information by another method. Can be overriden via maxcurrover and maxcurrover_hi.
/* 0x4C */ vu32 maxcurr_hi;
/* 0x50 */ vu16 setacmd12err; // Force error in acmd12errsts.
/* 0x52 */ vu16 setinterr;
/* 0x54 */ vu8 admaerr;
/* 0x55 */ vu8 rsvd1[3]; // 55-57 reserved.
/* 0x58 */ vu32 admaaddr;
/* 0x5C */ vu32 admaaddr_hi;
/* 0x60 */ vu16 presets[11];
/* 0x76 */ vu16 rsvd2;
/* 0x78 */ vu32 adma3addr;
/* 0x7C */ vu32 adma3addr_hi;
/* 0x80 */ vu8 uhs2[124]; // 80-FB UHS-II.
/* 0xFC */ vu16 slotintsts;
/* 0xFE */ vu16 hcver; // 0x303 (4.00).
/* UHS-II range. Used for Vendor registers here */
/* 0x100 */ vu32 venclkctl;
/* 0x104 */ vu32 vensysswctl;
/* 0x108 */ vu32 venerrintsts;
/* 0x10C */ vu32 vencapover;
/* 0x110 */ vu32 venbootctl;
/* 0x114 */ vu32 venbootacktout;
/* 0x118 */ vu32 venbootdattout;
/* 0x11C */ vu32 vendebouncecnt;
/* 0x120 */ vu32 venmiscctl;
/* 0x124 */ vu32 maxcurrover;
/* 0x128 */ vu32 maxcurrover_hi;
/* 0x12C */ vu32 unk0[32]; // 0x12C
/* 0x1AC */ vu32 veniotrimctl;
/* 0x1B0 */ vu32 vendllcalcfg;
/* 0x1B4 */ vu32 vendllctl0;
/* 0x1B8 */ vu32 vendllctl1;
/* 0x1BC */ vu32 vendllcalcfgsts;
/* 0x1C0 */ vu32 ventunctl0;
/* 0x1C4 */ vu32 ventunctl1;
/* 0x1C8 */ vu32 ventunsts0;
/* 0x1CC */ vu32 ventunsts1;
/* 0x1D0 */ vu32 venclkgatehystcnt;
/* 0x1D4 */ vu32 venpresetval0;
/* 0x1D8 */ vu32 venpresetval1;
/* 0x1DC */ vu32 venpresetval2;
/* 0x1E0 */ vu32 sdmemcmppadctl;
/* 0x1E4 */ vu32 autocalcfg;
/* 0x1E8 */ vu32 autocalintval;
/* 0x1EC */ vu32 autocalsts;
/* 0x1F0 */ vu32 iospare;
/* 0x1F4 */ vu32 mcciffifoctl;
/* 0x1F8 */ vu32 timeoutwcoal;
} t210_sdmmc_t;
static_assert(sizeof(t210_sdmmc_t) == 0x1FC, "T210 SDMMC REG size is wrong!");
#endif