git subrepo pull --force emummc
subrepo: subdir: "emummc" merged: "2fc47cbb8" upstream: origin: "https://github.com/lulle2007200/emuMMC.git" branch: "develop" commit: "2fc47cbb8" git-subrepo: version: "0.4.9" origin: "https://github.com/ingydotnet/git-subrepo.git" commit: "30db3b8"
This commit is contained in:
lulle2007200
214
emummc/source/fatal/bdk/rtc/max77620-rtc.c
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214
emummc/source/fatal/bdk/rtc/max77620-rtc.c
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/*
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* PMIC Real Time Clock driver for Nintendo Switch's MAX77620-RTC
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*
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* Copyright (c) 2018-2022 CTCaer
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* Copyright (c) 2019 shchmue
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <rtc/max77620-rtc.h>
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#include <soc/i2c.h>
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#include <soc/pmc.h>
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#include <soc/timer.h>
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#include <soc/t210.h>
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int epoch_offset = 0;
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void max77620_rtc_prep_read()
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{
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i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_UPDATE0_REG, MAX77620_RTC_READ_UPDATE);
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}
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void max77620_rtc_get_time(rtc_time_t *time)
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{
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u8 val = 0;
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// Update RTC regs from RTC clock.
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i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_UPDATE0_REG, MAX77620_RTC_READ_UPDATE);
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// Get control reg config.
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val = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_CONTROL_REG);
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// TODO: Check for binary format also?
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// Get time.
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time->sec = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_SEC_REG) & 0x7F;
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time->min = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_MIN_REG) & 0x7F;
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u8 hour = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_HOUR_REG);
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time->hour = hour & 0x1F;
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if (!(val & MAX77620_RTC_24H) && (hour & MAX77620_RTC_HOUR_PM_MASK))
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time->hour = (time->hour & 0xF) + 12;
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// Get day of week. 1: Monday to 7: Sunday.
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time->weekday = 0;
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val = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_WEEKDAY_REG);
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for (int i = 0; i < 8; i++)
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{
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time->weekday++;
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if (val & 1)
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break;
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val >>= 1;
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}
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// Get date.
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time->day = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_DATE_REG) & 0x1f;
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time->month = (i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_MONTH_REG) & 0xF) - 1;
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time->year = (i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_YEAR_REG) & 0x7F) + 2000;
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}
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void max77620_rtc_stop_alarm()
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{
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u8 val = 0;
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// Update RTC regs from RTC clock.
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i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_UPDATE0_REG, MAX77620_RTC_READ_UPDATE);
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msleep(16);
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// Stop alarm for both ALARM1 and ALARM2. Horizon uses ALARM2.
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for (int i = 0; i < (MAX77620_RTC_NR_TIME_REGS * 2); i++)
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{
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val = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM1_SEC_REG + i);
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val &= ~MAX77620_RTC_ALARM_EN_MASK;
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i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM1_SEC_REG + i, val);
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}
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// Update RTC clock from RTC regs.
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i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_UPDATE0_REG, MAX77620_RTC_WRITE_UPDATE);
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}
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void max77620_rtc_epoch_to_date(u32 epoch, rtc_time_t *time)
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{
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u32 tmp, edays, year, month, day;
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// Set time.
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time->sec = epoch % 60;
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epoch /= 60;
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time->min = epoch % 60;
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epoch /= 60;
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time->hour = epoch % 24;
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epoch /= 24;
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// Calculate base date values.
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tmp = (u32)(((u64)4 * epoch + 102032) / 146097 + 15);
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tmp = (u32)((u64)epoch + 2442113 + tmp - (tmp >> 2));
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year = (20 * tmp - 2442) / 7305;
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edays = tmp - 365 * year - (year >> 2);
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month = edays * 1000 / 30601;
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day = edays - month * 30 - month * 601 / 1000;
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// Month/Year offset.
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if (month < 14)
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{
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year -= 4716;
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month--;
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}
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else
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{
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year -= 4715;
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month -= 13;
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}
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// Set date.
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time->year = year;
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time->month = month;
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time->day = day;
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// Set weekday.
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time->weekday = 0; //! TODO.
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}
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u32 max77620_rtc_date_to_epoch(const rtc_time_t *time)
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{
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u32 year, month, epoch;
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//Year
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year = time->year;
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//Month of year
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month = time->month;
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// Month/Year offset.
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if (month < 3)
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{
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month += 12;
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year--;
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}
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epoch = (365 * year) + (year >> 2) - (year / 100) + (year / 400); // Years to days.
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epoch += (30 * month) + (3 * (month + 1) / 5) + time->day; // Months to days.
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epoch -= 719561; // Epoch time is 1/1/1970.
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epoch *= 86400; // Days to seconds.
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epoch += (3600 * time->hour) + (60 * time->min) + time->sec; // Add hours, minutes and seconds.
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return epoch;
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}
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void max77620_rtc_get_time_adjusted(rtc_time_t *time)
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{
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max77620_rtc_get_time(time);
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if (epoch_offset)
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{
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u32 epoch = (u32)((s64)max77620_rtc_date_to_epoch(time) + epoch_offset);
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max77620_rtc_epoch_to_date(epoch, time);
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}
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}
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void max77620_rtc_set_epoch_offset(int offset)
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{
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epoch_offset = offset;
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}
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void max77620_rtc_set_reboot_reason(rtc_reboot_reason_t *rr)
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{
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max77620_rtc_stop_alarm();
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// Set reboot reason.
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i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM1_YEAR_REG, rr->enc.val1);
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i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM2_YEAR_REG, rr->enc.val2);
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// Set reboot reason magic.
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i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM1_WEEKDAY_REG, RTC_REBOOT_REASON_MAGIC);
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i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM2_WEEKDAY_REG, RTC_REBOOT_REASON_MAGIC);
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// Update RTC clock from RTC regs.
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i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_UPDATE0_REG, MAX77620_RTC_WRITE_UPDATE);
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msleep(16);
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}
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bool max77620_rtc_get_reboot_reason(rtc_reboot_reason_t *rr)
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{
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u8 magic[2];
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// Get reboot reason magic.
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magic[0] = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM1_WEEKDAY_REG);
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magic[1] = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM2_WEEKDAY_REG);
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// Magic must be correct and match on both registers.
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if (magic[0] != RTC_REBOOT_REASON_MAGIC || magic[0] != magic[1])
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return false;
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// Reboot reason setter is expected to have updated the actual regs already.
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rr->enc.val1 = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM1_YEAR_REG);
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rr->enc.val2 = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM2_YEAR_REG);
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// Clear magic and update actual regs.
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i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM1_WEEKDAY_REG, 0);
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i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM2_WEEKDAY_REG, 0);
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i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_UPDATE0_REG, MAX77620_RTC_WRITE_UPDATE);
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// Return reboot reason. False if [config] was selected.
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return true;
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}
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120
emummc/source/fatal/bdk/rtc/max77620-rtc.h
vendored
Normal file
120
emummc/source/fatal/bdk/rtc/max77620-rtc.h
vendored
Normal file
@@ -0,0 +1,120 @@
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/*
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* PMIC Real Time Clock driver for Nintendo Switch's MAX77620-RTC
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*
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* Copyright (c) 2018-2022 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _MFD_MAX77620_RTC_H_
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#define _MFD_MAX77620_RTC_H_
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#include <utils/types.h>
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#define MAX77620_RTC_I2C_ADDR 0x68
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#define MAX77620_RTC_NR_TIME_REGS 7
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#define MAX77620_RTC_RTCINT_REG 0x00
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#define MAX77620_RTC_RTCINTM_REG 0x01
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#define MAX77620_RTC_CONTROLM_REG 0x02
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#define MAX77620_RTC_CONTROL_REG 0x03
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#define MAX77620_RTC_BIN_FORMAT BIT(0)
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#define MAX77620_RTC_24H BIT(1)
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#define MAX77620_RTC_UPDATE0_REG 0x04
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#define MAX77620_RTC_WRITE_UPDATE BIT(0)
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#define MAX77620_RTC_READ_UPDATE BIT(4)
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#define MAX77620_RTC_UPDATE1_REG 0x05
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#define MAX77620_RTC_RTCSMPL_REG 0x06
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#define MAX77620_RTC_SEC_REG 0x07
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#define MAX77620_RTC_MIN_REG 0x08
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#define MAX77620_RTC_HOUR_REG 0x09
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#define MAX77620_RTC_HOUR_PM_MASK BIT(6)
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#define MAX77620_RTC_WEEKDAY_REG 0x0A
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#define MAX77620_RTC_MONTH_REG 0x0B
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#define MAX77620_RTC_YEAR_REG 0x0C
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#define MAX77620_RTC_DATE_REG 0x0D
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#define MAX77620_ALARM1_SEC_REG 0x0E
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#define MAX77620_ALARM1_MIN_REG 0x0F
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#define MAX77620_ALARM1_HOUR_REG 0x10
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#define MAX77620_ALARM1_WEEKDAY_REG 0x11
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#define MAX77620_ALARM1_MONTH_REG 0x12
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#define MAX77620_ALARM1_YEAR_REG 0x13
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#define MAX77620_ALARM1_DATE_REG 0x14
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#define MAX77620_ALARM2_SEC_REG 0x15
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#define MAX77620_ALARM2_MIN_REG 0x16
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#define MAX77620_ALARM2_HOUR_REG 0x17
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#define MAX77620_ALARM2_WEEKDAY_REG 0x18
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#define MAX77620_ALARM2_MONTH_REG 0x19
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#define MAX77620_ALARM2_YEAR_REG 0x1A
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#define MAX77620_ALARM2_DATE_REG 0x1B
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#define MAX77620_RTC_ALARM_EN_MASK BIT(7)
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typedef struct _rtc_time_t {
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u8 weekday;
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u8 sec;
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u8 min;
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u8 hour;
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u8 day;
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u8 month;
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u16 year;
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} rtc_time_t;
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#define RTC_REBOOT_REASON_MAGIC 0x77 // 7-bit reg.
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enum {
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REBOOT_REASON_NOP = 0, // Use [config].
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REBOOT_REASON_SELF = 1, // Use autoboot_idx/autoboot_list.
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REBOOT_REASON_MENU = 2, // Force menu.
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REBOOT_REASON_UMS = 3, // Force selected UMS partition.
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REBOOT_REASON_REC = 4, // Set PMC_SCRATCH0_MODE_RECOVERY and reboot to self.
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REBOOT_REASON_PANIC = 5 // Inform bootloader that panic occured if T210B01.
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};
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typedef struct _rtc_rr_decoded_t
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{
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u16 reason:4;
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u16 autoboot_idx:4;
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u16 autoboot_list:1;
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u16 ums_idx:3;
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} rtc_rr_decoded_t;
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typedef struct _rtc_rr_encoded_t
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{
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u16 val1:6; // 6-bit reg.
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u16 val2:6; // 6-bit reg.
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} rtc_rr_encoded_t;
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typedef struct _rtc_reboot_reason_t
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{
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union {
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rtc_rr_decoded_t dec;
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rtc_rr_encoded_t enc;
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};
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} rtc_reboot_reason_t;
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void max77620_rtc_prep_read();
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void max77620_rtc_get_time(rtc_time_t *time);
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void max77620_rtc_get_time_adjusted(rtc_time_t *time);
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void max77620_rtc_set_epoch_offset(int offset);
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void max77620_rtc_stop_alarm();
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void max77620_rtc_epoch_to_date(u32 epoch, rtc_time_t *time);
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u32 max77620_rtc_date_to_epoch(const rtc_time_t *time);
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void max77620_rtc_set_reboot_reason(rtc_reboot_reason_t *rr);
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bool max77620_rtc_get_reboot_reason(rtc_reboot_reason_t *rr);
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#endif /* _MFD_MAX77620_RTC_H_ */
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Reference in New Issue
Block a user