@@ -99,17 +99,26 @@ void pmc_scratch_lock(pmc_sec_lock_t lock_mask)
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}
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}
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int pmc_enable_partition(pmc_power_rail_t part, u32 enable)
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/*
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* !TODO: Non CCPLEX power domains power gating/ungating.
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* Power gating: clock should be in reset if enabled and then
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* pmc_domain_pwrgate_set is run.
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* Power ungating: run pmc_domain_pwrgate_set, enable clocks and keep in
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* reset, remove clamping, remove reset, run mbist war if T210 and then clocks
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* can be disabled.
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*/
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int pmc_domain_pwrgate_set(pmc_power_rail_t part, u32 enable)
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{
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u32 part_mask = BIT(part);
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u32 desired_state = enable << part;
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// Check if the partition has the state we want.
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// Check if the power domain has the state we want.
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if ((PMC(APBDEV_PMC_PWRGATE_STATUS) & part_mask) == desired_state)
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return 1;
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u32 i = 5001;
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while (PMC(APBDEV_PMC_PWRGATE_TOGGLE) & 0x100)
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while (PMC(APBDEV_PMC_PWRGATE_TOGGLE) & PMC_PWRGATE_TOGGLE_START)
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{
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usleep(1);
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i--;
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@@ -118,7 +127,7 @@ int pmc_enable_partition(pmc_power_rail_t part, u32 enable)
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}
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// Toggle power gating.
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PMC(APBDEV_PMC_PWRGATE_TOGGLE) = part | 0x100;
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PMC(APBDEV_PMC_PWRGATE_TOGGLE) = part | PMC_PWRGATE_TOGGLE_START;
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i = 5001;
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while (i > 0)
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