Damien Zhao
@@ -2,7 +2,7 @@
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018 shuffle2
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* Copyright (c) 2018 balika011
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* Copyright (c) 2019-2023 CTCaer
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* Copyright (c) 2019-2025 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -32,8 +32,12 @@
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#define FUSE_TIME_PGM1 0x18
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#define FUSE_TIME_PGM2 0x1C
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#define FUSE_PRIV2INTFC 0x20
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#define FUSE_PRIV2INTFC_START_DATA BIT(0)
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#define FUSE_PRIV2INTFC_SKIP_RECORDS BIT(1)
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#define FUSE_FUSEBYPASS 0x24
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#define FUSE_PRIVATEKEYDISABLE 0x28
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#define FUSE_PRIVKEY_DISABLE BIT(0)
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#define FUSE_PRIVKEY_TZ_STICKY_BIT BIT(4)
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#define FUSE_DISABLEREGPROGRAM 0x2C
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#define FUSE_WRITE_ACCESS_SW 0x30
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#define FUSE_PWR_GOOD_SW 0x34
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@@ -113,14 +117,14 @@
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#define FUSE_PUBLIC_KEY5 0x178
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#define FUSE_PUBLIC_KEY6 0x17C
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#define FUSE_PUBLIC_KEY7 0x180
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#define FUSE_TSENSOR1_CALIB 0x184
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#define FUSE_TSENSOR2_CALIB 0x188
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#define FUSE_TSENSOR1_CALIB 0x184 // CPU1.
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#define FUSE_TSENSOR2_CALIB 0x188 // CPU2.
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#define FUSE_OPT_SECURE_SCC_DIS_B01 0x18C
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#define FUSE_OPT_CP_REV 0x190
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#define FUSE_OPT_CP_REV 0x190 // FUSE style revision - ATE. 0x101 0x100
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#define FUSE_OPT_PFG 0x194
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#define FUSE_TSENSOR0_CALIB 0x198
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#define FUSE_TSENSOR0_CALIB 0x198 // CPU0.
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#define FUSE_FIRST_BOOTROM_PATCH_SIZE 0x19C
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#define FUSE_SECURITY_MODE 0x1A0
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#define FUSE_PRIVATE_KEY0 0x1A4
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@@ -164,22 +168,22 @@
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#define FUSE_SPARE_REGISTER_ODM_B01 0x224
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#define FUSE_GPU_IDDQ_CALIB 0x228
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#define FUSE_TSENSOR3_CALIB 0x22C
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#define FUSE_TSENSOR3_CALIB 0x22C // CPU3.
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#define FUSE_CLOCK_BONDOUT0 0x230
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#define FUSE_CLOCK_BONDOUT1 0x234
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#define FUSE_RESERVED_ODM26_B01 0x238
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#define FUSE_RESERVED_ODM27_B01 0x23C
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#define FUSE_RESERVED_ODM28_B01 0x240
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#define FUSE_RESERVED_ODM28_B01 0x240 // MAX77812 phase configuration.
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#define FUSE_OPT_SAMPLE_TYPE 0x244
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#define FUSE_OPT_SUBREVISION 0x248
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#define FUSE_OPT_SUBREVISION 0x248 // "", "p", "q", "r". e.g: A01p.
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#define FUSE_OPT_SW_RESERVED_0 0x24C
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#define FUSE_OPT_SW_RESERVED_1 0x250
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#define FUSE_TSENSOR4_CALIB 0x254
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#define FUSE_TSENSOR5_CALIB 0x258
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#define FUSE_TSENSOR6_CALIB 0x25C
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#define FUSE_TSENSOR7_CALIB 0x260
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#define FUSE_TSENSOR4_CALIB 0x254 // GPU.
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#define FUSE_TSENSOR5_CALIB 0x258 // MEM0.
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#define FUSE_TSENSOR6_CALIB 0x25C // MEM1.
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#define FUSE_TSENSOR7_CALIB 0x260 // PLLX.
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#define FUSE_OPT_PRIV_SEC_DIS 0x264
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#define FUSE_PKC_DISABLE 0x268
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@@ -199,7 +203,7 @@
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#define FUSE_RESERVED_ODM29_B01 0x294
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#define FUSE_APB2JTAG_DISABLE 0x298
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#define FUSE_ODM_INFO 0x29C
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#define FUSE_ODM_INFO 0x29C // Debug features disable.
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#define FUSE_ARM_CRYPT_DE_FEATURE 0x2A8
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#define FUSE_OPT_RAM_WTSEL_TSMCPDP_PO4SVT_B01 0x2B0
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@@ -210,9 +214,12 @@
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#define FUSE_WOA_SKU_FLAG 0x2C0
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#define FUSE_ECO_RESERVE_1 0x2C4
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#define FUSE_GCPLEX_CONFIG_FUSE 0x2C8
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#define FUSE_GPU_VPR_AUTO_FETCH_DIS BIT(0)
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#define FUSE_GPU_VPR_ENABLED BIT(1)
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#define FUSE_GPU_WPR_ENABLED BIT(2)
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#define FUSE_PRODUCTION_MONTH 0x2CC
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#define FUSE_RAM_REPAIR_INDICATOR 0x2D0
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#define FUSE_TSENSOR9_CALIB 0x2D4
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#define FUSE_TSENSOR9_CALIB 0x2D4 // AOTAG.
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#define FUSE_VMIN_CALIBRATION 0x2DC
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#define FUSE_AGING_SENSOR_CALIBRATION 0x2E0
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#define FUSE_DEBUG_AUTHENTICATION 0x2E4
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@@ -220,8 +227,8 @@
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#define FUSE_SECURE_PROVISION_INFO 0x2EC
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#define FUSE_OPT_GPU_DISABLE_CP1 0x2F0
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#define FUSE_SPARE_ENDIS 0x2F4
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#define FUSE_ECO_RESERVE_0 0x2F8
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#define FUSE_RESERVED_CALIB0 0x304
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#define FUSE_ECO_RESERVE_0 0x2F8 // AID.
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#define FUSE_RESERVED_CALIB0 0x304 // GPCPLL ADC Calibration.
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#define FUSE_RESERVED_CALIB1 0x308
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#define FUSE_OPT_GPU_TPC0_DISABLE 0x30C
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#define FUSE_OPT_GPU_TPC0_DISABLE_CP1 0x310
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@@ -239,7 +246,7 @@
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#define FUSE_OPT_RAM_RCT_TSMCDP_PO4HVT_B01 0x328
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#define FUSE_OPT_RAM_WCT_TSMCDP_PO4HVT_B01 0x32c
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#define FUSE_OPT_RAM_KP_TSMCDP_PO4HVT_B01 0x330
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#define FUSE_OPT_ROM_SVOP_SP_B01 0x334
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#define FUSE_OPT_RAM_SVOP_SP_B01 0x334
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#define FUSE_OPT_GPU_TPC0_DISABLE_CP2 0x338
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#define FUSE_OPT_GPU_TPC1_DISABLE 0x33C
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@@ -248,7 +255,7 @@
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#define FUSE_OPT_CPU_DISABLE_CP2 0x348
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#define FUSE_OPT_GPU_DISABLE_CP2 0x34C
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#define FUSE_USB_CALIB_EXT 0x350
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#define FUSE_RESERVED_FIELD 0x354
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#define FUSE_RESERVED_FIELD 0x354 // RMA.
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#define FUSE_SPARE_REALIGNMENT_REG 0x37C
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#define FUSE_SPARE_BIT_0 0x380
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//...
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@@ -262,24 +269,24 @@
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#define FUSE_CMD_MASK 0x3
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/*! Fuse status. */
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#define FUSE_STATUS_RESET 0
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#define FUSE_STATUS_POST_RESET 1
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#define FUSE_STATUS_LOAD_ROW0 2
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#define FUSE_STATUS_LOAD_ROW1 3
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#define FUSE_STATUS_IDLE 4
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#define FUSE_STATUS_READ_SETUP 5
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#define FUSE_STATUS_READ_STROBE 6
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#define FUSE_STATUS_SAMPLE_FUSES 7
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#define FUSE_STATUS_READ_HOLD 8
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#define FUSE_STATUS_FUSE_SRC_SETUP 9
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#define FUSE_STATUS_WRITE_SETUP 10
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#define FUSE_STATUS_WRITE_ADDR_SETUP 11
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#define FUSE_STATUS_WRITE_PROGRAM 12
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#define FUSE_STATUS_WRITE_ADDR_HOLD 13
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#define FUSE_STATUS_FUSE_SRC_HOLD 14
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#define FUSE_STATUS_LOAD_RIR 15
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#define FUSE_STATUS_READ_BEFORE_WRITE_SETUP 16
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#define FUSE_STATUS_READ_DEASSERT_PD 17
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#define FUSE_STATUS_RESET 0
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#define FUSE_STATUS_POST_RESET 1
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#define FUSE_STATUS_LOAD_ROW0 2
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#define FUSE_STATUS_LOAD_ROW1 3
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#define FUSE_STATUS_IDLE 4
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#define FUSE_STATUS_READ_SETUP 5
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#define FUSE_STATUS_READ_STROBE 6
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#define FUSE_STATUS_SAMPLE_FUSES 7
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#define FUSE_STATUS_READ_HOLD 8
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#define FUSE_STATUS_FUSE_SRC_SETUP 9
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#define FUSE_STATUS_WRITE_SETUP 10
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#define FUSE_STATUS_WRITE_ADDR_SETUP 11
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#define FUSE_STATUS_WRITE_PROGRAM 12
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#define FUSE_STATUS_WRITE_ADDR_HOLD 13
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#define FUSE_STATUS_FUSE_SRC_HOLD 14
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#define FUSE_STATUS_LOAD_RIR 15
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#define FUSE_STATUS_READ_BEFORE_WRITE_SETUP 16
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#define FUSE_STATUS_READ_DEASSERT_PD 17
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/*! Fuse cache registers. */
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#define FUSE_RESERVED_ODMX(x) (0x1C8 + 4 * (x))
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@@ -304,12 +311,13 @@ enum
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void fuse_disable_program();
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u32 fuse_read_odm(u32 idx);
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u32 fuse_read_odm_keygen_rev();
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u32 fuse_read_bootrom_rev();
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u32 fuse_read_dramid(bool raw_id);
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u32 fuse_read_hw_state();
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u32 fuse_read_hw_type();
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int fuse_set_sbk();
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void fuse_wait_idle();
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void fuse_sense();
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u32 fuse_read(u32 addr);
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int fuse_read_ipatch(void (*ipatch)(u32 offset, u32 value));
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int fuse_read_evp_thunk(u32 *iram_evp_thunks, u32 *iram_evp_thunks_len);
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void fuse_read_array(u32 *words);
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