@@ -90,11 +90,11 @@ void ccplex_boot_cpu0(u32 entry, bool lock)
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CLOCK(CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2) &= 0xFFFFF000;
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// Enable CPU main rail.
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pmc_enable_partition(POWER_RAIL_CRAIL, ENABLE);
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pmc_domain_pwrgate_set(POWER_RAIL_CRAIL, ENABLE);
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// Enable cluster 0 non-CPU rail.
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pmc_enable_partition(POWER_RAIL_C0NC, ENABLE);
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pmc_domain_pwrgate_set(POWER_RAIL_C0NC, ENABLE);
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// Enable CPU0 rail.
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pmc_enable_partition(POWER_RAIL_CE0, ENABLE);
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pmc_domain_pwrgate_set(POWER_RAIL_CE0, ENABLE);
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// Request and wait for RAM repair. Needed for the Fast cluster.
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FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) = RAM_REPAIR_REQ;
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@@ -115,7 +115,7 @@ void ccplex_boot_cpu0(u32 entry, bool lock)
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}
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// Tighten up the security aperture.
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// MC(MC_TZ_SECURITY_CTRL) = 1;
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// MC(MC_TZ_SECURITY_CTRL) = TZ_SEC_CTRL_CPU_STRICT_TZ_APERTURE_CHECK;
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// Clear MSELECT reset.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_V_CLR) = BIT(CLK_V_MSELECT);
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@@ -150,11 +150,11 @@ void ccplex_powergate_cpu0()
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_V_SET) = BIT(CLK_V_MSELECT);
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// Disable CE0.
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pmc_enable_partition(POWER_RAIL_CE0, DISABLE);
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pmc_domain_pwrgate_set(POWER_RAIL_CE0, DISABLE);
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// Disable cluster 0 non-CPU.
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pmc_enable_partition(POWER_RAIL_C0NC, DISABLE);
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pmc_domain_pwrgate_set(POWER_RAIL_C0NC, DISABLE);
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// Disable CPU rail.
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pmc_enable_partition(POWER_RAIL_CRAIL, DISABLE);
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pmc_domain_pwrgate_set(POWER_RAIL_CRAIL, DISABLE);
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clock_disable_coresight();
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