update bdk

Signed-off-by: Damien Zhao <zdm65477730@126.com>
2023-02-25 00:33:58 +08:00
parent 06d55e6d87
commit cf553f87dd
129 changed files with 7997 additions and 5104 deletions
--- a/bdk/power/bm92t36.c
+++ b/bdk/power/bm92t36.c
@@ -1,7 +1,7 @@
 /*
 * USB-PD driver for Nintendo Switch's TI BM92T36
 *
- * Copyright (c) 2020 CTCaer
+ * Copyright (c) 2020-2023 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -73,18 +73,23 @@ void bm92t36_get_sink_info(bool *inserted, usb_pd_objects_t *usb_pd)

 	if (inserted)
 	{
+		memset(buf, 0, sizeof(buf));
 		_bm92t36_read_reg(buf, 2, STATUS1_REG);
 		*inserted = buf[0] & STATUS1_INSERT ? true : false;
 	}

 	if (usb_pd)
 	{
+		memset(buf, 0, sizeof(buf));
 		_bm92t36_read_reg(buf, 29, READ_PDOS_SRC_REG);
 		memcpy(pdos, &buf[1], 28);

 		memset(usb_pd, 0, sizeof(usb_pd_objects_t));
 		usb_pd->pdo_no = buf[0] / sizeof(pd_object_t);

+		if (usb_pd->pdo_no > 7)
+			usb_pd->pdo_no = 7;
+
 		for (u32 i = 0; i < usb_pd->pdo_no; i++)
 		{
 			usb_pd->pdos[i].amperage = pdos[i].amp * 10;
--- a/bdk/power/bq24193.h
+++ b/bdk/power/bq24193.h
@@ -28,7 +28,7 @@

 // REG 1 masks.
 #define BQ24193_PORCONFIG_BOOST_MASK       (1<<0)
-#define BQ24193_PORCONFIG_SYSMIN_MASK      (7<<1)
+#define BQ24193_PORCONFIG_SYSMIN_MASK      (7<<1) // 3000uV HOS default.
 #define BQ24193_PORCONFIG_CHGCONFIG_MASK   (3<<4)
 #define BQ24193_PORCONFIG_CHGCONFIG_CHARGER_EN (1<<4)
 #define BQ24193_PORCONFIG_I2CWATCHDOG_MASK (1<<6)
--- a/bdk/power/max17050.c
+++ b/bdk/power/max17050.c
@@ -24,7 +24,7 @@

 #include "max17050.h"
 #include <soc/i2c.h>
-#include <utils/util.h>
+#include <soc/timer.h>

 #define BASE_SNS_UOHM 5000

--- a/bdk/power/max77620.h
+++ b/bdk/power/max77620.h
@@ -95,9 +95,9 @@
 #define  MAX77620_IRQSD_PFI_SD1               BIT(6)
 #define  MAX77620_IRQSD_PFI_SD0               BIT(7)

-#define MAX77620_REG_IRQ_LVL2_L0_7  0x08 // LDO number that irq occured.
+#define MAX77620_REG_IRQ_LVL2_L0_7  0x08 // LDO number that irq occurred.
 #define MAX77620_REG_IRQ_MSK_L0_7   0x10
-#define MAX77620_REG_IRQ_LVL2_L8    0x09 // LDO number that irq occured. Only bit0: LDO8 is valid.
+#define MAX77620_REG_IRQ_LVL2_L8    0x09 // LDO number that irq occurred. Only bit0: LDO8 is valid.
 #define MAX77620_REG_IRQ_MSK_L8     0x11
 #define MAX77620_REG_IRQ_LVL2_GPIO  0x0A // Edge detection interrupt.

@@ -139,8 +139,8 @@
 #define MAX77620_REG_DVSSD0         0x1B
 #define MAX77620_REG_DVSSD1         0x1C
 #define  MAX77620_SDX_VOLT_MASK               0xFF
-#define  MAX77620_SD0_VOLT_MASK               0x3F
-#define  MAX77620_SD1_VOLT_MASK               0x7F
+#define  MAX77620_SD0_VOLT_MASK               0x7F // Max is 0x40.
+#define  MAX77620_SD1_VOLT_MASK               0x7F // Max is 0x4C.
 #define  MAX77620_LDO_VOLT_MASK               0x3F

 #define MAX77620_REG_SD0_CFG        0x1D
@@ -318,7 +318,7 @@
 #define MAX77620_REG_CID2           0x5A
 #define MAX77620_REG_CID3           0x5B
 #define MAX77620_REG_CID4           0x5C // OTP version.
-#define MAX77620_REG_CID5           0x5D
+#define MAX77620_REG_CID5           0x5D // ES version.
 #define  MAX77620_CID_DIDO_MASK               0xF
 #define  MAX77620_CID_DIDO_SHIFT              0
 #define  MAX77620_CID_DIDM_MASK               0xF0
--- a/bdk/power/max7762x.c
+++ b/bdk/power/max7762x.c
@@ -20,8 +20,8 @@
 #include <power/max77812.h>
 #include <soc/fuse.h>
 #include <soc/i2c.h>
+#include <soc/timer.h>
 #include <soc/t210.h>
-#include <utils/util.h>

 #define REGULATOR_SD  0
 #define REGULATOR_LDO 1
@@ -88,11 +88,11 @@ static const max77620_regulator_t _pmic_regulators[] = {
 	{ "ldo7",  50000, 800000, 1050000, 1050000,  REGULATOR_LDO, MAX77620_REG_LDO7_CFG, MAX77620_REG_LDO7_CFG2,  MAX77620_LDO_VOLT_MASK,  {{ MAX77620_REG_FPS_LDO7, 1, 4, 3 }} },
 	{ "ldo8",  50000, 800000, 1050000, 2800000,  REGULATOR_LDO, MAX77620_REG_LDO8_CFG, MAX77620_REG_LDO8_CFG2,  MAX77620_LDO_VOLT_MASK,  {{ MAX77620_REG_FPS_LDO8, 3, 7, 0 }} },

-	{ "max77621_CPU", 6250, 606250, 1000000, 1400000,  REGULATOR_BC0, MAX77621_VOUT_REG,    MAX77621_VOUT_DVS_REG,  MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} },
-	{ "max77621_GPU", 6250, 606250, 1200000, 1400000,  REGULATOR_BC0, MAX77621_VOUT_REG,    MAX77621_VOUT_DVS_REG,  MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} },
+	{ "max77621_CPU", 6250, 606250, 1000000, 1400000,  REGULATOR_BC0, MAX77621_REG_VOUT,    MAX77621_REG_VOUT_DVS,  MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} },
+	{ "max77621_GPU", 6250, 606250, 1200000, 1400000,  REGULATOR_BC0, MAX77621_REG_VOUT,    MAX77621_REG_VOUT_DVS,  MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} },
 	{ "max77812_CPU", 5000, 250000,  600000, 1525000,  REGULATOR_BC1, MAX77812_REG_M4_VOUT, MAX77812_REG_EN_CTRL,   MAX77812_BUCK_VOLT_MASK,    {{ MAX77812_EN_CTRL_EN_M4_MASK, MAX77812_EN_CTRL_EN_M4_SHIFT, 0, 0 }} },
+	{ "max77812_RAM", 5000, 250000,  600000,  650000,  REGULATOR_BC1, MAX77812_REG_M3_VOUT, MAX77812_REG_EN_CTRL,   MAX77812_BUCK_VOLT_MASK,    {{ MAX77812_EN_CTRL_EN_M3_MASK, MAX77812_EN_CTRL_EN_M3_SHIFT, 0, 0 }} } // Only on PHASE211 configuration.
 	//{ "max77812_GPU", 5000, 250000,  600000, 1525000,  REGULATOR_BC1, MAX77812_REG_M1_VOUT, MAX77812_REG_EN_CTRL,   MAX77812_BUCK_VOLT_MASK,    {{ MAX77812_EN_CTRL_EN_M1_MASK, MAX77812_EN_CTRL_EN_M1_SHIFT, 0, 0 }} },
-	//{ "max77812_RAM", 5000, 250000,  600000, 1525000,  REGULATOR_BC1, MAX77812_REG_M3_VOUT, MAX77812_REG_EN_CTRL,   MAX77812_BUCK_VOLT_MASK,    {{ MAX77812_EN_CTRL_EN_M3_MASK, MAX77812_EN_CTRL_EN_M3_SHIFT, 0, 0 }} } // Only on PHASE211 configuration.
 };

 static u8 _max77812_get_address()
@@ -121,7 +121,12 @@ static u8 _max7762x_get_i2c_address(u32 id)
 	case REGULATOR_BC0:
 		return (id == REGULATOR_CPU0 ? MAX77621_CPU_I2C_ADDR : MAX77621_GPU_I2C_ADDR);
 	case REGULATOR_BC1:
-		return _max77812_get_address();
+		{
+		u8 reg_addr = _max77812_get_address();
+		if (id == REGULATOR_RAM1 && reg_addr == MAX77812_PHASE31_CPU_I2C_ADDR)
+			reg_addr = 0;
+		return reg_addr;
+		}
 	default:
 		return 0;
 	}
@@ -175,20 +180,22 @@ int max77620_regulator_config_fps(u32 id)
 	return 1;
 }

-int max7762x_regulator_set_voltage(u32 id, u32 mv)
+int max7762x_regulator_set_voltage(u32 id, u32 uv)
 {
 	if (id > REGULATOR_MAX)
 		return 0;

 	const max77620_regulator_t *reg = &_pmic_regulators[id];

-	if (mv < reg->uv_min || mv > reg->uv_max)
+	if (uv < reg->uv_min || uv > reg->uv_max)
 		return 0;

 	u8 addr = _max7762x_get_i2c_address(id);
+	if (!addr)
+		return 0;

 	// Calculate voltage multiplier.
-	u32 mult = (mv + reg->uv_step - 1 - reg->uv_min) / reg->uv_step;
+	u32 mult = (uv + reg->uv_step - 1 - reg->uv_min) / reg->uv_step;
 	u8 val = i2c_recv_byte(I2C_5, addr, reg->volt_addr);
 	val = (val & ~reg->volt_mask) | (mult & reg->volt_mask);

@@ -249,6 +256,8 @@ int max7762x_regulator_enable(u32 id, bool enable)
 	}

 	u8 addr = _max7762x_get_i2c_address(id);
+	if (!addr)
+		return 0;

 	// Read and enable/disable.
 	u8 val = i2c_recv_byte(I2C_5, addr, reg_addr);
@@ -291,6 +300,8 @@ void max77621_config_default(u32 id, bool por)
 		return;

 	u8 addr = _max7762x_get_i2c_address(id);
+	if (!addr)
+		return;

 	if (por)
 	{
@@ -299,13 +310,13 @@ void max77621_config_default(u32 id, bool por)
 		max7762x_regulator_enable(id, false);

 		// Configure to default.
-		i2c_send_byte(I2C_5, addr, MAX77621_CONTROL1_REG, reg->ctrl.ctrl1_por);
-		i2c_send_byte(I2C_5, addr, MAX77621_CONTROL2_REG, reg->ctrl.ctrl2_por);
+		i2c_send_byte(I2C_5, addr, MAX77621_REG_CONTROL1, reg->ctrl.ctrl1_por);
+		i2c_send_byte(I2C_5, addr, MAX77621_REG_CONTROL2, reg->ctrl.ctrl2_por);
 	}
 	else
 	{
-		i2c_send_byte(I2C_5, addr, MAX77621_CONTROL1_REG, reg->ctrl.ctrl1_hos);
-		i2c_send_byte(I2C_5, addr, MAX77621_CONTROL2_REG, reg->ctrl.ctrl2_hos);
+		i2c_send_byte(I2C_5, addr, MAX77621_REG_CONTROL1, reg->ctrl.ctrl1_hos);
+		i2c_send_byte(I2C_5, addr, MAX77621_REG_CONTROL2, reg->ctrl.ctrl2_hos);
 	}
 }

--- a/bdk/power/max7762x.h
+++ b/bdk/power/max7762x.h
@@ -20,6 +20,14 @@

 #include <utils/types.h>

+/*
+ * SDx actual min is 625 mV. Multipliers 0/1 reserved.
+ * SD0 max is 1400 mV
+ * SD1 max is 1550 mV
+ * SD2 max is 3787.5 mV
+ * SD3 max is 3787.5 mV
+ */
+
 /*
 * Switch Power domains (max77620):
 * Name  | Usage         | uV step | uV min | uV default | uV max  | Init
@@ -58,22 +66,22 @@
 #define REGULATOR_LDO6 10
 #define REGULATOR_LDO7 11
 #define REGULATOR_LDO8 12
-#define REGULATOR_CPU0 13
-#define REGULATOR_GPU0 14
-#define REGULATOR_CPU1 15
-//#define REGULATOR_GPU1 16
-//#define REGULATOR_GPU1 17
-#define REGULATOR_MAX  15
+#define REGULATOR_CPU0 13 // T210 CPU.
+#define REGULATOR_GPU0 14 // T210 CPU.
+#define REGULATOR_CPU1 15 // T210B01 CPU.
+#define REGULATOR_RAM1 16 // T210B01 RAM for PHASE211.
+//#define REGULATOR_GPU1 17 // T210B01 CPU.
+#define REGULATOR_MAX  REGULATOR_RAM1

 #define MAX77621_CPU_I2C_ADDR 0x1B
 #define MAX77621_GPU_I2C_ADDR 0x1C

-#define MAX77621_VOUT_REG     0x00
-#define MAX77621_VOUT_DVS_REG 0x01
-#define MAX77621_CONTROL1_REG 0x02
-#define MAX77621_CONTROL2_REG 0x03
-#define MAX77621_CHIPID1_REG  0x04
-#define MAX77621_CHIPID2_REG  0x05
+#define MAX77621_REG_VOUT     0x00
+#define MAX77621_REG_VOUT_DVS 0x01
+#define MAX77621_REG_CONTROL1 0x02
+#define MAX77621_REG_CONTROL2 0x03
+#define MAX77621_REG_CHIPID1  0x04
+#define MAX77621_REG_CHIPID2  0x05

 /* MAX77621_VOUT_DVC_DVS */
 #define MAX77621_DVC_DVS_VOLT_MASK    0x7F
@@ -106,11 +114,10 @@
 #define MAX77621_INDUCTOR_PLUS_60_PER 3
 #define MAX77621_INDUCTOR_MASK        3

-#define MAX77621_CKKADV_TRIP_75mV_PER_US          0x0
-#define MAX77621_CKKADV_TRIP_150mV_PER_US         BIT(2)
-#define MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS BIT(3)
-#define MAX77621_CKKADV_TRIP_DISABLE              (BIT(2) | BIT(3))
-#define MAX77621_CKKADV_TRIP_MASK                 (BIT(2) | BIT(3))
+#define MAX77621_CKKADV_TRIP_75mV_PER_US          (0  << 2)
+#define MAX77621_CKKADV_TRIP_150mV_PER_US         (1u << 2)
+#define MAX77621_CKKADV_TRIP_DISABLE              (3u << 2)
+#define MAX77621_CKKADV_TRIP_MASK                 (3u << 2)

 #define MAX77621_FT_ENABLE       BIT(4)
 #define MAX77621_DISCH_ENABLE    BIT(5)
@@ -118,18 +125,17 @@
 #define MAX77621_T_JUNCTION_120  BIT(7)

 #define MAX77621_CPU_CTRL1_POR_DEFAULT  (MAX77621_RAMP_50mV_PER_US)
-#define MAX77621_CPU_CTRL1_HOS_DEFAULT  (MAX77621_AD_ENABLE                        | \
-										 MAX77621_NFSR_ENABLE                      | \
-										 MAX77621_SNS_ENABLE                       | \
+#define MAX77621_CPU_CTRL1_HOS_DEFAULT  (MAX77621_AD_ENABLE               | \
+										 MAX77621_NFSR_ENABLE             | \
+										 MAX77621_SNS_ENABLE              | \
 										 MAX77621_RAMP_12mV_PER_US)
-#define MAX77621_CPU_CTRL2_POR_DEFAULT  (MAX77621_T_JUNCTION_120                   | \
-										 MAX77621_FT_ENABLE                        | \
-										 MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS | \
-										 MAX77621_CKKADV_TRIP_150mV_PER_US         | \
+#define MAX77621_CPU_CTRL2_POR_DEFAULT  (MAX77621_T_JUNCTION_120          | \
+										 MAX77621_FT_ENABLE               | \
+										 MAX77621_CKKADV_TRIP_DISABLE     | \
 										 MAX77621_INDUCTOR_NOMINAL)
-#define MAX77621_CPU_CTRL2_HOS_DEFAULT  (MAX77621_T_JUNCTION_120                   | \
-										 MAX77621_WDTMR_ENABLE                     | \
-										 MAX77621_CKKADV_TRIP_75mV_PER_US          | \
+#define MAX77621_CPU_CTRL2_HOS_DEFAULT  (MAX77621_T_JUNCTION_120          | \
+										 MAX77621_WDTMR_ENABLE            | \
+										 MAX77621_CKKADV_TRIP_75mV_PER_US | \
 										 MAX77621_INDUCTOR_NOMINAL)

 #define MAX77621_CTRL_HOS_CFG 0
@@ -137,7 +143,7 @@

 int  max77620_regulator_get_status(u32 id);
 int  max77620_regulator_config_fps(u32 id);
-int  max7762x_regulator_set_voltage(u32 id, u32 mv);
+int  max7762x_regulator_set_voltage(u32 id, u32 uv);
 int  max7762x_regulator_enable(u32 id, bool enable);
 void max77620_config_gpio(u32 id, bool enable);
 void max77620_config_default();
--- a/bdk/power/max77812.h
+++ b/bdk/power/max77812.h
@@ -17,8 +17,8 @@
 #ifndef _MAX77812_H_
 #define _MAX77812_H_

-#define MAX77812_PHASE31_CPU_I2C_ADDR  0x31 // 2 Outputs: 3-phase M1 + 1-phase M4.
-#define MAX77812_PHASE211_CPU_I2C_ADDR 0x33 // 3 Outputs: 2-phase M1 + 1-phase M3 + 1-phase M4.
+#define MAX77812_PHASE31_CPU_I2C_ADDR  0x31 // High power GPU. 2 Outputs: 3-phase M1 + 1-phase M4.
+#define MAX77812_PHASE211_CPU_I2C_ADDR 0x33 // Low  power GPU. 3 Outputs: 2-phase M1 + 1-phase M3 + 1-phase M4.

 #define MAX77812_REG_RSET			0x00
 #define MAX77812_REG_INT_SRC		0x01
@@ -66,22 +66,23 @@
 #define MAX77812_REG_M2_VOUT_S		0x2C
 #define MAX77812_REG_M3_VOUT_S		0x2D
 #define MAX77812_REG_M4_VOUT_S		0x2E
-#define MAX77812_REG_M1_CFG			0x2F
-#define MAX77812_REG_M2_CFG			0x30
-#define MAX77812_REG_M3_CFG			0x31
-#define MAX77812_REG_M4_CFG			0x32
-#define MAX77812_REG_GLB_CFG1		0x33
-#define MAX77812_REG_GLB_CFG2		0x34
+#define MAX77812_REG_M1_CFG			0x2F // HOS: M1_ILIM - 7.2A/4.8A.
+#define MAX77812_REG_M2_CFG			0x30 // HOS: M2_ILIM - 7.2A/4.8A.
+#define MAX77812_REG_M3_CFG			0x31 // HOS: M3_ILIM - 7.2A/4.8A.
+#define MAX77812_REG_M4_CFG			0x32 // HOS: M4_ILIM - 7.2A/4.8A.
+#define MAX77812_REG_GLB_CFG1		0x33 // HOS: B_SD_SR/B_SS_SR - 5mV/us.
+#define MAX77812_REG_GLB_CFG2		0x34 // HOS: B_RD_SR/B_RU_SR - 5mV/us
 #define MAX77812_REG_GLB_CFG3		0x35

-/*! Protected area and settings only for MAX77812_REG_VERSION 4 */
+/*! Protected area and settings only for MAX77812_ES2_VERSION */
 #define MAX77812_REG_GLB_CFG4		0x36
-#define MAX77812_REG_GLB_CFG5		0x37
-#define MAX77812_REG_GLB_CFG6		0x38
+#define MAX77812_REG_GLB_CFG5		0x37 // HOS: 0x3E. Unmasked write.
+#define MAX77812_REG_GLB_CFG6		0x38 // HOS: 0x90. Unmasked write.
 #define MAX77812_REG_GLB_CFG7		0x39
-#define MAX77812_REG_GLB_CFG8		0x3A
-#define MAX77812_REG_PROT_ACCESS	0xFD
-#define MAX77812_REG_MAX			0xFE
+#define MAX77812_REG_GLB_CFG8		0x3A // HOS: 0x3A. Unmasked write.
+
+#define MAX77812_REG_PROT_ACCESS	0xFD // 0x00: Lock, 0x5A: Unlock.
+#define MAX77812_REG_MAX			0xFD

 #define MAX77812_REG_EN_CTRL_MASK(n)		BIT(n)
 #define MAX77812_START_SLEW_RATE_MASK		0x07
--- a/bdk/power/regulator_5v.c
+++ b/bdk/power/regulator_5v.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2021 CTCaer
+ * Copyright (c) 2019-2023 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -27,38 +27,31 @@ static bool usb_src = false;

 void regulator_5v_enable(u8 dev)
 {
+	bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210;
+
 	// The power supply selection from battery or USB is automatic.
 	if (!reg_5v_dev)
 	{
 		// Fan and Rail power from battery 5V regulator.
 		PINMUX_AUX(PINMUX_AUX_SATA_LED_ACTIVE) = 1;
-		gpio_config(GPIO_PORT_A, GPIO_PIN_5, GPIO_MODE_GPIO);
-		gpio_output_enable(GPIO_PORT_A, GPIO_PIN_5, GPIO_OUTPUT_ENABLE);
-		gpio_write(GPIO_PORT_A, GPIO_PIN_5, GPIO_HIGH);
+		gpio_direction_output(GPIO_PORT_A, GPIO_PIN_5, GPIO_HIGH);

-		// Only Icosa and Iowa have USB 5V VBUS rails. Skip on Hoag/Aula.
-		u32 hw_type = fuse_read_hw_type();
-		if (hw_type == FUSE_NX_HW_TYPE_ICOSA ||
-			hw_type == FUSE_NX_HW_TYPE_IOWA)
+		// Only Icosa has USB 5V VBUS rails.
+		if (tegra_t210)
 		{
 			// Fan and Rail power from USB 5V VBUS.
 			PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN0) = PINMUX_LPDR | 1;
-			gpio_config(GPIO_PORT_CC, GPIO_PIN_4, GPIO_MODE_GPIO);
-			gpio_output_enable(GPIO_PORT_CC, GPIO_PIN_4, GPIO_OUTPUT_ENABLE);
-			gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_LOW);
+			gpio_direction_output(GPIO_PORT_CC, GPIO_PIN_4, GPIO_LOW);
 		}

-		// Enable GPIO AO IO rail for T210.
-		if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210)
-		{
-			// Make sure GPIO power is enabled.
-			PMC(APBDEV_PMC_NO_IOPOWER) &= ~PMC_NO_IOPOWER_GPIO_IO_EN;
-			(void)PMC(APBDEV_PMC_NO_IOPOWER); // Commit write.
+		// Make sure GPIO IO power is enabled.
+		PMC(APBDEV_PMC_NO_IOPOWER) &= ~PMC_NO_IOPOWER_GPIO_IO_EN;
+		(void)PMC(APBDEV_PMC_NO_IOPOWER); // Commit write.
+
+		// Override power detect for GPIO AO IO rails.
+		PMC(APBDEV_PMC_PWR_DET_VAL) &= ~PMC_PWR_DET_GPIO_IO_EN;
+		(void)PMC(APBDEV_PMC_PWR_DET_VAL); // Commit write.

-			// Override power detect for GPIO AO IO rails.
-			PMC(APBDEV_PMC_PWR_DET_VAL) &= ~PMC_PWR_DET_GPIO_IO_EN;
-			(void)PMC(APBDEV_PMC_PWR_DET_VAL); // Commit write.
-		}
 		usb_src = false;
 	}
 	reg_5v_dev |= dev;
@@ -66,36 +59,23 @@ void regulator_5v_enable(u8 dev)

 void regulator_5v_disable(u8 dev)
 {
+	bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210;
+
 	reg_5v_dev &= ~dev;

 	if (!reg_5v_dev)
 	{
 		// Rail power from battery 5V regulator.
 		gpio_write(GPIO_PORT_A, GPIO_PIN_5, GPIO_LOW);
-		gpio_output_enable(GPIO_PORT_A, GPIO_PIN_5, GPIO_OUTPUT_DISABLE);
-		gpio_config(GPIO_PORT_A, GPIO_PIN_5, GPIO_MODE_SPIO);
-		PINMUX_AUX(PINMUX_AUX_SATA_LED_ACTIVE) = PINMUX_PARKED | PINMUX_INPUT_ENABLE;

-		// Only Icosa and Iowa have USB 5V VBUS rails. Skip on Hoag/Aula.
-		u32 hw_type = fuse_read_hw_type();
-		if (hw_type == FUSE_NX_HW_TYPE_ICOSA ||
-			hw_type == FUSE_NX_HW_TYPE_IOWA)
+		// Only Icosa has USB 5V VBUS rails.
+		if (tegra_t210)
 		{
 			// Rail power from USB 5V VBUS.
 			gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_LOW);
-			gpio_output_enable(GPIO_PORT_CC, GPIO_PIN_4, GPIO_OUTPUT_DISABLE);
-			gpio_config(GPIO_PORT_CC, GPIO_PIN_4, GPIO_MODE_SPIO);
-			PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN0) = PINMUX_IO_HV | PINMUX_LPDR | PINMUX_PARKED | PINMUX_INPUT_ENABLE;
 			usb_src = false;

 		}
-
-		// GPIO AO IO rails.
-		if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210)
-		{
-			PMC(APBDEV_PMC_PWR_DET_VAL) |= PMC_PWR_DET_GPIO_IO_EN;
-			(void)PMC(APBDEV_PMC_PWR_DET_VAL); // Commit write.
-		}
 	}
 }

@@ -106,10 +86,8 @@ bool regulator_5v_get_dev_enabled(u8 dev)

 void regulator_5v_usb_src_enable(bool enable)
 {
-	// Only for Icosa/Iowa. Skip on Hoag/Aula.
-	u32 hw_type = fuse_read_hw_type();
-	if (hw_type != FUSE_NX_HW_TYPE_ICOSA &&
-		hw_type != FUSE_NX_HW_TYPE_IOWA)
+	// Only for Icosa.
+	if (hw_get_chip_id() != GP_HIDREV_MAJOR_T210)
 		return;

 	if (enable && !usb_src)