uplift bdk

Signed-off-by: Damien Zhao <zdm65477730@126.com>
2023-04-02 13:21:57 +08:00
parent cf553f87dd
commit c9b22b2a36
24 changed files with 868 additions and 467 deletions
--- a/bdk/storage/sdmmc_driver.c
+++ b/bdk/storage/sdmmc_driver.c
@@ -34,9 +34,8 @@
 //#define ERROR_EXTRA_PRINTING
 #define DPRINTF(...)

-#ifdef BDK_SDMMC_OC_AND_EXTRA_PRINT
+#ifdef BDK_SDMMC_EXTRA_PRINT
 #define ERROR_EXTRA_PRINTING
-#define SDMMC_EMMC_OC
 #endif

 /*! SCMMC controller base addresses. */
@@ -109,13 +108,13 @@ void sdmmc_set_bus_width(sdmmc_t *sdmmc, u32 bus_width)

 void sdmmc_save_tap_value(sdmmc_t *sdmmc)
 {
-	sdmmc->venclkctl_tap = sdmmc->regs->venclkctl >> 16;
+	sdmmc->venclkctl_tap = (sdmmc->regs->venclkctl & 0xFF0000) >> 16;
 	sdmmc->venclkctl_set = 1;
 }

 static int _sdmmc_config_tap_val(sdmmc_t *sdmmc, u32 type)
 {
-	const u32 dqs_trim_val = 0x28;
+	const u32 dqs_trim_val = 40; // 24 if HS533/HS667.
 	const u8  tap_values_t210[4] = { 4, 0, 3, 0 };

 	u32 tap_val = 0;
@@ -123,7 +122,7 @@ static int _sdmmc_config_tap_val(sdmmc_t *sdmmc, u32 type)
 	if (type == SDHCI_TIMING_MMC_HS400)
 		sdmmc->regs->vencapover = (sdmmc->regs->vencapover & 0xFFFFC0FF) | (dqs_trim_val << 8);

-	sdmmc->regs->ventunctl0 &= ~TEGRA_MMC_VNDR_TUN_CTRL0_TAP_VAL_UPDATED_BY_HW;
+	sdmmc->regs->ventunctl0 &= ~SDHCI_TEGRA_TUNING_TAP_HW_UPDATED;

 	if (type == SDHCI_TIMING_MMC_HS400)
 	{
@@ -189,21 +188,21 @@ static void _sdmmc_autocal_execute(sdmmc_t *sdmmc, u32 power)
 		sdmmc->regs->clkcon &= ~SDHCI_CLOCK_CARD_EN;
 	}

-	// Enable E_INPUT power.
-	if (!(sdmmc->regs->sdmemcmppadctl & TEGRA_MMC_SDMEMCOMPPADCTRL_PAD_E_INPUT_PWRD))
+	// Enable E_INPUT (SD) or Disable E_PWRD (eMMC) power.
+	if (!(sdmmc->regs->sdmemcmppadctl & SDHCI_TEGRA_PADCTRL_E_INPUT_PWRD))
 	{
-		sdmmc->regs->sdmemcmppadctl |= TEGRA_MMC_SDMEMCOMPPADCTRL_PAD_E_INPUT_PWRD;
+		sdmmc->regs->sdmemcmppadctl |= SDHCI_TEGRA_PADCTRL_E_INPUT_PWRD;
 		_sdmmc_commit_changes(sdmmc);
 		usleep(1);
 	}

 	// Enable auto calibration and start auto configuration.
-	sdmmc->regs->autocalcfg |= TEGRA_MMC_AUTOCALCFG_AUTO_CAL_ENABLE | TEGRA_MMC_AUTOCALCFG_AUTO_CAL_START;
+	sdmmc->regs->autocalcfg |= SDHCI_TEGRA_AUTOCAL_ENABLE | SDHCI_TEGRA_AUTOCAL_START;
 	_sdmmc_commit_changes(sdmmc);
 	usleep(2);

 	u32 timeout = get_tmr_ms() + 10;
-	while (sdmmc->regs->autocalsts & TEGRA_MMC_AUTOCALSTS_AUTO_CAL_ACTIVE)
+	while (sdmmc->regs->autocalsts & SDHCI_TEGRA_AUTOCAL_ACTIVE)
 	{
 		if (get_tmr_ms() > timeout)
 		{
@@ -226,22 +225,18 @@ static void _sdmmc_autocal_execute(sdmmc_t *sdmmc, u32 power)
 	// In case auto calibration fails, we load suggested standard values.
 	if (!timeout)
 	{
+		sdmmc->regs->autocalcfg &= ~SDHCI_TEGRA_AUTOCAL_ENABLE;
 		_sdmmc_pad_config_fallback(sdmmc, power);
-		sdmmc->regs->autocalcfg &= ~TEGRA_MMC_AUTOCALCFG_AUTO_CAL_ENABLE;
 	}

-	// Disable E_INPUT to conserve power.
-	sdmmc->regs->sdmemcmppadctl &= ~TEGRA_MMC_SDMEMCOMPPADCTRL_PAD_E_INPUT_PWRD;
+	// Disable E_INPUT (SD) or enable E_PWRD (eMMC) to conserve power.
+	sdmmc->regs->sdmemcmppadctl &= ~SDHCI_TEGRA_PADCTRL_E_INPUT_PWRD;

 	if (should_enable_sd_clock)
 		sdmmc->regs->clkcon |= SDHCI_CLOCK_CARD_EN;
 }

-#ifdef SDMMC_EMMC_OC
-static int _sdmmc_dll_cal_execute(sdmmc_t *sdmmc, bool overclock)
-#else
 static int _sdmmc_dll_cal_execute(sdmmc_t *sdmmc)
-#endif
 {
 	int result = 1, should_disable_sd_clock = 0;

@@ -251,17 +246,15 @@ static int _sdmmc_dll_cal_execute(sdmmc_t *sdmmc)
 		sdmmc->regs->clkcon |= SDHCI_CLOCK_CARD_EN;
 	}

-#ifdef SDMMC_EMMC_OC
-	 // Add -4 TX_DLY_CODE_OFFSET if HS533.
-	if (sdmmc->id == SDMMC_4 && overclock)
-		sdmmc->regs->vendllcalcfg = sdmmc->regs->vendllcalcfg &= 0xFFFFC07F | (0x7C << 7);
-#endif
+	 // Add -4 TX_DLY_CODE_OFFSET if HS533/HS667.
+	 // if (sdmmc->id == SDMMC_4 && sdmmc->card_clock > 208000)
+	 //	sdmmc->regs->vendllctl0 = sdmmc->regs->vendllctl0 &= 0xFFFFC07F | (0x7C << 7);

-	sdmmc->regs->vendllcalcfg |= TEGRA_MMC_DLLCAL_CFG_EN_CALIBRATE;
+	sdmmc->regs->vendllcalcfg |= SDHCI_TEGRA_DLLCAL_CALIBRATE;
 	_sdmmc_commit_changes(sdmmc);

 	u32 timeout = get_tmr_ms() + 5;
-	while (sdmmc->regs->vendllcalcfg & TEGRA_MMC_DLLCAL_CFG_EN_CALIBRATE)
+	while (sdmmc->regs->vendllcalcfg & SDHCI_TEGRA_DLLCAL_CALIBRATE)
 	{
 		if (get_tmr_ms() > timeout)
 		{
@@ -271,7 +264,7 @@ static int _sdmmc_dll_cal_execute(sdmmc_t *sdmmc)
 	}

 	timeout = get_tmr_ms() + 10;
-	while (sdmmc->regs->vendllcalcfgsts & TEGRA_MMC_DLLCAL_CFG_STATUS_DLL_ACTIVE)
+	while (sdmmc->regs->vendllcalcfgsts & SDHCI_TEGRA_DLLCAL_ACTIVE)
 	{
 		if (get_tmr_ms() > timeout)
 		{
@@ -286,7 +279,7 @@ out:;
 	return result;
 }

-static void _sdmmc_reset(sdmmc_t *sdmmc)
+static void _sdmmc_reset_cmd_data(sdmmc_t *sdmmc)
 {
 	sdmmc->regs->swrst |= SDHCI_RESET_CMD | SDHCI_RESET_DATA;
 	_sdmmc_commit_changes(sdmmc);
@@ -304,6 +297,13 @@ static void _sdmmc_reset_all(sdmmc_t *sdmmc)
 		;
 }

+void sdmmc_setup_drv_type(sdmmc_t *sdmmc, u32 type)
+{
+	sdmmc->regs->hostctl2  = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_DRV_TYPE_MASK)) | SDHCI_CTRL_DRV_TYPE(type);
+
+	_sdmmc_commit_changes(sdmmc);
+}
+
 int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
 {
 	// Disable the SD clock if it was enabled, and reenable it later.
@@ -316,7 +316,7 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)

 	_sdmmc_config_tap_val(sdmmc, type);

-	_sdmmc_reset(sdmmc);
+	_sdmmc_reset_cmd_data(sdmmc);

 	switch (type)
 	{
@@ -330,22 +330,20 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)

 	case SDHCI_TIMING_MMC_HS52:
 	case SDHCI_TIMING_SD_HS25:
-		sdmmc->regs->hostctl  |= SDHCI_CTRL_HISPD; // SD only?
+		sdmmc->regs->hostctl  |= SDHCI_CTRL_HISPD;
 		sdmmc->regs->hostctl2 &= ~SDHCI_CTRL_VDD_180;
 		break;

 	case SDHCI_TIMING_MMC_HS200:
-	case SDHCI_TIMING_UHS_SDR50: // T210 Errata for SDR50, the host must be set to SDR104.
+	case SDHCI_TIMING_UHS_SDR50: // T210 Errata: the host must be set to SDR104 to WAR a CRC issue.
 	case SDHCI_TIMING_UHS_SDR104:
 	case SDHCI_TIMING_UHS_SDR82:
-	case SDHCI_TIMING_UHS_DDR50:
-	case SDHCI_TIMING_MMC_DDR100:
+	case SDHCI_TIMING_MMC_HS100:
 		sdmmc->regs->hostctl2  = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | UHS_SDR104_BUS_SPEED;
 		sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
 		break;

 	case SDHCI_TIMING_MMC_HS400:
-		// Non standard.
 		sdmmc->regs->hostctl2  = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | HS400_BUS_SPEED;
 		sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
 		break;
@@ -359,6 +357,14 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
 		sdmmc->regs->hostctl2  = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | UHS_SDR12_BUS_SPEED;
 		sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
 		break;
+
+	case SDHCI_TIMING_UHS_DDR50:
+#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT
+	case SDHCI_TIMING_UHS_DDR200:
+#endif
+		sdmmc->regs->hostctl2  = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | UHS_DDR50_BUS_SPEED;
+		sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180;
+		break;
 	}

 	_sdmmc_commit_changes(sdmmc);
@@ -367,31 +373,24 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type)
 	u16 divisor;
 	clock_sdmmc_get_card_clock_div(&clock, &divisor, type);
 	clock_sdmmc_config_clock_source(&clock, sdmmc->id, clock);
-	sdmmc->divisor = (clock + divisor - 1) / divisor;
+	sdmmc->card_clock = (clock + divisor - 1) / divisor;

 	//if divisor != 1 && divisor << 31 -> error

-	u16 div = divisor >> 1;
-	divisor = 0;
-	if (div > 0xFF)
-		divisor = div >> SDHCI_DIVIDER_SHIFT;
+	u16 div_lo = divisor >> 1;
+	u16 div_hi = 0;
+	if (div_lo > 0xFF)
+		div_hi = div_lo >> SDHCI_DIV_LO_SHIFT;

-	sdmmc->regs->clkcon = (sdmmc->regs->clkcon & ~(SDHCI_DIV_MASK | SDHCI_DIV_HI_MASK))
-		| (div << SDHCI_DIVIDER_SHIFT) | (divisor << SDHCI_DIVIDER_HI_SHIFT);
+	sdmmc->regs->clkcon = (sdmmc->regs->clkcon & ~(SDHCI_DIV_MASK | SDHCI_DIV_HI_MASK)) |
+						  (div_lo << SDHCI_DIV_LO_SHIFT) | (div_hi << SDHCI_DIV_HI_SHIFT);

 	// Enable the SD clock again.
 	if (should_enable_sd_clock)
 		sdmmc->regs->clkcon |= SDHCI_CLOCK_CARD_EN;

 	if (type == SDHCI_TIMING_MMC_HS400)
-	{
-#ifdef SDMMC_EMMC_OC
-		bool overclock_en = clock > 208000;
-		return _sdmmc_dll_cal_execute(sdmmc, overclock_en);
-#else
 		return _sdmmc_dll_cal_execute(sdmmc);
-#endif
-	}

 	return 1;
 }
@@ -524,7 +523,7 @@ static int _sdmmc_wait_cmd_data_inhibit(sdmmc_t *sdmmc, bool wait_dat)
 	while (sdmmc->regs->prnsts & SDHCI_CMD_INHIBIT)
 		if (get_tmr_ms() > timeout)
 		{
-			_sdmmc_reset(sdmmc);
+			_sdmmc_reset_cmd_data(sdmmc);
 			return 0;
 		}

@@ -534,7 +533,7 @@ static int _sdmmc_wait_cmd_data_inhibit(sdmmc_t *sdmmc, bool wait_dat)
 		while (sdmmc->regs->prnsts & SDHCI_DATA_INHIBIT)
 			if (get_tmr_ms() > timeout)
 			{
-				_sdmmc_reset(sdmmc);
+				_sdmmc_reset_cmd_data(sdmmc);
 				return 0;
 			}
 	}
@@ -550,7 +549,7 @@ static int _sdmmc_wait_card_busy(sdmmc_t *sdmmc)
 	while (!(sdmmc->regs->prnsts & SDHCI_DATA_0_LVL))
 		if (get_tmr_ms() > timeout)
 		{
-			_sdmmc_reset(sdmmc);
+			_sdmmc_reset_cmd_data(sdmmc);
 			return 0;
 		}

@@ -611,8 +610,9 @@ static int _sdmmc_send_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, bool is_data_presen

 	if (is_data_present)
 		cmdflags |= SDHCI_CMD_DATA;
+
 	sdmmc->regs->argument = cmd->arg;
-	sdmmc->regs->cmdreg = (cmd->cmd << 8) | cmdflags;
+	sdmmc->regs->cmdreg   = SDHCI_CMD_IDX(cmd->cmd) | cmdflags;

 	return 1;
 }
@@ -627,10 +627,8 @@ static void _sdmmc_send_tuning_cmd(sdmmc_t *sdmmc, u32 cmd)
 	_sdmmc_send_cmd(sdmmc, &cmdbuf, true);
 }

-static int _sdmmc_tuning_execute_once(sdmmc_t *sdmmc, u32 cmd)
+static int _sdmmc_tuning_execute_once(sdmmc_t *sdmmc, u32 cmd, u32 tap)
 {
-	if (sdmmc->powersave_enabled)
-		return 0;
 	if (!_sdmmc_wait_cmd_data_inhibit(sdmmc, true))
 		return 0;

@@ -640,11 +638,21 @@ static int _sdmmc_tuning_execute_once(sdmmc_t *sdmmc, u32 cmd)
 	sdmmc->regs->norintsts = sdmmc->regs->norintsts;
 	sdmmc->regs->clkcon &= ~SDHCI_CLOCK_CARD_EN;

+#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT
+	// Set tap if manual tuning.
+	if (tap != HW_TAP_TUNING)
+	{
+		sdmmc->regs->ventunctl0 &= ~SDHCI_TEGRA_TUNING_TAP_HW_UPDATED;
+		sdmmc->regs->venclkctl   = (sdmmc->regs->venclkctl & 0xFF00FFFF) | (tap << 16);
+		sdmmc->regs->ventunctl0 |=  SDHCI_TEGRA_TUNING_TAP_HW_UPDATED;
+	}
+#endif
+
 	_sdmmc_send_tuning_cmd(sdmmc, cmd);
 	_sdmmc_commit_changes(sdmmc);
 	usleep(1);

-	_sdmmc_reset(sdmmc);
+	_sdmmc_reset_cmd_data(sdmmc);

 	sdmmc->regs->clkcon |= SDHCI_CLOCK_CARD_EN;
 	_sdmmc_commit_changes(sdmmc);
@@ -657,59 +665,167 @@ static int _sdmmc_tuning_execute_once(sdmmc_t *sdmmc, u32 cmd)
 			sdmmc->regs->norintsts = SDHCI_INT_DATA_AVAIL;
 			sdmmc->regs->norintstsen &= ~SDHCI_INT_DATA_AVAIL;
 			_sdmmc_commit_changes(sdmmc);
-			usleep((1000 * 8 + sdmmc->divisor - 1) / sdmmc->divisor);
+			usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles.
 			return 1;
 		}
 	}

-	_sdmmc_reset(sdmmc);
+	_sdmmc_reset_cmd_data(sdmmc);

 	sdmmc->regs->norintstsen &= ~SDHCI_INT_DATA_AVAIL;
 	_sdmmc_commit_changes(sdmmc);
-	usleep((1000 * 8 + sdmmc->divisor - 1) / sdmmc->divisor);
+	usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles.

 	return 0;
 }

+#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT
+typedef struct _sdmmc_manual_tuning_t
+{
+	u32 result[8];
+	u32 num_iter;
+	u32 tap_start;
+	u32 tap_end;
+} sdmmc_manual_tuning_t;
+
+static int _sdmmc_manual_tuning_set_tap(sdmmc_t *sdmmc, sdmmc_manual_tuning_t *tuning)
+{
+	u32 tap_start = INVALID_TAP;
+	u32 win_size  = 0;
+	u32 best_tap  = 0;
+	u32 best_size = 0;
+
+	for (u32 i = 0; i < tuning->num_iter; i++)
+	{
+		u32 iter_end = i == (tuning->num_iter - 1) ? 1 : 0;
+		u32 stable = tuning->result[i / 32] & BIT(i % 32);
+		if (stable && !iter_end)
+		{
+			if (tap_start == INVALID_TAP)
+				tap_start = i;
+
+			win_size++;
+		}
+		else
+		{
+			if (tap_start != INVALID_TAP)
+			{
+				u32 tap_end = !iter_end ? (i - 1) : i;
+
+				// Check if window is wider.
+				if (win_size > best_size)
+				{
+					best_tap  = (tap_start + tap_end) / 2;
+					best_size = win_size + iter_end;
+
+				}
+
+				tap_start = INVALID_TAP;
+				win_size  = 0;
+			}
+		}
+	}
+
+	// Check if failed.
+	if (!best_tap)
+		return 0;
+
+	sdmmc->regs->clkcon     &= ~SDHCI_CLOCK_CARD_EN;
+	sdmmc->regs->ventunctl0 &= ~SDHCI_TEGRA_TUNING_TAP_HW_UPDATED;
+
+	// Set tap.
+	sdmmc->regs->venclkctl   = (sdmmc->regs->venclkctl & 0xFF00FFFF) | (best_tap << 16);
+
+	sdmmc->regs->ventunctl0 |=  SDHCI_TEGRA_TUNING_TAP_HW_UPDATED;
+	sdmmc->regs->clkcon     |= SDHCI_CLOCK_CARD_EN;
+
+	return 1;
+}
+
+/*
+ * SD Card DDR200 (DDR208) support
+ *
+ * On Tegra X1, that can be done with DDR50 host mode.
+ * Tuning though can't be done automatically on any DDR mode.
+ * So it needs to be done manually and selected tap will be applied from the biggest
+ * sampling window.
+ */
+static int sdmmc_tuning_execute_ddr200(sdmmc_t *sdmmc)
+{
+	sdmmc_manual_tuning_t manual_tuning = { 0 };
+	manual_tuning.num_iter = 128;
+
+	sdmmc->regs->ventunctl1  = 0; // step_size 1.
+	sdmmc->regs->ventunctl0  = (sdmmc->regs->ventunctl0 & 0xFFFF1FFF) | (2 << 13); // 128 Tries.
+	sdmmc->regs->ventunctl0  = (sdmmc->regs->ventunctl0 & 0xFFFFE03F) | (1 << 6);  // 1x Multiplier.
+	sdmmc->regs->ventunctl0 |= SDHCI_TEGRA_TUNING_TAP_HW_UPDATED;
+
+	sdmmc->regs->hostctl2   |= SDHCI_CTRL_EXEC_TUNING;
+
+	for (u32 i = 0; i < manual_tuning.num_iter; i++)
+	{
+		_sdmmc_tuning_execute_once(sdmmc, MMC_SEND_TUNING_BLOCK, i);
+
+		// Save result for manual tuning.
+		int sampled = (sdmmc->regs->hostctl2 >> SDHCI_CTRL_TUNED_CLK_SHIFT) & 1;
+		manual_tuning.result[i / 32] |= sampled << (i % 32);
+
+		if (!(sdmmc->regs->hostctl2 & SDHCI_CTRL_EXEC_TUNING))
+			break;
+	}
+
+	return _sdmmc_manual_tuning_set_tap(sdmmc, &manual_tuning);
+}
+#endif
+
 int sdmmc_tuning_execute(sdmmc_t *sdmmc, u32 type, u32 cmd)
 {
-	u32 max = 0, flag = 0;
+	u32 num_iter, flag;
+
+	if (sdmmc->powersave_enabled)
+		return 0;

 	switch (type)
 	{
 	case SDHCI_TIMING_MMC_HS200:
-	case SDHCI_TIMING_MMC_HS400:
 	case SDHCI_TIMING_UHS_SDR104:
 	case SDHCI_TIMING_UHS_SDR82:
-		max = 128;
+		num_iter = 128;
 		flag = (2 << 13); // 128 iterations.
 		break;

 	case SDHCI_TIMING_UHS_SDR50:
-	case SDHCI_TIMING_UHS_DDR50:
-	case SDHCI_TIMING_MMC_DDR100:
-		max = 256;
+	case SDHCI_TIMING_UHS_DDR50: // HW tuning is not supported on DDR modes. But it sets tap to 0 which is proper.
+	case SDHCI_TIMING_MMC_HS100:
+		num_iter = 256;
 		flag = (4 << 13); // 256 iterations.
 		break;

+	case SDHCI_TIMING_MMC_HS400:
 	case SDHCI_TIMING_UHS_SDR12:
 	case SDHCI_TIMING_UHS_SDR25:
 		return 1;

+#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT
+	case SDHCI_TIMING_UHS_DDR200:
+		return sdmmc_tuning_execute_ddr200(sdmmc);
+#endif
+
 	default:
 		return 0;
 	}

-	sdmmc->regs->ventunctl1 = 0; // step_size 1.
+	sdmmc->regs->ventunctl1  = 0; // step_size 1.
+	sdmmc->regs->ventunctl0  = (sdmmc->regs->ventunctl0 & 0xFFFF1FFF) | flag;     // Tries.
+	sdmmc->regs->ventunctl0  = (sdmmc->regs->ventunctl0 & 0xFFFFE03F) | (1 << 6); // 1x Multiplier.
+	sdmmc->regs->ventunctl0 |= SDHCI_TEGRA_TUNING_TAP_HW_UPDATED;

-	sdmmc->regs->ventunctl0 = (sdmmc->regs->ventunctl0 & 0xFFFF1FFF) | flag; // Tries.
-	sdmmc->regs->ventunctl0 = (sdmmc->regs->ventunctl0 & 0xFFFFE03F) | (1 << 6); // 1x Multiplier.
-	sdmmc->regs->ventunctl0 |= TEGRA_MMC_VNDR_TUN_CTRL0_TAP_VAL_UPDATED_BY_HW;
 	sdmmc->regs->hostctl2   |= SDHCI_CTRL_EXEC_TUNING;

-	for (u32 i = 0; i < max; i++)
+	for (u32 i = 0; i < num_iter; i++)
 	{
-		_sdmmc_tuning_execute_once(sdmmc, cmd);
+		_sdmmc_tuning_execute_once(sdmmc, cmd, HW_TAP_TUNING);
+
 		if (!(sdmmc->regs->hostctl2 & SDHCI_CTRL_EXEC_TUNING))
 			break;
 	}
@@ -737,7 +853,7 @@ static int _sdmmc_enable_internal_clock(sdmmc_t *sdmmc)
 	// Enable 32bit addressing if used (sysad. if blkcnt it fallbacks to 16bit).
 	sdmmc->regs->hostctl2 |= SDHCI_HOST_VERSION_4_EN;

-	if (!(sdmmc->regs->capareg & SDHCI_CAN_64BIT))
+	if (!(sdmmc->regs->capareg & SDHCI_CAP_64BIT))
 		return 0;

 	sdmmc->regs->hostctl2 |= SDHCI_ADDRESSING_64BIT_EN;
@@ -767,8 +883,8 @@ static int _sdmmc_autocal_config_offset(sdmmc_t *sdmmc, u32 power)
 		{
 			if (!sdmmc->t210b01)
 			{
-				off_pd = 123;
-				off_pu = 123;
+				off_pd = 0x7B; // -5.
+				off_pu = 0x7B; // -5.
 			}
 			else
 			{
@@ -780,7 +896,7 @@ static int _sdmmc_autocal_config_offset(sdmmc_t *sdmmc, u32 power)
 		{
 			if (!sdmmc->t210b01)
 			{
-				off_pd = 125;
+				off_pd = 0x7D; // -3.
 				off_pu = 0;
 			}
 		}
@@ -812,7 +928,7 @@ static u32 _sdmmc_check_mask_interrupt(sdmmc_t *sdmmc, u16 *pout, u16 mask)
 	u16 norintsts = sdmmc->regs->norintsts;
 	u16 errintsts = sdmmc->regs->errintsts;

-DPRINTF("norintsts %08X, errintsts %08X\n", norintsts, errintsts);
+	DPRINTF("norintsts %08X, errintsts %08X\n", norintsts, errintsts);

 	if (pout)
 		*pout = norintsts;
@@ -847,7 +963,7 @@ static int _sdmmc_wait_response(sdmmc_t *sdmmc)
 			break;
 		if (result != SDMMC_MASKINT_NOERROR || get_tmr_ms() > timeout)
 		{
-			_sdmmc_reset(sdmmc);
+			_sdmmc_reset_cmd_data(sdmmc);
 			return 0;
 		}
 	}
@@ -897,11 +1013,11 @@ int sdmmc_stop_transmission(sdmmc_t *sdmmc, u32 *rsp)
 		should_disable_sd_clock = true;
 		sdmmc->regs->clkcon |= SDHCI_CLOCK_CARD_EN;
 		_sdmmc_commit_changes(sdmmc);
-		usleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor);
+		usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles.
 	}

 	int result = _sdmmc_stop_transmission_inner(sdmmc, rsp);
-	usleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor);
+	usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles.

 	if (should_disable_sd_clock)
 		sdmmc->regs->clkcon &= ~SDHCI_CLOCK_CARD_EN;
@@ -934,9 +1050,9 @@ static int _sdmmc_config_dma(sdmmc_t *sdmmc, u32 *blkcnt_out, sdmmc_req_t *req)
 	if (blkcnt_out)
 		*blkcnt_out = blkcnt;

-	u32 trnmode = SDHCI_TRNS_DMA;
+	u32 trnmode = SDHCI_TRNS_DMA | SDHCI_TRNS_RTYPE_R1;

-	// Set mulitblock request.
+	// Set multiblock request.
 	if (req->is_multi_block)
 		trnmode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_BLK_CNT_EN;

@@ -988,15 +1104,17 @@ static int _sdmmc_update_dma(sdmmc_t *sdmmc)
 			if (result != SDMMC_MASKINT_NOERROR)
 			{
 #ifdef ERROR_EXTRA_PRINTING
-				EPRINTFARGS("SDMMC%d: %08X!", sdmmc->id + 1, result);
+				EPRINTFARGS("SDMMC%d: int error!", sdmmc->id + 1);
 #endif
-				_sdmmc_reset(sdmmc);
+				_sdmmc_reset_cmd_data(sdmmc);
+
 				return 0;
 			}
 		} while (get_tmr_ms() < timeout);
 	} while (sdmmc->regs->blkcnt != blkcnt);

-	_sdmmc_reset(sdmmc);
+	_sdmmc_reset_cmd_data(sdmmc);
+
 	return 0;
 }

@@ -1039,7 +1157,7 @@ static int _sdmmc_execute_cmd_inner(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_
 	if (!result)
 		EPRINTFARGS("SDMMC%d: Transfer timeout!", sdmmc->id + 1);
 #endif
-DPRINTF("rsp(%d): %08X, %08X, %08X, %08X\n", result,
+	DPRINTF("rsp(%d): %08X, %08X, %08X, %08X\n", result,
 		sdmmc->regs->rspreg0, sdmmc->regs->rspreg1, sdmmc->regs->rspreg2, sdmmc->regs->rspreg3);
 	if (result)
 	{
@@ -1171,6 +1289,7 @@ static int _sdmmc_config_sdmmc1(bool t210b01)
 	APB_MISC(APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL) = 1;

 	// Configure SDMMC1 CLK pinmux, based on state and SoC type.
+	PINMUX_AUX(PINMUX_AUX_SDMMC1_CLK) &= ~PINMUX_SCHMT;
 	if (PINMUX_AUX(PINMUX_AUX_SDMMC1_CLK) != (PINMUX_DRIVE_2X | PINMUX_INPUT_ENABLE | PINMUX_PULL_DOWN)) // Check if CLK pad is already configured.
 		PINMUX_AUX(PINMUX_AUX_SDMMC1_CLK) = PINMUX_DRIVE_2X | PINMUX_INPUT_ENABLE | (t210b01 ? PINMUX_PULL_NONE : PINMUX_PULL_DOWN);

@@ -1244,7 +1363,7 @@ static void _sdmmc_config_emmc(u32 id, bool t210b01)
 	}
 }

-int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int powersave_enable)
+int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type)
 {
 	u32 clock;
 	u16 divisor;
@@ -1301,11 +1420,10 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int p
 	sdmmc->clock_stopped = 0;

 	// Set default pad IO trimming configuration.
-	sdmmc->regs->iospare |= 0x80000; // Enable muxing.
-	sdmmc->regs->veniotrimctl &= 0xFFFFFFFB; // Set Band Gap VREG to supply DLL.
+	sdmmc->regs->iospare |= BIT(19);      // Enable 1 cycle delayed cmd_oen.
+	sdmmc->regs->veniotrimctl &= ~BIT(2); // Set Band Gap VREG to supply DLL.
 	sdmmc->regs->venclkctl = (sdmmc->regs->venclkctl & 0xE0FFFFFB) | ((u32)trim_values[sdmmc->id] << 24);
-	sdmmc->regs->sdmemcmppadctl =
-		(sdmmc->regs->sdmemcmppadctl & TEGRA_MMC_SDMEMCOMPPADCTRL_COMP_VREF_SEL_MASK) | vref_sel;
+	sdmmc->regs->sdmemcmppadctl = (sdmmc->regs->sdmemcmppadctl & ~SDHCI_TEGRA_PADCTRL_VREF_SEL_MASK) | vref_sel;

 	// Configure auto calibration values.
 	if (!_sdmmc_autocal_config_offset(sdmmc, power))
@@ -1322,7 +1440,7 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int p

 		if (sdmmc_setup_clock(sdmmc, type))
 		{
-			sdmmc_card_clock_powersave(sdmmc, powersave_enable);
+			sdmmc_card_clock_powersave(sdmmc, SDMMC_POWER_SAVE_DISABLE);
 			_sdmmc_card_clock_enable(sdmmc);
 			_sdmmc_commit_changes(sdmmc);

@@ -1408,11 +1526,11 @@ int sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *b
 		should_disable_sd_clock = 1;
 		sdmmc->regs->clkcon |= SDHCI_CLOCK_CARD_EN;
 		_sdmmc_commit_changes(sdmmc);
-		usleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor);
+		usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles.
 	}

 	int result = _sdmmc_execute_cmd_inner(sdmmc, cmd, req, blkcnt_out);
-	usleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor);
+	usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles.

 	if (should_disable_sd_clock)
 		sdmmc->regs->clkcon &= ~SDHCI_CLOCK_CARD_EN;
@@ -1425,9 +1543,6 @@ int sdmmc_enable_low_voltage(sdmmc_t *sdmmc)
 	if (sdmmc->id != SDMMC_1)
 		return 0;

-	if (!sdmmc_setup_clock(sdmmc, SDHCI_TIMING_UHS_SDR12))
-		return 0;
-
 	_sdmmc_commit_changes(sdmmc);

 	// Switch to 1.8V and wait for regulator to stabilize. Assume max possible wait needed.