@@ -29,8 +29,6 @@
|
||||
#include <storage/sd.h>
|
||||
#include <utils/util.h>
|
||||
|
||||
#define USE_RTC_TIMER
|
||||
|
||||
u8 bit_count(u32 val)
|
||||
{
|
||||
u8 cnt = 0;
|
||||
@@ -197,10 +195,32 @@ int atoi(const char *nptr)
|
||||
return (int)strtol(nptr, (char **)NULL, 10);
|
||||
}
|
||||
|
||||
void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops)
|
||||
void reg_write_array(u32 *base, const reg_cfg_t *cfg, u32 num_cfg)
|
||||
{
|
||||
for (u32 i = 0; i < num_ops; i++)
|
||||
base[ops[i].off] = ops[i].val;
|
||||
// Expected register offset is a u32 array index.
|
||||
for (u32 i = 0; i < num_cfg; i++)
|
||||
base[cfg[i].idx] = cfg[i].val;
|
||||
}
|
||||
|
||||
u16 crc16_calc(const u8 *buf, u32 len)
|
||||
{
|
||||
const u8 *p, *q;
|
||||
u16 crc = 0x55aa;
|
||||
|
||||
static u16 table[16] = {
|
||||
0x0000, 0xCC01, 0xD801, 0x1400, 0xF001, 0x3C00, 0x2800, 0xE401,
|
||||
0xA001, 0x6C00, 0x7800, 0xB401, 0x5000, 0x9C01, 0x8801, 0x4400
|
||||
};
|
||||
|
||||
q = buf + len;
|
||||
for (p = buf; p < q; p++)
|
||||
{
|
||||
u8 oct = *p;
|
||||
crc = (crc >> 4) ^ table[crc & 0xf] ^ table[(oct >> 0) & 0xf];
|
||||
crc = (crc >> 4) ^ table[crc & 0xf] ^ table[(oct >> 4) & 0xf];
|
||||
}
|
||||
|
||||
return crc;
|
||||
}
|
||||
|
||||
u32 crc32_calc(u32 crc, const u8 *buf, u32 len)
|
||||
@@ -262,7 +282,7 @@ void power_set_state(power_state_t state)
|
||||
sd_end();
|
||||
|
||||
// De-initialize and power down various hardware.
|
||||
hw_reinit_workaround(false, 0);
|
||||
hw_deinit(false, 0);
|
||||
|
||||
// Set power state.
|
||||
switch (state)
|
||||
|
||||
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Block a user