uplift bdk

Signed-off-by: Damien Zhao <zdm65477730@126.com>
2024-04-13 12:27:17 +08:00
parent cf9ec7683b
commit 029b32f722
109 changed files with 58033 additions and 2060 deletions
--- a/bdk/mem/emc.h
+++ b/bdk/mem/emc.h
@@ -698,6 +698,8 @@

 typedef enum _emc_mr_t
 {
+	MR0_FEAT    = 0,
+	MR4_TEMP    = 4,
 	MR5_MAN_ID  = 5,
 	MR6_REV_ID1 = 6,
 	MR7_REV_ID2 = 7,
@@ -710,7 +712,7 @@ enum
 	EMC_CHAN1 = 1
 };

-typedef struct _emc_mr_data_t
+typedef struct _emc_mr_chip_data_t
 {
 	// Device 0.
 	u8 rank0_ch0;
@@ -719,6 +721,12 @@ typedef struct _emc_mr_data_t
 	// Device 1.
 	u8 rank1_ch0;
 	u8 rank1_ch1;
+} emc_mr_chip_data_t;
+
+typedef struct _emc_mr_data_t
+{
+	emc_mr_chip_data_t chip0;
+	emc_mr_chip_data_t chip1;
 } emc_mr_data_t;

 #endif
--- a/bdk/mem/heap.c
+++ b/bdk/mem/heap.c
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2020 CTCaer
+ * Copyright (c) 2018-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -159,6 +159,13 @@ void *calloc(u32 num, u32 size)
 	return res;
 }

+void *zalloc(u32 size)
+{
+	void *res = (void *)_heap_alloc(size);
+	memset(res, 0, ALIGN(size, sizeof(hnode_t))); // Clear the aligned size.
+	return res;
+}
+
 void free(void *buf)
 {
 	if (buf >= _heap.start)
--- a/bdk/mem/heap.h
+++ b/bdk/mem/heap.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2020 CTCaer
+ * Copyright (c) 2018-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -48,6 +48,7 @@ void heap_init(void *base);
 void heap_set(heap_t *heap);
 void *malloc(u32 size);
 void *calloc(u32 num, u32 size);
+void *zalloc(u32 size);
 void free(void *buf);
 void heap_monitor(heap_monitor_t *mon, bool print_node_stats);

--- a/bdk/mem/mc.c
+++ b/bdk/mem/mc.c
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
- * Copyright (c) 2018-2022 CTCaer
+ * Copyright (c) 2018-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -21,7 +21,7 @@
 #include <soc/t210.h>
 #include <soc/clock.h>

-void mc_config_tsec_carveout(u32 bom, u32 size1mb, bool lock)
+void mc_config_tzdram_carveout(u32 bom, u32 size1mb, bool lock)
 {
 	MC(MC_SEC_CARVEOUT_BOM) = bom;
 	MC(MC_SEC_CARVEOUT_SIZE_MB) = size1mb;
@@ -31,96 +31,47 @@ void mc_config_tsec_carveout(u32 bom, u32 size1mb, bool lock)

 void mc_config_carveout()
 {
+	// Enable ACR GSR3.
 	*(vu32 *)0x8005FFFC = 0xC0EDBBCC;
 	MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = 1;
 	MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 0;
 	MC(MC_VIDEO_PROTECT_BOM) = 0;
-	MC(MC_VIDEO_PROTECT_SIZE_MB) = 0;
-	MC(MC_VIDEO_PROTECT_REG_CTRL) = 1;
+	MC(MC_VIDEO_PROTECT_REG_CTRL) = VPR_CTRL_LOCKED;

-	// Configure TSEC carveout @ 0x90000000, 1MB.
-	//mc_config_tsec_carveout(0x90000000, 1, false);
-	mc_config_tsec_carveout(0, 0, true);
+	// Configure TZDRAM carveout @ 0x90000000, 1MB.
+	//mc_config_tzdram_carveout(0x90000000, 1, false);
+	mc_config_tzdram_carveout(0, 0, true);

 	MC(MC_MTS_CARVEOUT_BOM) = 0;
-	MC(MC_MTS_CARVEOUT_SIZE_MB) = 0;
-	MC(MC_MTS_CARVEOUT_ADR_HI) = 0;
 	MC(MC_MTS_CARVEOUT_REG_CTRL) = 1;

-	MC(MC_SECURITY_CARVEOUT1_BOM) = 0;
-	MC(MC_SECURITY_CARVEOUT1_BOM_HI) = 0;
 	MC(MC_SECURITY_CARVEOUT1_SIZE_128KB) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1) = 0;
 	MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2) = 0;
 	MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT1_CFG0) = 0x4000006;
+	MC(MC_SECURITY_CARVEOUT1_CFG0) = SEC_CARVEOUT_CFG_LOCKED            |
+									 SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY |
+									 SEC_CARVEOUT_CFG_APERTURE_ID(0)    |
+									 SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH;

 	MC(MC_SECURITY_CARVEOUT2_BOM) = 0x80020000;
-	MC(MC_SECURITY_CARVEOUT2_BOM_HI) = 0;
-	MC(MC_SECURITY_CARVEOUT2_SIZE_128KB) = 2;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = 0x3100000;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = 0x300;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT2_CFG0) = 0x440167E;
+	MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = SEC_CARVEOUT_CA2_R_GPU  | SEC_CARVEOUT_CA2_W_GPU | SEC_CARVEOUT_CA2_R_TSEC;

-	MC(MC_SECURITY_CARVEOUT3_BOM) = 0;
-	MC(MC_SECURITY_CARVEOUT3_BOM_HI) = 0;
-	MC(MC_SECURITY_CARVEOUT3_SIZE_128KB) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = 0x3000000;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = 0x300;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT3_CFG0) = 0x4401E7E;
-
-	MC(MC_SECURITY_CARVEOUT4_BOM) = 0;
-	MC(MC_SECURITY_CARVEOUT4_BOM_HI) = 0;
 	MC(MC_SECURITY_CARVEOUT4_SIZE_128KB) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1) = 0;
 	MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3) = 0;
 	MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT4_CFG0) = 0x8F;
+	MC(MC_SECURITY_CARVEOUT4_CFG0) = SEC_CARVEOUT_CFG_TZ_SECURE         |
+									 SEC_CARVEOUT_CFG_LOCKED            |
+									 SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY |
+									 SEC_CARVEOUT_CFG_RD_NS             |
+									 SEC_CARVEOUT_CFG_WR_NS;

-	MC(MC_SECURITY_CARVEOUT5_BOM) = 0;
-	MC(MC_SECURITY_CARVEOUT5_BOM_HI) = 0;
 	MC(MC_SECURITY_CARVEOUT5_SIZE_128KB) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1) = 0;
 	MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
-	MC(MC_SECURITY_CARVEOUT5_CFG0) = 0x8F;
+	MC(MC_SECURITY_CARVEOUT5_CFG0) = SEC_CARVEOUT_CFG_TZ_SECURE         |
+									 SEC_CARVEOUT_CFG_LOCKED            |
+									 SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY |
+									 SEC_CARVEOUT_CFG_RD_NS             |
+									 SEC_CARVEOUT_CFG_WR_NS;
 }

 void mc_enable_ahb_redirect()
@@ -157,12 +108,10 @@ bool mc_client_has_access(void *address)
 void mc_enable()
 {
 	// Reset EMC source to PLLP.
-	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF) | (2 << 29);
-	// Enable memory clocks.
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_EMC);
-	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_MEM);
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF) | (2 << 29u);
+	// Enable and clear reset for memory clocks.
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM);
 	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = BIT(CLK_X_EMC_DLL);
-	// Clear clock resets for memory.
 	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM);
 	usleep(5);

--- a/bdk/mem/mc_t210.h
+++ b/bdk/mem/mc_t210.h
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2014, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2014, NVIDIA Corporation.
+ * Copyright (c) 2018-2023, CTCaer
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
@@ -14,6 +15,22 @@
 #ifndef _MC_T210_H_
 #define _MC_T210_H_

+/*! MC SMMU registers */
+#define MC_SMMU_CONFIG               0x10
+#define MC_SMMU_TLB_CONFIG           0x14
+#define MC_SMMU_PTC_CONFIG           0x18
+#define MC_SMMU_PTB_ASID             0x1c
+#define MC_SMMU_PTB_DATA             0x20
+#define MC_SMMU_TLB_FLUSH            0x30
+#define MC_SMMU_PTC_FLUSH            0x34
+#define MC_SMMU_ASID_SECURITY        0x38
+#define MC_SMMU_TRANSLATION_ENABLE_0 0x228
+#define MC_SMMU_TRANSLATION_ENABLE_1 0x22c
+#define MC_SMMU_TRANSLATION_ENABLE_2 0x230
+#define MC_SMMU_TRANSLATION_ENABLE_3 0x234
+#define MC_SMMU_TRANSLATION_ENABLE_4 0xb98
+
+/*! MC General registers */
 #define MC_INTSTATUS                                            0x0
 #define MC_INTMASK                                              0x4
 #define MC_ERR_STATUS                                           0x8
@@ -464,7 +481,7 @@
 #define MC_UNTRANSLATED_REGION_CHECK                            0x948
 #define MC_DA_CONFIG0                                           0x9dc

-/* MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS0 */
+/*! MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS0 */
 #define SEC_CARVEOUT_CA0_R_PTCR       BIT(0)
 #define SEC_CARVEOUT_CA0_R_DISPLAY0A  BIT(1)
 #define SEC_CARVEOUT_CA0_R_DISPLAY0AB BIT(2)
@@ -484,7 +501,7 @@
 #define SEC_CARVEOUT_CA0_R_PPCSAHBSLV BIT(30)
 #define SEC_CARVEOUT_CA0_R_SATAR      BIT(31)

-/* MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS1 */
+/*! MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS1 */
 #define SEC_CARVEOUT_CA1_R_VDEBSEV    BIT(2)
 #define SEC_CARVEOUT_CA1_R_VDEMBE     BIT(3)
 #define SEC_CARVEOUT_CA1_R_VDEMCE     BIT(4)
@@ -504,7 +521,7 @@
 #define SEC_CARVEOUT_CA1_W_VDEBSEV    BIT(30)
 #define SEC_CARVEOUT_CA1_W_VDEDBG     BIT(31)

-/* MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS2 */
+/*! MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS2 */
 #define SEC_CARVEOUT_CA2_W_VDEMBE    BIT(0)
 #define SEC_CARVEOUT_CA2_W_VDETPM    BIT(1)
 #define SEC_CARVEOUT_CA2_R_ISPRA     BIT(4)
@@ -524,7 +541,7 @@
 #define SEC_CARVEOUT_CA2_W_GPU       BIT(25)
 #define SEC_CARVEOUT_CA2_R_DISPLAYT  BIT(26)

-/* MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS3 */
+/*! MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS3 */
 #define SEC_CARVEOUT_CA3_R_SDMMCA   BIT(0)
 #define SEC_CARVEOUT_CA3_R_SDMMCAA  BIT(1)
 #define SEC_CARVEOUT_CA3_R_SDMMC    BIT(2)
@@ -544,7 +561,7 @@
 #define SEC_CARVEOUT_CA3_R_NVJPG    BIT(30)
 #define SEC_CARVEOUT_CA3_W_NVJPG    BIT(31)

-/* MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS4 */
+/*! MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS4 */
 #define SEC_CARVEOUT_CA4_R_SE    BIT(0)
 #define SEC_CARVEOUT_CA4_W_SE    BIT(1)
 #define SEC_CARVEOUT_CA4_R_AXIAP BIT(2)
--- a/bdk/mem/minerva.c
+++ b/bdk/mem/minerva.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022 CTCaer
+ * Copyright (c) 2019-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -27,13 +27,18 @@
 #include <soc/t210.h>
 #include <utils/util.h>

+#define TABLE_FREQ_KHZ_OFFSET        0x40
+#define TABLE_LA_REGS_T210_OFFSET    0x1284
+#define TABLE_LA_REGS_T210B01_OFFSET 0xFA4
+#define LA_SDMMC1_INDEX 6
+
 extern volatile nyx_storage_t *nyx_str;

 void (*minerva_cfg)(mtc_config_t *mtc_cfg, void *);

 u32 minerva_init()
 {
-	u32 curr_ram_idx = 0;
+	u32 tbl_idx = 0;

 	minerva_cfg = NULL;
 	mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
@@ -98,13 +103,13 @@ u32 minerva_init()

 	// Get current frequency
 	u32 current_emc_clk_src = CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC);
-	for (curr_ram_idx = 0; curr_ram_idx < 10; curr_ram_idx++)
+	for (tbl_idx = 0; tbl_idx < mtc_cfg->table_entries; tbl_idx++)
 	{
-		if (current_emc_clk_src == mtc_cfg->mtc_table[curr_ram_idx].clk_src_emc)
+		if (current_emc_clk_src == mtc_cfg->mtc_table[tbl_idx].clk_src_emc)
 			break;
 	}

-	mtc_cfg->rate_from = mtc_cfg->mtc_table[curr_ram_idx].rate_khz;
+	mtc_cfg->rate_from = mtc_cfg->mtc_table[tbl_idx].rate_khz;
 	mtc_cfg->rate_to = FREQ_204;
 	mtc_cfg->train_mode = OP_TRAIN;
 	minerva_cfg(mtc_cfg, NULL);
@@ -140,6 +145,27 @@ void minerva_change_freq(minerva_freq_t freq)
 	}
 }

+void minerva_sdmmc_la_program(void *table, bool t210b01)
+{
+
+	u32 freq = *(u32 *)(table + TABLE_FREQ_KHZ_OFFSET);
+	u32 *la_scale_regs = (u32 *)(table + (t210b01 ? TABLE_LA_REGS_T210B01_OFFSET : TABLE_LA_REGS_T210_OFFSET));
+
+	// Adjust SDMMC1 latency allowance.
+	switch (freq)
+	{
+	case 204000:
+		la_scale_regs[LA_SDMMC1_INDEX] = (la_scale_regs[LA_SDMMC1_INDEX] & 0xFF0000) | 50;
+		break;
+	case 408000:
+		la_scale_regs[LA_SDMMC1_INDEX] = (la_scale_regs[LA_SDMMC1_INDEX] & 0xFF0000) | 25;
+		break;
+	default:
+		la_scale_regs[LA_SDMMC1_INDEX] = (la_scale_regs[LA_SDMMC1_INDEX] & 0xFF0000) | 20;
+		break;
+	}
+}
+
 void minerva_prep_boot_freq()
 {
 	if (!minerva_cfg)
@@ -157,23 +183,46 @@ void minerva_prep_boot_freq()
 	minerva_change_freq(FREQ_800);
 }

-void minerva_prep_boot_l4t(int oc_freq)
+void minerva_prep_boot_l4t(u32 oc_freq, u32 opt_custom)
 {
 	if (!minerva_cfg)
 		return;

 	mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;

+	// Program SDMMC LA regs.
+	for (u32 i = 0; i < mtc_cfg->table_entries; i++)
+		minerva_sdmmc_la_program(&mtc_cfg->mtc_table[i], false);
+
 	// Add OC frequency.
 	if (oc_freq && mtc_cfg->mtc_table[mtc_cfg->table_entries - 1].rate_khz == FREQ_1600)
 	{
 		memcpy(&mtc_cfg->mtc_table[mtc_cfg->table_entries],
 			   &mtc_cfg->mtc_table[mtc_cfg->table_entries - 1],
 			   sizeof(emc_table_t));
-		mtc_cfg->mtc_table[mtc_cfg->table_entries].rate_khz = oc_freq;
+
+		mtc_cfg->mtc_table[mtc_cfg->table_entries].opt_custom = opt_custom;
+		mtc_cfg->mtc_table[mtc_cfg->table_entries].rate_khz   = oc_freq;
 		mtc_cfg->table_entries++;
 	}

+	// Trim table.
+	int entries = 0;
+	for (u32 i = 0; i < mtc_cfg->table_entries; i++)
+	{
+		// Copy frequencies from 204/408/800 MHz and 1333+ MHz.
+		int rate = mtc_cfg->mtc_table[i].rate_khz;
+		if (rate == FREQ_204 ||
+			rate == FREQ_408 ||
+			rate == FREQ_800 ||
+			rate >= FREQ_1333)
+		{
+			memcpy(&mtc_cfg->mtc_table[entries], &mtc_cfg->mtc_table[i], sizeof(emc_table_t));
+			entries++;
+		}
+	}
+	mtc_cfg->table_entries = entries;
+
 	// Set init frequency.
 	minerva_change_freq(FREQ_204);

@@ -181,35 +230,21 @@ void minerva_prep_boot_l4t(int oc_freq)
 	mtc_cfg->train_mode = OP_TRAIN;
 	for (u32 i = 0; i < mtc_cfg->table_entries; i++)
 	{
-		mtc_cfg->rate_to = mtc_cfg->mtc_table[i].rate_khz;
-		// Skip already trained frequencies.
-		if (mtc_cfg->rate_to == FREQ_204 || mtc_cfg->rate_to == FREQ_800 || mtc_cfg->rate_to == FREQ_1600)
+		// Skip already trained frequencies and OC freq (Arachne handles it).
+		if (mtc_cfg->mtc_table[i].trained || mtc_cfg->rate_to == oc_freq)
 			continue;

 		// Train frequency.
+		mtc_cfg->rate_to = mtc_cfg->mtc_table[i].rate_khz;
 		minerva_cfg(mtc_cfg, NULL);
 	}

 	// Do FSP WAR and scale to 800 MHz as boot freq.
 	bool fsp_opwr_disabled = !(EMC(EMC_MRW3) & 0xC0);
 	if (fsp_opwr_disabled)
-		minerva_change_freq(FREQ_666);
+		minerva_change_freq(FREQ_1333);
 	minerva_change_freq(FREQ_800);

-	// Trim table.
-	int entries = 0;
-	for (u32 i = 0; i < mtc_cfg->table_entries; i++)
-	{
-		// Copy freqs from 204 MHz to 800 MHz and 1600 MHz and above.
-		int rate = mtc_cfg->mtc_table[i].rate_khz;
-		if ((rate >= FREQ_204 && rate <= FREQ_800) || rate >= FREQ_1600)
-		{
-			memcpy(&mtc_cfg->mtc_table[entries], &mtc_cfg->mtc_table[i], sizeof(emc_table_t));
-			entries++;
-		}
-	}
-	mtc_cfg->table_entries = entries;
-
 	// Do not let other mtc ops.
 	mtc_cfg->init_done = 0;
 }
--- a/bdk/mem/minerva.h
+++ b/bdk/mem/minerva.h
@@ -53,16 +53,18 @@ enum train_mode_t
 typedef enum
 {
 	FREQ_204  = 204000,
-	FREQ_666  = 665600,
+	FREQ_408  = 408000,
 	FREQ_800  = 800000,
+	FREQ_1333 = 1331200,
 	FREQ_1600 = 1600000
 } minerva_freq_t;

 extern void (*minerva_cfg)(mtc_config_t *mtc_cfg, void *);
 u32  minerva_init();
 void minerva_change_freq(minerva_freq_t freq);
+void minerva_sdmmc_la_program(void *table, bool t210b01);
 void minerva_prep_boot_freq();
-void minerva_prep_boot_l4t(int oc_freq);
+void minerva_prep_boot_l4t(u32 oc_freq, u32 opt_custom);
 void minerva_periodic_training();
 emc_table_t *minerva_get_mtc_table();
 int minerva_get_mtc_table_entries();
--- a/bdk/mem/mtc_table.h
+++ b/bdk/mem/mtc_table.h
@@ -481,7 +481,8 @@ typedef struct
 	u32 rate_khz;
 	u32 min_volt;
 	u32 gpu_min_volt;
-	char clock_src[32];
+	char clock_src[28];
+	u32 opt_custom;
 	u32 clk_src_emc;
 	u32 needs_training;
 	u32 training_pattern;
--- a/bdk/mem/sdram.c
+++ b/bdk/mem/sdram.c
@@ -42,8 +42,8 @@
 typedef struct _sdram_vendor_patch_t
 {
 	u32 val;
-	u32 offset:16;
 	u32 dramcf:16;
+	u32 offset:16;
 } sdram_vendor_patch_t;

 static const u8 dram_encoding_t210b01[] = {
@@ -67,21 +67,21 @@ static const u8 dram_encoding_t210b01[] = {
 /* 17 */	LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL,
 /* 18 */	LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL,
 /* 19 */	LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL,
-/* 20 */	LPDDR4X_4GB_SAMSUNG_1Z,
-/* 21 */	LPDDR4X_4GB_SAMSUNG_1Z,
-/* 22 */	LPDDR4X_4GB_SAMSUNG_1Z,
+/* 20 */	LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL,
+/* 21 */	LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL,
+/* 22 */	LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL,
 /* 23 */	LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL,
 /* 24 */	LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL,
 /* 25 */	LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF,
 /* 26 */	LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF,
 /* 27 */	LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF,
 /* 28 */	LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL,
-/* 29 */	LPDDR4X_4GB_HYNIX_1A,
-/* 30 */	LPDDR4X_4GB_HYNIX_1A,
-/* 31 */	LPDDR4X_4GB_HYNIX_1A,
-/* 32 */	LPDDR4X_4GB_MICRON_1A,
-/* 33 */	LPDDR4X_4GB_MICRON_1A,
-/* 34 */	LPDDR4X_4GB_MICRON_1A,
+/* 29 */	LPDDR4X_4GB_HYNIX_H54G46CYRBX267,
+/* 30 */	LPDDR4X_4GB_HYNIX_H54G46CYRBX267,
+/* 31 */	LPDDR4X_4GB_HYNIX_H54G46CYRBX267,
+/* 32 */	LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB,
+/* 33 */	LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB,
+/* 34 */	LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB,
 };

 #include "sdram_config.inl"
@@ -127,15 +127,19 @@ static void _sdram_req_mrr_data(u32 data, bool dual_channel)
 emc_mr_data_t sdram_read_mrx(emc_mr_t mrx)
 {
 	emc_mr_data_t data;
-	u32 dual_channel = (EMC(EMC_FBIO_CFG7) >> 2) & 1;
+	u32 mrr;
+	bool dual_rank    = EMC(EMC_ADR_CFG) & 1;
+	bool dual_channel = (EMC(EMC_FBIO_CFG7) >> 2) & 1; // Each EMC channel is a RAM chip module.

 	// Clear left overs.
-	for (u32 i = 0; i < 32; i++)
+	for (u32 i = 0; i < 16; i++)
 	{
 		(void)EMC(EMC_MRR);
 		usleep(1);
 	}

+	memset(&data, 0xFF, sizeof(emc_mr_data_t));
+
 	/*
 	 * When a dram chip has only one rank, then the info from the 2 ranks differs.
 	 * Info not matching is only allowed on different channels.
@@ -143,21 +147,38 @@ emc_mr_data_t sdram_read_mrx(emc_mr_t mrx)

 	// Get Device 0 (Rank 0) info from both dram chips (channels).
 	_sdram_req_mrr_data((2u << 30) | (mrx << 16), dual_channel);
-	data.rank0_ch0 = EMC(EMC_MRR) & 0xFF;
-	data.rank0_ch1 = (EMC(EMC_MRR) & 0xFF00 >> 8);
+
+	// Ram module 0 info.
+	mrr = EMC_CH0(EMC_MRR);
+	data.chip0.rank0_ch0 = mrr & 0xFF;
+	data.chip0.rank0_ch1 = (mrr & 0xFF00 >> 8);
+
+	// Ram module 1 info.
+	if (dual_channel)
+	{
+		mrr = EMC_CH1(EMC_MRR);
+		data.chip1.rank0_ch0 = mrr & 0xFF;
+		data.chip1.rank0_ch1 = (mrr & 0xFF00 >> 8);
+	}

 	// If Rank 1 exists, get info.
-	if (EMC(EMC_ADR_CFG) & 1)
+	if (dual_rank)
 	{
 		// Get Device 1 (Rank 1) info from both dram chips (channels).
 		_sdram_req_mrr_data((1u << 30) | (mrx << 16), dual_channel);
-		data.rank1_ch0 = EMC(EMC_MRR) & 0xFF;
-		data.rank1_ch1 = (EMC(EMC_MRR) & 0xFF00 >> 8);
-	}
-	else
-	{
-		data.rank1_ch0 = 0xFF;
-		data.rank1_ch1 = 0xFF;
+
+		// Ram module 0 info.
+		mrr = EMC_CH0(EMC_MRR);
+		data.chip0.rank1_ch0 = mrr & 0xFF;
+		data.chip0.rank1_ch1 = (mrr & 0xFF00 >> 8);
+
+		// Ram module 1 info.
+		if (dual_channel)
+		{
+			mrr = EMC_CH1(EMC_MRR);
+			data.chip1.rank1_ch0 = mrr & 0xFF;
+			data.chip1.rank1_ch1 = (mrr & 0xFF00 >> 8);
+		}
 	}

 	return data;
@@ -167,12 +188,12 @@ static void _sdram_config_t210(const sdram_params_t210_t *params)
 {
 	// Program DPD3/DPD4 regs (coldboot path).
 	// Enable sel_dpd on unused pins.
-	u32 dpd_req = (params->emc_pmc_scratch1 & 0x3FFFFFFF) | 0x80000000;
+	u32 dpd_req = (params->emc_pmc_scratch1 & 0x3FFFFFFF) | (2 << 30u);
 	PMC(APBDEV_PMC_IO_DPD3_REQ) = (dpd_req ^ 0xFFFF) & 0xC000FFFF;
 	usleep(params->pmc_io_dpd3_req_wait);

 	// Disable e_dpd_vttgen.
-	dpd_req = (params->emc_pmc_scratch2 & 0x3FFFFFFF) | 0x80000000;
+	dpd_req = (params->emc_pmc_scratch2 & 0x3FFFFFFF) | (2 << 30u);
 	PMC(APBDEV_PMC_IO_DPD4_REQ) = (dpd_req & 0xFFFF0000) ^ 0x3FFF0000;
 	usleep(params->pmc_io_dpd4_req_wait);

@@ -209,7 +230,7 @@ break_nosleep:
 	if (params->emc_clock_source_dll)
 		CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL) = params->emc_clock_source_dll;
 	if (params->clear_clock2_mc1)
-		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_CLR) = 0x40000000; // Clear Reset to MC1.
+		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_CLR) = BIT(CLK_W_MC1); // Clear Reset to MC1.

 	// Enable and clear reset for memory clocks.
 	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM);
@@ -233,7 +254,7 @@ break_nosleep:

 	// Program CMD mapping. Required before brick mapping, else
 	// we can't guarantee CK will be differential at all times.
-	EMC(EMC_FBIO_CFG7) = params->emc_fbio_cfg7;
+	EMC(EMC_FBIO_CFG7)          = params->emc_fbio_cfg7;
 	EMC(EMC_CMD_MAPPING_CMD0_0) = params->emc_cmd_mapping_cmd0_0;
 	EMC(EMC_CMD_MAPPING_CMD0_1) = params->emc_cmd_mapping_cmd0_1;
 	EMC(EMC_CMD_MAPPING_CMD0_2) = params->emc_cmd_mapping_cmd0_2;
@@ -246,7 +267,7 @@ break_nosleep:
 	EMC(EMC_CMD_MAPPING_CMD3_0) = params->emc_cmd_mapping_cmd3_0;
 	EMC(EMC_CMD_MAPPING_CMD3_1) = params->emc_cmd_mapping_cmd3_1;
 	EMC(EMC_CMD_MAPPING_CMD3_2) = params->emc_cmd_mapping_cmd3_2;
-	EMC(EMC_CMD_MAPPING_BYTE) = params->emc_cmd_mapping_byte;
+	EMC(EMC_CMD_MAPPING_BYTE)   = params->emc_cmd_mapping_byte;

 	// Program brick mapping.
 	EMC(EMC_PMACRO_BRICK_MAPPING_0) = params->emc_pmacro_brick_mapping0;
@@ -289,13 +310,13 @@ break_nosleep:
 	EMC(EMC_AUTO_CAL_CONFIG7) = params->emc_auto_cal_config7;
 	EMC(EMC_AUTO_CAL_CONFIG8) = params->emc_auto_cal_config8;

-	EMC(EMC_PMACRO_RX_TERM)    = params->emc_pmacro_rx_term;
-	EMC(EMC_PMACRO_DQ_TX_DRV)  = params->emc_pmacro_dq_tx_drive;
-	EMC(EMC_PMACRO_CA_TX_DRV)  = params->emc_pmacro_ca_tx_drive;
-	EMC(EMC_PMACRO_CMD_TX_DRV) = params->emc_pmacro_cmd_tx_drive;
+	EMC(EMC_PMACRO_RX_TERM)            = params->emc_pmacro_rx_term;
+	EMC(EMC_PMACRO_DQ_TX_DRV)          = params->emc_pmacro_dq_tx_drive;
+	EMC(EMC_PMACRO_CA_TX_DRV)          = params->emc_pmacro_ca_tx_drive;
+	EMC(EMC_PMACRO_CMD_TX_DRV)         = params->emc_pmacro_cmd_tx_drive;
 	EMC(EMC_PMACRO_AUTOCAL_CFG_COMMON) = params->emc_pmacro_auto_cal_common;
-	EMC(EMC_AUTO_CAL_CHANNEL)  = params->emc_auto_cal_channel;
-	EMC(EMC_PMACRO_ZCTRL)      = params->emc_pmacro_zcrtl;
+	EMC(EMC_AUTO_CAL_CHANNEL)          = params->emc_auto_cal_channel;
+	EMC(EMC_PMACRO_ZCTRL)              = params->emc_pmacro_zcrtl;

 	EMC(EMC_DLL_CFG_0)     = params->emc_dll_cfg0;
 	EMC(EMC_DLL_CFG_1)     = params->emc_dll_cfg1;
@@ -328,7 +349,7 @@ break_nosleep:
 	EMC(EMC_PMACRO_CMD_RX_TERM_MODE)     = params->emc_pmacro_cmd_rx_term_mode;
 	EMC(EMC_PMACRO_CMD_PAD_TX_CTRL)      = params->emc_pmacro_cmd_pad_tx_ctrl;

-	EMC(EMC_CFG_3) = params->emc_cfg3;
+	EMC(EMC_CFG_3)                   = params->emc_cfg3;
 	EMC(EMC_PMACRO_TX_PWRD_0)        = params->emc_pmacro_tx_pwrd0;
 	EMC(EMC_PMACRO_TX_PWRD_1)        = params->emc_pmacro_tx_pwrd1;
 	EMC(EMC_PMACRO_TX_PWRD_2)        = params->emc_pmacro_tx_pwrd2;
@@ -561,9 +582,11 @@ break_nosleep:

 	EMC(EMC_PMACRO_COMMON_PAD_TX_CTRL) = params->emc_pmacro_common_pad_tx_ctrl;
 	EMC(EMC_DBG)                 = params->emc_dbg;
+
 	EMC(EMC_QRST)                = params->emc_qrst;
 	EMC(EMC_ISSUE_QRST)          = 1;
 	EMC(EMC_ISSUE_QRST)          = 0;
+
 	EMC(EMC_QSAFE)               = params->emc_qsafe;
 	EMC(EMC_RDV)                 = params->emc_rdv;
 	EMC(EMC_RDV_MASK)            = params->emc_rdv_mask;
@@ -616,7 +639,7 @@ break_nosleep:
 	}

 	// Release SEL_DPD_CMD.
-	PMC(APBDEV_PMC_IO_DPD3_REQ) = ((params->emc_pmc_scratch1 & 0x3FFFFFFF) | 0x40000000) & 0xCFFF0000;
+	PMC(APBDEV_PMC_IO_DPD3_REQ) = (params->emc_pmc_scratch1 & 0xFFF0000) | (1 << 30u);
 	usleep(params->pmc_io_dpd3_req_wait);

 	// Set autocal interval if not configured.
@@ -707,7 +730,7 @@ break_nosleep:
 		EMC(EMC_REF) = (((1 << params->emc_extra_refresh_num) - 1) << 8) | (params->emc_dev_select << 30) | 3;

 	// Enable refresh.
-	EMC(EMC_REFCTRL) = params->emc_dev_select | 0x80000000;
+	EMC(EMC_REFCTRL) = params->emc_dev_select | BIT(31);

 	EMC(EMC_DYN_SELF_REF_CONTROL) = params->emc_dyn_self_ref_control;
 	EMC(EMC_CFG_UPDATE)    = params->emc_cfg_update;
@@ -717,7 +740,7 @@ break_nosleep:
 	EMC(EMC_SEL_DPD_CTRL)  = params->emc_sel_dpd_ctrl;

 	// Write addr swizzle lock bit.
-	EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare | 2;
+	EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare | BIT(1);

 	EMC(EMC_TIMING_CONTROL) = 1; // Re-trigger timing to latch power saving functions.

@@ -751,15 +774,15 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params)
 	// Program DPD3/DPD4 regs (coldboot path).
 	// Enable sel_dpd on unused pins.
 	PMC(APBDEV_PMC_WEAK_BIAS)   = (pmc_scratch1 & 0x1000) << 19 | (pmc_scratch1 & 0xFFF) << 18 | (pmc_scratch1 & 0x8000) << 15;
-	PMC(APBDEV_PMC_IO_DPD3_REQ) = (pmc_scratch1 & 0x9FFF) + 0x80000000;
+	PMC(APBDEV_PMC_IO_DPD3_REQ) = (pmc_scratch1 & 0x9FFF) | (2 << 30u);
 	usleep(params->pmc_io_dpd3_req_wait);

 	// Disable e_dpd_vttgen.
-	PMC(APBDEV_PMC_IO_DPD4_REQ) = (pmc_scratch2 & 0x3FFF0000) | 0x80000000;
+	PMC(APBDEV_PMC_IO_DPD4_REQ) = (pmc_scratch2 & 0x3FFF0000) | (2 << 30u);
 	usleep(params->pmc_io_dpd4_req_wait);

 	// Disable e_dpd_bg.
-	PMC(APBDEV_PMC_IO_DPD4_REQ) = (pmc_scratch2 & 0x1FFF) | 0x80000000;
+	PMC(APBDEV_PMC_IO_DPD4_REQ) = (pmc_scratch2 & 0x1FFF) | (2 << 30u);
 	usleep(1);

 	// Program CMD mapping. Required before brick mapping, else
@@ -1155,9 +1178,11 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params)
 	EMC(EMC_PUTERM_WIDTH)    = params->emc_puterm_width;

 	EMC(EMC_DBG)                 = params->emc_dbg;
+
 	EMC(EMC_QRST)                = params->emc_qrst;
 	EMC(EMC_ISSUE_QRST)          = 1;
 	EMC(EMC_ISSUE_QRST)          = 0;
+
 	EMC(EMC_QSAFE)               = params->emc_qsafe;
 	EMC(EMC_RDV)                 = params->emc_rdv;
 	EMC(EMC_RDV_MASK)            = params->emc_rdv_mask;
@@ -1219,7 +1244,7 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params)
 		*(vu32 *)params->emc_bct_spare_secure16 = params->emc_bct_spare_secure17;

 	// Release SEL_DPD_CMD.
-	PMC(APBDEV_PMC_IO_DPD3_REQ) = ((params->emc_pmc_scratch1 & 0x3FFFFFFF) | 0x40000000) & 0xCFFF0000;
+	PMC(APBDEV_PMC_IO_DPD3_REQ) = (params->emc_pmc_scratch1 & 0xFFF0000) | (1 << 30u);
 	usleep(params->pmc_io_dpd3_req_wait);

 	// Set transmission pad control parameters.
@@ -1315,7 +1340,7 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params)
 		EMC(EMC_REF) = ((1 << params->emc_extra_refresh_num << 8) - 253) | (params->emc_dev_select << 30);

 	// Enable refresh.
-	EMC(EMC_REFCTRL) = params->emc_dev_select | 0x80000000;
+	EMC(EMC_REFCTRL) = params->emc_dev_select | BIT(31);

 	EMC(EMC_DYN_SELF_REF_CONTROL) = params->emc_dyn_self_ref_control;
 	EMC(EMC_CFG)           = params->emc_cfg;
@@ -1324,7 +1349,7 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params)
 	EMC(EMC_SEL_DPD_CTRL)  = params->emc_sel_dpd_ctrl;

 	// Write addr swizzle lock bit.
-	EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare | 2;
+	EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare | BIT(1);

 	EMC(EMC_TIMING_CONTROL) = 1; // Re-trigger timing to latch power saving functions.

--- a/bdk/mem/sdram.h
+++ b/bdk/mem/sdram.h
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
- * Copyright (c) 2020-2023 CTCaer
+ * Copyright (c) 2020-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -23,81 +23,86 @@
 /*
 * Tegra X1/X1+ EMC/DRAM Bandwidth Chart:
 *
- * Note: BWbits T210    = Hz x ddr x bus width x channels = Hz x 2 x 32 x 2.
- *       BWbits T210B01 = Hz x ddr x bus width x channels = Hz x 2 x 64 x 2.
- *       Both assume that both sub-partitions are used and thus reaching max
- *       bandwidth per channel. (T210: 2x16-bit, T210B01: 2x32-bit).
- *       Retail Mariko use one sub-partition, in order to meet Erista perf.
- *
- *              T210   T210B01
- *   40.8 MHz:  0.61   1.22 GiB/s
- *   68.0 MHz:  1.01   2.02 GiB/s
- *  102.0 MHz:  1.52   3.04 GiB/s
- *  204.0 MHz:  3.04   6.08 GiB/s <-- Tegra X1/X1+ Init/SC7 Frequency
- *  408.0 MHz:  6.08  12.16 GiB/s
- *  665.6 MHz:  9.92  19.84 GiB/s
- *  800.0 MHz: 11.92  23.84 GiB/s <-- Tegra X1/X1+ Nvidia OS Boot Frequency
- * 1065.6 MHz: 15.89  31.78 GiB/s
- * 1331.2 MHz: 19.84  39.68 GiB/s
- * 1600.0 MHz: 23.84  47.68 GiB/s <-- Tegra X1/X1+ HOS Max Frequency
- * 1862.4 MHz: 27.75  55.50 GiB/s <-- Tegra X1  Official Max Frequency
- * 2131.2 MHz: 31.76  63.52 GiB/s <-- Tegra X1+ Official Max Frequency
+ * Note: Max BWbits = Hz x ddr x bus width x channels = Hz x 2 x 32 x 2.
+ *       Max BWbits = Hz x ddr x bus width x channels = Hz x 2 x 64 x 1.
+ *       Configurations supported: 1x32, 2x32, 1x64.
+ *       x64 ram modules can be used by combining the 2 32-bit channels into one.
 *
+ *  204.0 MHz:  3.04 <-- Tegra X1/X1+ Init/SC7 Frequency
+ *  408.0 MHz:  6.08
+ *  665.6 MHz:  9.92
+ *  800.0 MHz: 11.92 <-- Tegra X1/X1+ Nvidia OS Boot Frequency
+ * 1065.6 MHz: 15.89
+ * 1331.2 MHz: 19.84
+ * 1600.0 MHz: 23.84
+ * 1862.4 MHz: 27.75 <-- Tegra X1  Official Max Frequency
+ * 2131.2 MHz: 31.76 <-- Tegra X1+ Official Max Frequency. Not all regs have support for > 2046 MHz.
 */

 enum sdram_ids_erista
 {
 	// LPDDR4 3200Mbps.
-	LPDDR4_ICOSA_4GB_SAMSUNG_K4F6E304HB_MGCH        = 0,
-	LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE       = 1,
-	LPDDR4_ICOSA_4GB_MICRON_MT53B512M32D2NP_062_WT  = 2, // WT:C.
+	LPDDR4_ICOSA_4GB_SAMSUNG_K4F6E304HB_MGCH        = 0, // Die-B. (2y-01).
+	LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE       = 1, // Die-M. (2y-01).
+	LPDDR4_ICOSA_4GB_MICRON_MT53B512M32D2NP_062_WTC = 2, // Die-C. (2y-01).

-	LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH        = 4,
+	LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH        = 4, // Die-C. (2y-01).
+
+	// Custom hekate/L4T supported 8GB. 7 dram id can be easily applied in fuses.
+	LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX        = 7, // XX: CH/CJ/CL.
 };

 enum sdram_ids_mariko
 {
+	/*
+	 * Nintendo Switch LPDRR4X generations:
+	 * - 1x   nm are 1st-gen
+	 * - 1y   nm are 2nd-gen
+	 * - 1z/a nm are 3rd-gen
+	 */
+
 	// LPDDR4X 4266Mbps.
-	LPDDR4X_HOAG_4GB_HYNIX_H9HCNNNBKMMLXR_NEE       = 3, // Replaced from Copper. Die-M. (1y-01).
-	LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE       = 5, // Replaced from Copper. Die-M. (1y-01).
-	LPDDR4X_AULA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE       = 6, // Replaced from Copper. Die-M. (1y-01).
+	LPDDR4X_HOAG_4GB_HYNIX_H9HCNNNBKMMLXR_NEE       = 3, // Die-M. (1y-01).
+	LPDDR4X_AULA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE       = 5, // Die-M. (1y-01).
+	LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE       = 6, // Die-M. (1y-01).

 	// LPDDR4X 3733Mbps.
-	LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AM_MGCJ        = 8,  // Die-M. 1st gen. 8 banks. 3733Mbps.
-	LPDDR4X_IOWA_8GB_SAMSUNG_K4UBE3D4AM_MGCJ        = 9,  // Die-M.
-	LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLHR_NME       = 10, // Die-M.
-	LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WTE = 11, // 4266Mbps. Die-E.
+	LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AM_MGCJ        = 8,  // Die-M. (1x-03).
+	LPDDR4X_IOWA_8GB_SAMSUNG_K4UBE3D4AM_MGCJ        = 9,  // Die-M. (1x-03).
+	LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLHR_NME       = 10, // Die-M. (1x-03).
+	LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WTE = 11, // Die-E. (1x-03). D9WGB. 4266Mbps.

-	LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AM_MGCJ        = 12, // Die-M. 1st gen. 8 banks. 3733Mbps.
-	LPDDR4X_HOAG_8GB_SAMSUNG_K4UBE3D4AM_MGCJ        = 13, // Die-M.
-	LPDDR4X_HOAG_4GB_HYNIX_H9HCNNNBKMMLHR_NME       = 14, // Die-M.
-	LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTE = 15, // 4266Mbps. Die-E.
+	LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AM_MGCJ        = 12, // Die-M. (1x-03).
+	LPDDR4X_HOAG_8GB_SAMSUNG_K4UBE3D4AM_MGCJ        = 13, // Die-M. (1x-03).
+	LPDDR4X_HOAG_4GB_HYNIX_H9HCNNNBKMMLHR_NME       = 14, // Die-M. (1x-03).
+	LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTE = 15, // Die-E. (1x-03). D9WGB. 4266Mbps.

 	// LPDDR4X 4266Mbps.
-	LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AA_MGCL        = 17, // Die-A. (1y-X03). 2nd gen. 8 banks. 4266Mbps.
+	LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AA_MGCL        = 17, // Die-A. (1y-X03).
 	LPDDR4X_IOWA_8GB_SAMSUNG_K4UBE3D4AA_MGCL        = 18, // Die-A. (1y-X03).
-	LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AA_MGCL        = 19, // Die-A. (1y-X03). 2nd gen. 8 banks. 4266Mbps.
+	LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AA_MGCL        = 19, // Die-A. (1y-X03).

-	LPDDR4X_IOWA_4GB_SAMSUNG_1Z                     = 20, // 1z nm. 40% lower power usage. (1z-01).
-	LPDDR4X_HOAG_4GB_SAMSUNG_1Z                     = 21, // 1z nm. 40% lower power usage. (1z-01).
-	LPDDR4X_AULA_4GB_SAMSUNG_1Z                     = 22, // 1z nm. 40% lower power usage. (1z-01).
+	LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AB_MGCL        = 20, // Die-B. (1z-01). 40% lp.
+	LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AB_MGCL        = 21, // Die-B. (1z-01). 40% lp.
+	LPDDR4X_AULA_4GB_SAMSUNG_K4U6E3S4AB_MGCL        = 22, // Die-B. (1z-01). 40% lp.

 	LPDDR4X_HOAG_8GB_SAMSUNG_K4UBE3D4AA_MGCL        = 23, // Die-A. (1y-X03).
-	LPDDR4X_AULA_4GB_SAMSUNG_K4U6E3S4AA_MGCL        = 24, // Die-A. (1y-X03). 2nd gen. 8 banks. 4266Mbps.
+	LPDDR4X_AULA_4GB_SAMSUNG_K4U6E3S4AA_MGCL        = 24, // Die-A. (1y-X03).

-	LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WTF = 25, // 4266Mbps. Die-F. D9XRR. 10nm-class (1y-01).
-	LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTF = 26, // 4266Mbps. Die-F. D9XRR. 10nm-class (1y-01).
-	LPDDR4X_AULA_4GB_MICRON_MT53E512M32D2NP_046_WTF = 27, // 4266Mbps. Die-F. D9XRR. 10nm-class (1y-01).
+	LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WTF = 25, // Die-F. (1y-01). D9XRR.
+	LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTF = 26, // Die-F. (1y-01). D9XRR.
+	LPDDR4X_AULA_4GB_MICRON_MT53E512M32D2NP_046_WTF = 27, // Die-F. (1y-01). D9XRR.

-	LPDDR4X_AULA_8GB_SAMSUNG_K4UBE3D4AA_MGCL        = 28, // Die-A.
+	LPDDR4X_AULA_8GB_SAMSUNG_K4UBE3D4AA_MGCL        = 28, // Die-A. (1y-X03). 2nd gen.

-	LPDDR4X_UNK0_4GB_HYNIX_1A                       = 29, // 1a nm. 61% lower power usage. (1a-01).
-	LPDDR4X_UNK1_4GB_HYNIX_1A                       = 30, // 1a nm. 61% lower power usage. (1a-01).
-	LPDDR4X_UNK2_4GB_HYNIX_1A                       = 31, // 1a nm. 61% lower power usage. (1a-01).
+	// Old naming scheme: H9HCNNNBKMCLXR-NEE
+	LPDDR4X_IOWA_4GB_HYNIX_H54G46CYRBX267           = 29, // Die-C. (1a-01). 61% lp.
+	LPDDR4X_HOAG_4GB_HYNIX_H54G46CYRBX267           = 30, // Die-C. (1a-01). 61% lp.
+	LPDDR4X_AULA_4GB_HYNIX_H54G46CYRBX267           = 31, // Die-C. (1a-01). 61% lp.

-	LPDDR4X_UNK0_4GB_MICRON_1A                      = 32, // 1a nm. 61% lower power usage. (1a-01).
-	LPDDR4X_UNK1_4GB_MICRON_1A                      = 33, // 1a nm. 61% lower power usage. (1a-01).
-	LPDDR4X_UNK2_4GB_MICRON_1A                      = 34, // 1a nm. 61% lower power usage. (1a-01).
+	LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D1NP_046_WTB = 32, // Die-B. (1a-01). D8BQM. 61% lp.
+	LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D1NP_046_WTB = 33, // Die-B. (1a-01). D8BQM. 61% lp.
+	LPDDR4X_AULA_4GB_MICRON_MT53E512M32D1NP_046_WTB = 34, // Die-B. (1a-01). D8BQM. 61% lp.
 };

 enum sdram_codes_mariko
@@ -112,12 +117,11 @@ enum sdram_codes_mariko
 	LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE = 2, // DRAM IDs: 11, 15.
 	LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL        = 3, // DRAM IDs: 17, 19, 24.
 	LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL        = 4, // DRAM IDs: 18, 23, 28.
-	LPDDR4X_4GB_SAMSUNG_1Z                     = 5, // DRAM IDs: 20, 21, 22.
+	LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL        = 5, // DRAM IDs: 20, 21, 22.
 	LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF = 6, // DRAM IDs: 25, 26, 27.
 	LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE       = 7, // DRAM IDs: 03, 05, 06.
-
-	LPDDR4X_4GB_HYNIX_1A                       = 8, // DRAM IDs: 29, 30, 31.
-	LPDDR4X_4GB_MICRON_1A                      = 9, // DRAM IDs: 32, 33, 34.
+	LPDDR4X_4GB_HYNIX_H54G46CYRBX267           = 8, // DRAM IDs: 29, 30, 31.
+	LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB = 9, // DRAM IDs: 32, 33, 34.
 };

 void sdram_init();
--- a/bdk/mem/sdram_config.inl
+++ b/bdk/mem/sdram_config.inl
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
- * Copyright (c) 2020-2022 CTCaer
+ * Copyright (c) 2020-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -434,9 +434,9 @@ static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = {
 	.emc_dll_cfg0                                    = 0x1F13412F,
 	.emc_dll_cfg1                                    = 0x00010014,

-	.emc_pmc_scratch1                                = 0x4FAFFFFF,
+	.emc_pmc_scratch1                                = 0x4FAFFFFF, // APBDEV_PMC_IO_DPD3_REQ.
 	.emc_pmc_scratch2                                = 0x7FFFFFFF,
-	.emc_pmc_scratch3                                = 0x4006D70B,
+	.emc_pmc_scratch3                                = 0x4006D70B, // APBDEV_PMC_DDR_CNTRL.

 	.emc_pmacro_pad_cfg_ctrl                         = 0x00020000,
 	.emc_pmacro_vttgen_ctrl0                         = 0x00030808,
@@ -489,8 +489,8 @@ static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = {

 	/* DRAM size information */
 	.mc_emem_adr_cfg                                 = 0x00000001, // 2 Ranks.
-	.mc_emem_adr_cfg_dev0                            = 0x00070302, // Rank 0 Density 512MB.
-	.mc_emem_adr_cfg_dev1                            = 0x00070302, // Rank 1 Density 512MB.
+	.mc_emem_adr_cfg_dev0                            = 0x00070302, // Chip 0 Density 512MB.
+	.mc_emem_adr_cfg_dev1                            = 0x00070302, // Chip 1 Density 512MB.
 	.mc_emem_adr_cfg_channel_mask                    = 0xFFFF2400,
 	.mc_emem_adr_cfg_bank_mask0                      = 0x6E574400,
 	.mc_emem_adr_cfg_bank_mask1                      = 0x39722800,
@@ -499,7 +499,7 @@ static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = {
 	 * Specifies the value for MC_EMEM_CFG which holds the external memory
 	 * size (in KBytes)
 	 */
-	.mc_emem_cfg                                     = 0x00001000, // 4GB total density.
+	.mc_emem_cfg                                     = 0x00001000, // 4GB total density. Max 8GB.

 	/* MC arbitration configuration */
 	.mc_emem_arb_cfg                                 = 0x08000001,
@@ -542,16 +542,18 @@ static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = {
 	.mc_video_protect_bom_adr_hi                     = 0x00000000,
 	.mc_video_protect_size_mb                        = 0x00000000,

-	// AFI, BPMP, HC, ISP2, CCPLEX, PPCS (AHB), SATA, VI, XUSB_HOST, XUSB_DEV, ADSP, PPCS1 (AHB), DC1, SDMMC1A, SDMMC2A, SDMMC3A.
-	.mc_video_protect_vpr_override                   = 0xE4BAC343,
-	// SDMMC4A, ISP2B, PPCS2 (AHB), APE, SE, HC1, SE1, AXIAP, ETR.
-	.mc_video_protect_vpr_override1                  = 0x00001ED3,
+	// AFI, BPMP, HC, ISP2, CCPLEX, PPCS (AHB), SATA, VI, XUSB_HOST, XUSB_DEV, ADSP, PPCS1 (AHB), DC1, SDMMC1A, SDMMC2A, SDMMC3A. Plus TSEC, NVENC.
+	.mc_video_protect_vpr_override                   = 0xE4FACB43, // Default: 0xE4BAC343. New: 0xE4FACB43. + TSEC,  NVENC.
+	// SDMMC4A, ISP2B, PPCS2 (AHB), APE, SE, HC1, SE1, AXIAP, ETR. Plus TSECB, TSEC1, TSECB1.
+	.mc_video_protect_vpr_override1                  = 0x0000FED3, // Default: 0x00001ED3. New: 0x0000FED3. + TSECB, TSEC1, TSECB1.
+
+	.mc_video_protect_gpu_override0                  = 0x2A800000, // Default: 0x00000000. Forced to 1 by HOS Secmon.
+	.mc_video_protect_gpu_override1                  = 0x00000002, // Default: 0x00000000. Forced to 0 by HOS Secmon.

-	.mc_video_protect_gpu_override0                  = 0x00000000,
-	.mc_video_protect_gpu_override1                  = 0x00000000,
 	.mc_sec_carveout_bom                             = 0xFFF00000,
 	.mc_sec_carveout_adr_hi                          = 0x00000000,
 	.mc_sec_carveout_size_mb                         = 0x00000000,
+
 	.mc_video_protect_write_access                   = 0x00000000,
 	.mc_sec_carveout_protect_write_access            = 0x00000000,

@@ -646,53 +648,27 @@ static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = {
 	.mc_mts_carveout_reg_ctrl                        = 0x00000000
 };

+#define DCFG_OFFSET_OF(m) (OFFSET_OF(sdram_params_t210_t, m) / 4)
 static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210[] = {
 	// Hynix timing config.
-	{ 0x0000000D, 0x10C / 4, DRAM_ID(1) }, // emc_r2w.
-	{ 0x00000001, 0x16C / 4, DRAM_ID(1) }, // emc_puterm_extra.
-	{ 0x80000000, 0x170 / 4, DRAM_ID(1) }, // emc_puterm_width.
-	{ 0x00000210, 0x4F4 / 4, DRAM_ID(1) }, // emc_pmacro_data_rx_term_mode.
-	{ 0x00000005, 0x5C0 / 4, DRAM_ID(1) }, // mc_emem_arb_timing_r2w.
+	{ 0x0000000D, DRAM_ID(LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE), DCFG_OFFSET_OF(emc_r2w)                      },
+	{ 0x00000001, DRAM_ID(LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE), DCFG_OFFSET_OF(emc_puterm_extra)             },
+	{ 0x80000000, DRAM_ID(LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE), DCFG_OFFSET_OF(emc_puterm_width)             },
+	{ 0x00000210, DRAM_ID(LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE), DCFG_OFFSET_OF(emc_pmacro_data_rx_term_mode) },
+	{ 0x00000005, DRAM_ID(LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE), DCFG_OFFSET_OF(mc_emem_arb_timing_r2w)       },

 	// Samsung 6GB density config.
-	{ 0x000C0302, 0x56C / 4, DRAM_ID(4) }, // mc_emem_adr_cfg_dev0. 768MB Rank 0 density.
-	{ 0x000C0302, 0x570 / 4, DRAM_ID(4) }, // mc_emem_adr_cfg_dev1. 768MB Rank 1 density.
-	{ 0x00001800, 0x584 / 4, DRAM_ID(4) }, // mc_emem_cfg. 6GB total density.
+	{ 0x000C0302, DRAM_ID(LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH),  DCFG_OFFSET_OF(mc_emem_adr_cfg_dev0)         }, // 768MB Chip 0 density.
+	{ 0x000C0302, DRAM_ID(LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH),  DCFG_OFFSET_OF(mc_emem_adr_cfg_dev1)         }, // 768MB Chip 1 density.
+	{ 0x00001800, DRAM_ID(LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH),  DCFG_OFFSET_OF(mc_emem_cfg)                  }, // 6GB total density. Max 8GB.

-#ifdef CONFIG_SDRAM_COPPER_SUPPORT
-	// Copper prototype Samsung/Hynix/Micron timing configs.
-	{ 0x0000003A,  0xEC / 4, DRAM_ID(6) },              // emc_rfc. Auto refresh.
-	{ 0x0000001D,  0xF0 / 4, DRAM_ID(6) },              // emc_rfc_pb. Bank Auto refresh.
-	{ 0x0000000D, 0x10C / 4, DRAM_ID(5) },              // emc_r2w.
-	{ 0x00000001, 0x16C / 4, DRAM_ID(5) },              // emc_puterm_extra.
-	{ 0x80000000, 0x170 / 4, DRAM_ID(5) },              // emc_puterm_width.
-	{ 0x00000012, 0x1B0 / 4, DRAM_ID(3) | DRAM_ID(5) | DRAM_ID(6) }, // emc_rw2pden.
-	{ 0x0000003B, 0x1C0 / 4, DRAM_ID(6) },              // emc_txsr.
-	{ 0x0000003B, 0x1C4 / 4, DRAM_ID(6) },              // emc_txsr_dll.
-	{ 0x00000003, 0x1DC / 4, DRAM_ID(3) | DRAM_ID(5) | DRAM_ID(6) }, // emc_tclkstable.
-	{ 0x00120015, 0x334 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dq_rank0_4.
-	{ 0x00160012, 0x338 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dq_rank0_5.
-	{ 0x00120015, 0x34C / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dq_rank1_4.
-	{ 0x00160012, 0x350 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dq_rank1_5.
-	{ 0x002F0032, 0x354 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_0.
-	{ 0x00310032, 0x358 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_1.
-	{ 0x00360034, 0x35C / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_2.
-	{ 0x0033002F, 0x360 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_3.
-	{ 0x00000006, 0x364 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_4.
-	{ 0x002F0032, 0x36C / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_0.
-	{ 0x00310032, 0x370 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_1.
-	{ 0x00360034, 0x374 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_2.
-	{ 0x0033002F, 0x378 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_3.
-	{ 0x00000006, 0x37C / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_4.
-	{ 0x00150015, 0x3A4 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ddll_long_cmd_0.
-	{ 0x00120012, 0x3AC / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ddll_long_cmd_2.
-	{ 0x00160016, 0x3B0 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ddll_long_cmd_3.
-	{ 0x00000015, 0x3B4 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ddll_long_cmd_4.
-	{ 0x00000012, 0x49C / 4, DRAM_ID(3) | DRAM_ID(5) | DRAM_ID(6) }, // emc_cmd_brlshft2.
-	{ 0x00000012, 0x4A0 / 4, DRAM_ID(3) | DRAM_ID(5) | DRAM_ID(6) }, // emc_cmd_brlshft3.
-	{ 0x00000210, 0x4F4 / 4, DRAM_ID(5) },              // emc_pmacro_data_rx_term_mode.
-	{ 0x00000005, 0x5C0 / 4, DRAM_ID(5) },              // mc_emem_arb_timing_r2w.
-	{ 0x00000007, 0x5C8 / 4, DRAM_ID(6) },              // mc_emem_arb_timing_rfcpb. Bank refresh.
-	{ 0x72A30504, 0x5D4 / 4, DRAM_ID(6) },              // mc_emem_arb_misc0.
-#endif
+	// Samsung 8GB density config.
+	{ 0x0000003A, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(emc_rfc)                      },
+	{ 0x0000001D, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(emc_rfc_pb)                   },
+	{ 0x0000003B, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(emc_txsr)                     },
+	{ 0x0000003B, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(emc_txsr_dll)                 },
+	{ 0x00080302, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(mc_emem_adr_cfg_dev0)         }, // 1024MB Chip 0 density.
+	{ 0x00080302, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(mc_emem_adr_cfg_dev1)         }, // 1024MB Chip 1 density.
+	{ 0x00002000, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX),  DCFG_OFFSET_OF(mc_emem_cfg)                  }, // 8GB total density. Max 8GB.
 };
+#undef DCFG_OFFSET_OF
--- a/bdk/mem/sdram_config_t210b01.inl
+++ b/bdk/mem/sdram_config_t210b01.inl
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2022 CTCaer
+ * Copyright (c) 2020-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -542,8 +542,8 @@ static const sdram_params_t210b01_t _dram_cfg_08_10_12_14_samsung_hynix_4gb = {

 	/* DRAM size information */
 	.mc_emem_adr_cfg                                 = 0x00000000, // 1 Rank.
-	.mc_emem_adr_cfg_dev0                            = 0x00080302, // Rank 0 Density 1024MB.
-	.mc_emem_adr_cfg_dev1                            = 0x00080302, // Rank 1 Density 1024MB.
+	.mc_emem_adr_cfg_dev0                            = 0x00080302, // Chip 0 Density 1024MB.
+	.mc_emem_adr_cfg_dev1                            = 0x00080302, // Chip 1 Density 1024MB.
 	.mc_emem_adr_cfg_channel_mask                    = 0xFFFF2400,
 	.mc_emem_adr_cfg_bank_mask0                      = 0x6E574400,
 	.mc_emem_adr_cfg_bank_mask1                      = 0x39722800,
@@ -552,7 +552,7 @@ static const sdram_params_t210b01_t _dram_cfg_08_10_12_14_samsung_hynix_4gb = {
 	 * Specifies the value for MC_EMEM_CFG which holds the external memory
 	 * size (in KBytes)
 	 */
-	.mc_emem_cfg                                     = 0x00001000, // 4GB total density.
+	.mc_emem_cfg                                     = 0x00001000, // 4GB total density. Max 8GB.

 	/* MC arbitration configuration */
 	.mc_emem_arb_cfg                                 = 0x08000001,
@@ -595,17 +595,18 @@ static const sdram_params_t210b01_t _dram_cfg_08_10_12_14_samsung_hynix_4gb = {
 	.mc_video_protect_bom_adr_hi                     = 0x00000000,
 	.mc_video_protect_size_mb                        = 0x00000000,

-	// AFI, BPMP, HC, ISP2, CCPLEX, PPCS (AHB), SATA, VI, XUSB_HOST, XUSB_DEV, ADSP, PPCS1 (AHB), DC1, SDMMC1A, SDMMC2A, SDMMC3A.
-	.mc_video_protect_vpr_override                   = 0xE4BAC343,
-	// SDMMC4A, ISP2B, PPCS2 (AHB), APE, SE, HC1, SE1, AXIAP, ETR. Plus SE2, SE2B.
-	.mc_video_protect_vpr_override1                  = 0x06001ED3,
+	// AFI, BPMP, HC, ISP2, CCPLEX, PPCS (AHB), SATA, VI, XUSB_HOST, XUSB_DEV, ADSP, PPCS1 (AHB), DC1, SDMMC1A, SDMMC2A, SDMMC3A. Plus TSEC, NVENC.
+	.mc_video_protect_vpr_override                   = 0xE4FACB43, // Default: 0xE4BAC343.
+	// SDMMC4A, ISP2B, PPCS2 (AHB), APE, SE, HC1, SE1, AXIAP, ETR. Plus SE2, SE2B and TSECB, TSEC1, TSECB1.
+	.mc_video_protect_vpr_override1                  = 0x0600FED3, // Default: 0x06001ED3.

-	.mc_video_protect_gpu_override0                  = 0x00000000,
-	.mc_video_protect_gpu_override1                  = 0x00000000,
+	.mc_video_protect_gpu_override0                  = 0x2A800000, // Default: 0x00000000. Forced to 1 by HOS Secmon.
+	.mc_video_protect_gpu_override1                  = 0x00000002, // Default: 0x00000000. Forced to 0 by HOS Secmon.

 	.mc_sec_carveout_bom                             = 0xFFF00000,
 	.mc_sec_carveout_adr_hi                          = 0x00000000,
 	.mc_sec_carveout_size_mb                         = 0x00000000,
+
 	.mc_video_protect_write_access                   = 0x00000000,
 	.mc_sec_carveout_protect_write_access            = 0x00000000,

@@ -708,100 +709,104 @@ static const sdram_params_t210b01_t _dram_cfg_08_10_12_14_samsung_hynix_4gb = {

 #define DRAM_CC_LPDDR4X_PMACRO_IB      (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ))

-#define DRAM_CC_LPDDR4X_AUTOCAL_VPR    (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ)        | \
+#define DRAM_CC_LPDDR4X_PUPD_VPR       (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ)        | \
 										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE) | \
 										DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL)        | \
 										DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL)        | \
 										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF) | \
 										DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE)       | \
-										DRAM_CC(LPDDR4X_4GB_HYNIX_1A)                       | \
-										DRAM_CC(LPDDR4X_4GB_MICRON_1A)                      | \
-										DRAM_CC(LPDDR4X_4GB_SAMSUNG_1Z))
+										DRAM_CC(LPDDR4X_4GB_HYNIX_H54G46CYRBX267)           | \
+										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB) | \
+										DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL))

-#define DRAM_CC_LPDDR4X_DYN_SELF_CTRL  (DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE) | \
+#define DRAM_CC_LPDDR4X_DSR            (DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE) | \
 										DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL)        | \
 										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF) | \
 										DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE)       | \
-										DRAM_CC(LPDDR4X_4GB_HYNIX_1A)                       | \
-										DRAM_CC(LPDDR4X_4GB_MICRON_1A)                      | \
-										DRAM_CC(LPDDR4X_4GB_SAMSUNG_1Z))
+										DRAM_CC(LPDDR4X_4GB_HYNIX_H54G46CYRBX267)           | \
+										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB) | \
+										DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL))

-#define DRAM_CC_LPDDR4X_QUSE_EINPUT    (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ)        | \
+#define DRAM_CC_LPDDR4X_QUSE           (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ)        | \
 										DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL)        | \
 										DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL)        | \
 										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF) | \
 										DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE)       | \
-										DRAM_CC(LPDDR4X_4GB_HYNIX_1A)                       | \
-										DRAM_CC(LPDDR4X_4GB_MICRON_1A)                      | \
-										DRAM_CC(LPDDR4X_4GB_SAMSUNG_1Z))
+										DRAM_CC(LPDDR4X_4GB_HYNIX_H54G46CYRBX267)           | \
+										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB) | \
+										DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL))

 #define DRAM_CC_LPDDR4X_FAW            (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL)        | \
 										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF) | \
 										DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE)       | \
-										DRAM_CC(LPDDR4X_4GB_MICRON_1A))
+										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB))

 #define DRAM_CC_LPDDR4X_VPR            (DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE)       | \
-										DRAM_CC(LPDDR4X_4GB_HYNIX_1A)                       | \
-										DRAM_CC(LPDDR4X_4GB_MICRON_1A)                      | \
-										DRAM_CC(LPDDR4X_4GB_SAMSUNG_1Z))
+										DRAM_CC(LPDDR4X_4GB_HYNIX_H54G46CYRBX267)           | \
+										DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB) | \
+										DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL))

-#define DRAM_CC_LPDDR4X_SAMSUNG_8GB    (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ)        | \
+#define DRAM_CC_LPDDR4X_8GB            (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ)        | \
 										DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL))

+#define DCFG_OFFSET_OF(m) (OFFSET_OF(sdram_params_t210b01_t, m) / 4)
 static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210b01[] = {

 	// Samsung LPDDR4X 8GB K4UBE3D4AM-MGCJ Die-M for SDEV Iowa and Hoag.
-	{ 0x35353535, 0x350 / 4, DRAM_CC_LPDDR4X_PMACRO_IB }, // emc_pmacro_ib_vref_dq_0.
-	{ 0x35353535, 0x354 / 4, DRAM_CC_LPDDR4X_PMACRO_IB }, // emc_pmacro_ib_vref_dq_1.
-	{ 0x00100010, 0x3FC / 4, DRAM_CC_LPDDR4X_PMACRO_IB }, // emc_pmacro_ib_ddll_long_dqs_rank0_0.
-	{ 0x00100010, 0x400 / 4, DRAM_CC_LPDDR4X_PMACRO_IB }, // emc_pmacro_ib_ddll_long_dqs_rank0_1.
-	{ 0x00100010, 0x404 / 4, DRAM_CC_LPDDR4X_PMACRO_IB }, // emc_pmacro_ib_ddll_long_dqs_rank0_2.
-	{ 0x00100010, 0x408 / 4, DRAM_CC_LPDDR4X_PMACRO_IB }, // emc_pmacro_ib_ddll_long_dqs_rank0_3.
-	{ 0x00100010, 0x40C / 4, DRAM_CC_LPDDR4X_PMACRO_IB }, // emc_pmacro_ib_ddll_long_dqs_rank1_0.
-	{ 0x00100010, 0x410 / 4, DRAM_CC_LPDDR4X_PMACRO_IB }, // emc_pmacro_ib_ddll_long_dqs_rank1_1.
-	{ 0x00100010, 0x414 / 4, DRAM_CC_LPDDR4X_PMACRO_IB }, // emc_pmacro_ib_ddll_long_dqs_rank1_2.
-	{ 0x00100010, 0x418 / 4, DRAM_CC_LPDDR4X_PMACRO_IB }, // emc_pmacro_ib_ddll_long_dqs_rank1_3.
+	{ 0x35353535, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_vref_dq_0)             },
+	{ 0x35353535, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_vref_dq_1)             },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank0_0) },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank0_1) },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank0_2) },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank0_3) },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank1_0) },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank1_1) },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank1_2) },
+	{ 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank1_3) },

 	/*! Shared patched between DRAM Codes. */
-	{ 0x05500000, 0x0D4 / 4, DRAM_CC_LPDDR4X_AUTOCAL_VPR }, // emc_auto_cal_config2.
-	{ 0xC9AFBCBC, 0x0F4 / 4, DRAM_CC_LPDDR4X_AUTOCAL_VPR }, // emc_auto_cal_vref_sel0.
-	{ 0x2A800000, 0x6DC / 4, DRAM_CC_LPDDR4X_AUTOCAL_VPR }, // mc_video_protect_gpu_override0.
-	{ 0x00000002, 0x6E0 / 4, DRAM_CC_LPDDR4X_AUTOCAL_VPR }, // mc_video_protect_gpu_override1.
-	//!TODO Find out what mc_video_protect_gpu_override0 and mc_video_protect_gpu_override1 new bits are.
+	{ 0x05500000, DRAM_CC_LPDDR4X_PUPD_VPR,  DCFG_OFFSET_OF(emc_auto_cal_config2)                },
+	{ 0xC9AFBCBC, DRAM_CC_LPDDR4X_PUPD_VPR,  DCFG_OFFSET_OF(emc_auto_cal_vref_sel0)              },

-	{ 0x88161414, 0x2E0 / 4, DRAM_CC_LPDDR4X_DYN_SELF_CTRL }, // emc_mrw14.
-	{ 0x80000713, 0x32C / 4, DRAM_CC_LPDDR4X_DYN_SELF_CTRL }, // emc_dyn_self_ref_control.
+	// Moved to default config.
+	// { 0x2A800000, DRAM_CC_LPDDR4X_PUPD_VPR,  DCFG_OFFSET_OF(mc_video_protect_gpu_override0)      },
+	// { 0x00000002, DRAM_CC_LPDDR4X_PUPD_VPR,  DCFG_OFFSET_OF(mc_video_protect_gpu_override1)      },

-	{ 0x00000006, 0x1CC / 4, DRAM_CC_LPDDR4X_QUSE_EINPUT }, // emc_quse.
-	{ 0x00000005, 0x1D0 / 4, DRAM_CC_LPDDR4X_QUSE_EINPUT }, // emc_quse_width.
-	{ 0x00000003, 0x1DC / 4, DRAM_CC_LPDDR4X_QUSE_EINPUT }, // emc_einput.
-	{ 0x0000000C, 0x1E0 / 4, DRAM_CC_LPDDR4X_QUSE_EINPUT }, // emc_einput_duration.
+	{ 0x88161414, DRAM_CC_LPDDR4X_DSR,       DCFG_OFFSET_OF(emc_mrw14)                           },
+	{ 0x80000713, DRAM_CC_LPDDR4X_DSR,       DCFG_OFFSET_OF(emc_dyn_self_ref_control)            },

-	{ 0x00000008, 0x24C / 4, DRAM_CC_LPDDR4X_FAW }, // emc_tfaw.
-	{ 0x00000001, 0x670 / 4, DRAM_CC_LPDDR4X_FAW }, // mc_emem_arb_timing_faw.
+	{ 0x00000006, DRAM_CC_LPDDR4X_QUSE,      DCFG_OFFSET_OF(emc_quse)                            },
+	{ 0x00000005, DRAM_CC_LPDDR4X_QUSE,      DCFG_OFFSET_OF(emc_quse_width)                      },
+	{ 0x00000003, DRAM_CC_LPDDR4X_QUSE,      DCFG_OFFSET_OF(emc_einput)                          },
+	{ 0x0000000C, DRAM_CC_LPDDR4X_QUSE,      DCFG_OFFSET_OF(emc_einput_duration)                 },

-	{ 0xE4FACB43, 0x6D4 / 4, DRAM_CC_LPDDR4X_VPR }, // mc_video_protect_vpr_override. + TSEC, NVENC.
-	{ 0x0600FED3, 0x6D8 / 4, DRAM_CC_LPDDR4X_VPR }, // mc_video_protect_vpr_override1. + TSECB, TSEC1, TSECB1.
+	{ 0x00000008, DRAM_CC_LPDDR4X_FAW,       DCFG_OFFSET_OF(emc_tfaw)                            },
+	{ 0x00000001, DRAM_CC_LPDDR4X_FAW,       DCFG_OFFSET_OF(mc_emem_arb_timing_faw)              },

-	{ 0x00000001, 0x134 / 4, DRAM_CC_LPDDR4X_SAMSUNG_8GB }, // emc_adr_cfg. 2 Ranks.
-	{ 0x08010004, 0x2B8 / 4, DRAM_CC_LPDDR4X_SAMSUNG_8GB }, // emc_mrw1.
-	{ 0x08020000, 0x2BC / 4, DRAM_CC_LPDDR4X_SAMSUNG_8GB }, // emc_mrw2.
-	{ 0x080D0000, 0x2C0 / 4, DRAM_CC_LPDDR4X_SAMSUNG_8GB }, // emc_mrw3.
-	{ 0x08033131, 0x2C8 / 4, DRAM_CC_LPDDR4X_SAMSUNG_8GB }, // emc_mrw6.
-	{ 0x080B0000, 0x2CC / 4, DRAM_CC_LPDDR4X_SAMSUNG_8GB }, // emc_mrw8.
-	{ 0x0C0E5D5D, 0x2D0 / 4, DRAM_CC_LPDDR4X_SAMSUNG_8GB }, // emc_mrw9.
-	{ 0x080C5D5D, 0x2D4 / 4, DRAM_CC_LPDDR4X_SAMSUNG_8GB }, // emc_mrw10.
-	{ 0x0C0D0808, 0x2D8 / 4, DRAM_CC_LPDDR4X_SAMSUNG_8GB }, // emc_mrw12.
-	{ 0x0C0D0000, 0x2DC / 4, DRAM_CC_LPDDR4X_SAMSUNG_8GB }, // emc_mrw13.
-	{ 0x08161414, 0x2E0 / 4, DRAM_CC_LPDDR4X_SAMSUNG_8GB }, // emc_mrw14.
-	{ 0x08010004, 0x2E4 / 4, DRAM_CC_LPDDR4X_SAMSUNG_8GB }, // emc_mrw_extra.
-	{ 0x00000000, 0x340 / 4, DRAM_CC_LPDDR4X_SAMSUNG_8GB }, // emc_dev_select. Both devices.
-	{ 0x0051004F, 0x450 / 4, DRAM_CC_LPDDR4X_SAMSUNG_8GB }, // emc_zcal_mrw_cmd.
-	{ 0x40000001, 0x45C / 4, DRAM_CC_LPDDR4X_SAMSUNG_8GB }, // emc_zcal_init_dev1.
-	{ 0x00000000, 0x594 / 4, DRAM_CC_LPDDR4X_SAMSUNG_8GB }, // emc_pmacro_tx_pwrd4.
-	{ 0x00001000, 0x598 / 4, DRAM_CC_LPDDR4X_SAMSUNG_8GB }, // emc_pmacro_tx_pwrd5.
-	{ 0x00000001, 0x630 / 4, DRAM_CC_LPDDR4X_SAMSUNG_8GB }, // mc_emem_adr_cfg. 2 Ranks.
-	{ 0x00002000, 0x64C / 4, DRAM_CC_LPDDR4X_SAMSUNG_8GB }, // mc_emem_cfg. 8GB total density.
-	{ 0x00000002, 0x680 / 4, DRAM_CC_LPDDR4X_SAMSUNG_8GB }, // mc_emem_arb_timing_r2r.
-	{ 0x02020001, 0x694 / 4, DRAM_CC_LPDDR4X_SAMSUNG_8GB }, // mc_emem_arb_da_turns.
+	// Moved to default config.
+	// { 0xE4FACB43, DRAM_CC_LPDDR4X_VPR,       DCFG_OFFSET_OF(mc_video_protect_vpr_override)       }, // + TSEC,  NVENC.
+	// { 0x0600FED3, DRAM_CC_LPDDR4X_VPR,       DCFG_OFFSET_OF(mc_video_protect_vpr_override1)      }, // + TSECB, TSEC1, TSECB1.
+
+	{ 0x00000001, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_adr_cfg)                         }, // 2 Ranks.
+	{ 0x08010004, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw1)                            },
+	{ 0x08020000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw2)                            },
+	{ 0x080D0000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw3)                            },
+	{ 0x08033131, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw6)                            },
+	{ 0x080B0000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw8)                            },
+	{ 0x0C0E5D5D, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw9)                            },
+	{ 0x080C5D5D, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw10)                           },
+	{ 0x0C0D0808, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw12)                           },
+	{ 0x0C0D0000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw13)                           },
+	{ 0x08161414, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw14)                           },
+	{ 0x08010004, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_mrw_extra)                       },
+	{ 0x00000000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_dev_select)                      }, // Both devices.
+	{ 0x0051004F, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_zcal_mrw_cmd)                    },
+	{ 0x40000001, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_zcal_init_dev1)                  },
+	{ 0x00000000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_pmacro_tx_pwrd4)                 },
+	{ 0x00001000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(emc_pmacro_tx_pwrd5)                 },
+	{ 0x00000001, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(mc_emem_adr_cfg)                     }, // 2 Ranks.
+	{ 0x00002000, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(mc_emem_cfg)                         }, // 8GB total density. Max 8GB.
+	{ 0x00000002, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(mc_emem_arb_timing_r2r)              },
+	{ 0x02020001, DRAM_CC_LPDDR4X_8GB,       DCFG_OFFSET_OF(mc_emem_arb_da_turns)                },
 };
+#undef DCFG_OFFSET_OF
--- a/bdk/mem/sdram_param_t210b01.h
+++ b/bdk/mem/sdram_param_t210b01.h
@@ -225,7 +225,6 @@ typedef struct _sdram_params_t210b01_t
 	u32 emc_r2p;
 	/* Specifies the value for EMC_W2P */
 	u32 emc_w2p;
-	/* Specifies the value for EMC_RD_RCD */

 	u32 emc_tppd;
 	u32 emc_trtm;
@@ -235,6 +234,7 @@ typedef struct _sdram_params_t210b01_t
 	u32 emc_tr2ref;
 	u32 emc_ccdmw;

+	/* Specifies the value for EMC_RD_RCD */
 	u32 emc_rd_rcd;
 	/* Specifies the value for EMC_WR_RCD */
 	u32 emc_wr_rcd;
--- a/bdk/mem/smmu.c
+++ b/bdk/mem/smmu.c
@@ -1,7 +1,7 @@
 /*
 * Copyright (c) 2018 naehrwert
 * Copyright (c) 2018 balika011
- * Copyright (c) 2018-2022 CTCaer
+ * Copyright (c) 2018-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -18,156 +18,228 @@

 #include <string.h>

+#include <soc/bpmp.h>
 #include <soc/ccplex.h>
 #include <soc/timer.h>
 #include <soc/t210.h>
 #include <mem/mc_t210.h>
 #include <mem/smmu.h>
-#include <utils/aarch64_util.h>
+#include <memory_map.h>

-bool smmu_used = false;
-u8 *_pageheap = (u8 *)SMMU_HEAP_ADDR;
+/*! SMMU register defines */
+#define SMMU_ASID(asid)          (((asid) << 24u) | ((asid) << 16u) | ((asid) << 8u) | (asid))
+#define SMMU_ENABLE              BIT(31)
+#define SMMU_TLB_ACTIVE_LINES(l) ((l) << 0u)
+#define SMMU_TLB_RR_ARBITRATION  BIT(28)
+#define SMMU_TLB_HIT_UNDER_MISS  BIT(29)
+#define SMMU_TLB_STATS_ENABLE    BIT(31)
+#define SMUU_PTC_INDEX_MAP(m)    ((m) << 0u)
+#define SMUU_PTC_LINE_MASK(m)    ((m) << 8u)
+#define SMUU_PTC_REQ_LIMIT(l)    ((l) << 24u)
+#define SMUU_PTC_CACHE_ENABLE    BIT(29)
+#define SMUU_PTC_STATS_ENABLE    BIT(31)

-//Enabling SMMU requires a TZ secure write: MC(MC_SMMU_CONFIG) = 1;
-u8 smmu_payload[] __attribute__((aligned(16))) = {
-	0x41, 0x01, 0x00, 0x58, // 0x00: LDR  X1, =0x70019010
+/*! Page table defines */
+#define SMMU_4MB_REGION 0
+#define SMMU_PAGE_TABLE 1
+#define SMMU_PDIR_COUNT 1024
+#define SMMU_PTBL_COUNT 1024
+#define SMMU_PAGE_SHIFT 12u
+#define SMMU_PTN_SHIFT  SMMU_PAGE_SHIFT
+#define SMMU_PDN_SHIFT  22u
+#define SMMU_ADDR_TO_PFN(addr) ((addr) >> SMMU_PAGE_SHIFT)
+#define SMMU_ADDR_TO_PTN(addr) ((addr) >> SMMU_PTN_SHIFT)
+#define SMMU_ADDR_TO_PDN(addr) ((addr) >> SMMU_PDN_SHIFT)
+#define SMMU_PTN_TO_ADDR(ptn)  ((ptn)  << SMMU_PTN_SHIFT)
+#define SMMU_PDN_TO_ADDR(pdn)  ((pdn)  << SMMU_PDN_SHIFT)
+#define SMMU_PTB(page, attr) (((attr) << 29u) | ((page) >> SMMU_PAGE_SHIFT))
+
+static void *smmu_heap = (void *)SMMU_HEAP_ADDR;
+
+// Enabling SMMU requires a TZ (EL3) secure write. MC(MC_SMMU_CONFIG) = 1;
+static const u8 smmu_enable_payload[] = {
+	0xC1, 0x00, 0x00, 0x18, // 0x00: LDR  W1, =0x70019010
 	0x20, 0x00, 0x80, 0xD2, // 0x04: MOV  X0, #0x1
 	0x20, 0x00, 0x00, 0xB9, // 0x08: STR  W0, [X1]
 	0x1F, 0x71, 0x08, 0xD5, // 0x0C: IC   IALLUIS
 	0x9F, 0x3B, 0x03, 0xD5, // 0x10: DSB  ISH
 	0xFE, 0xFF, 0xFF, 0x17, // 0x14: B    loop
-	0x00, 0x00, 0x80, 0xD2, // 0x18: MOV  X0, #0x0
-	0x20, 0x00, 0x00, 0xB9, // 0x1C: STR  W0, [X1]
-	0x80, 0x00, 0x00, 0x58, // 0x20: LDR  X0, =0x4002B000
-	0x00, 0x00, 0x1F, 0xD6, // 0x28: BR   X0
-	0x10, 0x90, 0x01, 0x70, // 0x28: MC_SMMU_CONFIG
-	0x00, 0x00, 0x00, 0x00, // 0x2C:
-	0x00, 0x00, 0x00, 0x00, // 0x30: secmon address
-	0x00, 0x00, 0x00, 0x00  // 0x34:
+	0x10, 0x90, 0x01, 0x70, // 0x18: MC_SMMU_CONFIG
 };

-void *page_alloc(u32 num)
+void *smmu_page_zalloc(u32 num)
 {
-	u8 *res = _pageheap;
-	_pageheap += SZ_PAGE * num;
-	memset(res, 0, SZ_PAGE * num);
-	return res;
+	void *page = smmu_heap;
+	memset(page, 0, SZ_PAGE * num);
+
+	smmu_heap += SZ_PAGE * num;
+
+	return page;
 }

-u32 *smmu_alloc_pdir()
+static pde_t *_smmu_pdir_alloc()
 {
-	u32 *pdir = (u32 *)page_alloc(1);
-	for (int pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
-		pdir[pdn] = _PDE_VACANT(pdn);
+	pde_t *pdir = (pde_t *)smmu_page_zalloc(1);
+
+	// Initialize pdes with no permissions.
+	for (u32 pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++)
+		pdir[pdn].huge.page = pdn;
+
 	return pdir;
 }

-void smmu_flush_regs()
+static void _smmu_flush_regs()
 {
 	(void)MC(MC_SMMU_PTB_DATA);
 }

 void smmu_flush_all()
 {
-	MC(MC_SMMU_PTC_FLUSH) = 0;
-	smmu_flush_regs();

+	// Flush the entire page table cache.
+	MC(MC_SMMU_PTC_FLUSH) = 0;
+	_smmu_flush_regs();
+
+	// Flush the entire table.
 	MC(MC_SMMU_TLB_FLUSH) = 0;
-	smmu_flush_regs();
+	_smmu_flush_regs();
 }

-void smmu_init(u32 secmon_base)
+void smmu_init()
 {
 	MC(MC_SMMU_PTB_ASID)   = 0;
 	MC(MC_SMMU_PTB_DATA)   = 0;
-	MC(MC_SMMU_TLB_CONFIG) = 0x30000030;
-	MC(MC_SMMU_PTC_CONFIG) = 0x28000F3F;
+	MC(MC_SMMU_TLB_CONFIG) = SMMU_TLB_HIT_UNDER_MISS | SMMU_TLB_RR_ARBITRATION | SMMU_TLB_ACTIVE_LINES(48);
+	MC(MC_SMMU_PTC_CONFIG) = SMUU_PTC_CACHE_ENABLE | SMUU_PTC_REQ_LIMIT(8) | SMUU_PTC_LINE_MASK(0xF) | SMUU_PTC_INDEX_MAP(0x3F);
 	MC(MC_SMMU_PTC_FLUSH)  = 0;
 	MC(MC_SMMU_TLB_FLUSH)  = 0;
-
-	// Set the secmon address
-	*(u32 *)(smmu_payload + 0x30) = secmon_base;
 }

 void smmu_enable()
 {
-	if (smmu_used)
+	static bool enabled = false;
+
+	if (enabled)
 		return;

-	ccplex_boot_cpu0((u32)smmu_payload);
-	smmu_used = true;
-	msleep(150);
+	// Launch payload on CCPLEX in order to set SMMU enable bit.
+	ccplex_boot_cpu0((u32)smmu_enable_payload, false);
+	msleep(100);
+	ccplex_powergate_cpu0();

 	smmu_flush_all();
+
+	enabled = true;
 }

-bool smmu_is_used()
+void smmu_reset_heap()
 {
-	return smmu_used;
+	smmu_heap = (void *)SMMU_HEAP_ADDR;
 }

-void smmu_exit()
+void *smmu_init_domain(u32 dev_base, u32 asid)
 {
-	*(u32 *)(smmu_payload + 0x14) = _NOP();
-}
-
-u32 *smmu_init_domain4(u32 dev_base, u32 asid)
-{
-	u32 *pdir = smmu_alloc_pdir();
+	void *ptb = _smmu_pdir_alloc();

 	MC(MC_SMMU_PTB_ASID) = asid;
-	MC(MC_SMMU_PTB_DATA) = SMMU_MK_PDIR((u32)pdir, _PDIR_ATTR);
-	smmu_flush_regs();
+	MC(MC_SMMU_PTB_DATA) = SMMU_PTB((u32)ptb, SMMU_ATTR_ALL);
+	_smmu_flush_regs();

-	MC(dev_base) = 0x80000000 | (asid << 24) | (asid << 16) | (asid << 8) | (asid);
-	smmu_flush_regs();
+	// Use the same macro for both quad and single domains. Reserved bits are not set anyway.
+	MC(dev_base) = SMMU_ENABLE | SMMU_ASID(asid);
+	_smmu_flush_regs();

-	return pdir;
+	return ptb;
 }

-u32 *smmu_get_pte(u32 *pdir, u32 iova)
+void smmu_deinit_domain(u32 dev_base, u32 asid)
 {
-	u32 ptn = SMMU_ADDR_TO_PFN(iova);
-	u32 pdn = SMMU_ADDR_TO_PDN(iova);
-	u32 *ptbl;
+	MC(MC_SMMU_PTB_ASID) = asid;
+	MC(MC_SMMU_PTB_DATA) = 0;
+	MC(dev_base)         = 0;
+	_smmu_flush_regs();
+}

-	if (pdir[pdn] != _PDE_VACANT(pdn))
-		ptbl = (u32 *)((pdir[pdn] & SMMU_PFN_MASK) << SMMU_PDIR_SHIFT);
+void smmu_domain_bypass(u32 dev_base, bool bypass)
+{
+	if (bypass)
+	{
+		smmu_flush_all();
+		bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false);
+		MC(dev_base) &= ~SMMU_ENABLE;
+	}
 	else
 	{
-		ptbl = (u32 *)page_alloc(1);
+		bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false);
+		MC(dev_base) |=  SMMU_ENABLE;
+		smmu_flush_all();
+	}
+	_smmu_flush_regs();
+}
+
+static pte_t *_smmu_get_pte(pde_t *pdir, u32 iova)
+{
+	u32 pdn = SMMU_ADDR_TO_PDN(iova);
+	pte_t *ptbl;
+
+	// Get 4MB page table or initialize one.
+	if (pdir[pdn].tbl.attr)
+		ptbl = (pte_t *)(SMMU_PTN_TO_ADDR(pdir[pdn].tbl.table));
+	else
+	{
+		// Allocate page table.
+		ptbl = (pte_t *)smmu_page_zalloc(1);
+
+		// Get address.
 		u32 addr = SMMU_PDN_TO_ADDR(pdn);
-		for (int pn = 0; pn < SMMU_PTBL_COUNT; pn++, addr += SMMU_PAGE_SIZE)
-			ptbl[pn] = _PTE_VACANT(addr);
-		pdir[pdn] = SMMU_MK_PDE((u32)ptbl, _PDE_ATTR | _PDE_NEXT);
+
+		// Initialize page table with no permissions.
+		for (u32 pn = 0; pn < SMMU_PTBL_COUNT; pn++, addr += SZ_PAGE)
+			ptbl[pn].page = SMMU_ADDR_TO_PFN(addr);
+
+		// Set page table to the page directory.
+		pdir[pdn].tbl.table = SMMU_ADDR_TO_PTN((u32)ptbl);
+		pdir[pdn].tbl.next  = SMMU_PAGE_TABLE;
+		pdir[pdn].tbl.attr  = SMMU_ATTR_ALL;
+
 		smmu_flush_all();
 	}

-	return &ptbl[ptn % SMMU_PTBL_COUNT];
+	return &ptbl[SMMU_ADDR_TO_PTN(iova) % SMMU_PTBL_COUNT];
 }

-void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr)
+void smmu_map(void *ptb, u32 iova, u64 iopa, u32 pages, u32 attr)
 {
-	for (int i = 0; i < cnt; i++)
+	// Map pages to page table entries. VA/PA should be aligned to 4KB.
+	for (u32 i = 0; i < pages; i++)
 	{
-		u32 *pte = smmu_get_pte(pdir, addr);
-		*pte = SMMU_ADDR_TO_PFN(page) | attr;
-		addr += SZ_PAGE;
-		page += SZ_PAGE;
+		pte_t *pte = _smmu_get_pte((pde_t *)ptb, iova);
+
+		pte->page = SMMU_ADDR_TO_PFN(iopa);
+		pte->attr = attr;
+
+		iova += SZ_PAGE;
+		iopa += SZ_PAGE;
 	}
+
 	smmu_flush_all();
 }

-u32 *smmu_init_for_tsec()
+void smmu_map_huge(void *ptb, u32 iova, u64 iopa, u32 regions, u32 attr)
 {
-	return smmu_init_domain4(MC_SMMU_TSEC_ASID, 1);
-}
+	pde_t *pdir = (pde_t *)ptb;

-void smmu_deinit_for_tsec()
-{
-	MC(MC_SMMU_PTB_ASID)  = 1;
-	MC(MC_SMMU_PTB_DATA)  = 0;
-	MC(MC_SMMU_TSEC_ASID) = 0;
-	smmu_flush_regs();
-}
+	// Map 4MB regions to page directory entries. VA/PA should be aligned to 4MB.
+	for (u32 i = 0; i < regions; i++)
+	{
+		u32 pdn = SMMU_ADDR_TO_PDN(iova);
+		pdir[pdn].huge.page = SMMU_ADDR_TO_PDN(iopa);
+		pdir[pdn].huge.next = SMMU_4MB_REGION;
+		pdir[pdn].huge.attr = attr;

+		iova += SZ_4M;
+		iopa += SZ_4M;
+	}
+
+	smmu_flush_all();
+}
--- a/bdk/mem/smmu.h
+++ b/bdk/mem/smmu.h
@@ -1,5 +1,6 @@
 /*
 * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018-2024 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
@@ -14,70 +15,57 @@
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

+#include <assert.h>
+
 #include <utils/types.h>

-#define SMMU_HEAP_ADDR 0xA0000000
-
-#define MC_INTSTATUS                 0x0
-#define MC_INTMASK                   0x4
-#define MC_ERR_STATUS                0x8
-#define MC_ERR_ADR                   0xc
-#define MC_SMMU_CONFIG               0x10
-#define MC_SMMU_TLB_CONFIG           0x14
-#define MC_SMMU_PTC_CONFIG           0x18
-#define MC_SMMU_PTB_ASID             0x1c
-#define MC_SMMU_PTB_DATA             0x20
-#define MC_SMMU_TLB_FLUSH            0x30
-#define MC_SMMU_PTC_FLUSH            0x34
-#define MC_SMMU_ASID_SECURITY        0x38
 #define MC_SMMU_AVPC_ASID            0x23C
 #define MC_SMMU_TSEC_ASID            0x294
-#define MC_SMMU_TRANSLATION_ENABLE_0 0x228
-#define MC_SMMU_TRANSLATION_ENABLE_1 0x22c
-#define MC_SMMU_TRANSLATION_ENABLE_2 0x230
-#define MC_SMMU_TRANSLATION_ENABLE_3 0x234
-#define MC_SMMU_TRANSLATION_ENABLE_4 0xb98

-#define SMMU_PDE_NEXT_SHIFT 28
-#define MC_SMMU_PTB_DATA_0_ASID_NONSECURE_SHIFT 29
-#define MC_SMMU_PTB_DATA_0_ASID_WRITABLE_SHIFT  30
-#define MC_SMMU_PTB_DATA_0_ASID_READABLE_SHIFT  31
-#define SMMU_PAGE_SHIFT 12
-#define SMMU_PAGE_SIZE  (1 << SMMU_PAGE_SHIFT)
-#define SMMU_PDIR_COUNT 1024
-#define SMMU_PDIR_SIZE  (sizeof(u32) * SMMU_PDIR_COUNT)
-#define SMMU_PTBL_COUNT 1024
-#define SMMU_PTBL_SIZE  (sizeof(u32) * SMMU_PTBL_COUNT)
-#define SMMU_PDIR_SHIFT 12
-#define SMMU_PDE_SHIFT  12
-#define SMMU_PTE_SHIFT  12
-#define SMMU_PFN_MASK   0x000FFFFF
-#define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12)
-#define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22)
-#define SMMU_PDN_TO_ADDR(addr) ((pdn) << 22)
-#define _READABLE  (1 << MC_SMMU_PTB_DATA_0_ASID_READABLE_SHIFT)
-#define _WRITABLE  (1 << MC_SMMU_PTB_DATA_0_ASID_WRITABLE_SHIFT)
-#define _NONSECURE (1 << MC_SMMU_PTB_DATA_0_ASID_NONSECURE_SHIFT)
-#define _PDE_NEXT  (1 << SMMU_PDE_NEXT_SHIFT)
-#define _MASK_ATTR (_READABLE | _WRITABLE | _NONSECURE)
-#define _PDIR_ATTR (_READABLE | _WRITABLE | _NONSECURE)
-#define _PDE_ATTR  (_READABLE | _WRITABLE | _NONSECURE)
-#define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR)
-#define _PTE_ATTR  (_READABLE | _WRITABLE | _NONSECURE)
-#define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
-#define SMMU_MK_PDIR(page, attr) (((page) >> SMMU_PDIR_SHIFT) | (attr))
-#define SMMU_MK_PDE(page, attr)  (((page) >> SMMU_PDE_SHIFT) | (attr))
+#define SMMU_NS    BIT(0)
+#define SMMU_WRITE BIT(1)
+#define SMMU_READ  BIT(2)
+#define SMMU_ATTR_ALL (SMMU_READ | SMMU_WRITE | SMMU_NS)

-void *page_alloc(u32 num);
-u32 *smmu_alloc_pdir();
-void smmu_flush_regs();
-void smmu_flush_all();
-void smmu_init(u32 secmon_base);
-void smmu_enable();
-bool smmu_is_used();
-void smmu_exit();
-u32 *smmu_init_domain4(u32 dev_base, u32 asid);
-u32 *smmu_get_pte(u32 *pdir, u32 iova);
-void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr);
-u32 *smmu_init_for_tsec();
-void smmu_deinit_for_tsec();
+typedef struct _pde_t {
+	union {
+		union {
+			struct {
+				u32 table:22;
+				u32 rsvd:6;
+				u32 next:1;
+				u32 attr:3;
+			} tbl;
+
+			struct {
+				u32 rsvd_:10;
+				u32 page:12;
+				u32 rsvd:6;
+				u32 next:1;
+				u32 attr:3;
+			} huge;
+		};
+
+		u32 pde;
+	};
+} pde_t;
+
+typedef struct _pte_t {
+	u32 page:22;
+	u32 rsvd:7;
+	u32 attr:3;
+} pte_t;
+
+static_assert(sizeof(pde_t) == sizeof(u32), "pde_t size is wrong!");
+static_assert(sizeof(pte_t) == sizeof(u32), "pte_t size is wrong!");
+
+void *smmu_page_zalloc(u32 num);
+void  smmu_flush_all();
+void  smmu_init();
+void  smmu_enable();
+void  smmu_reset_heap();
+void *smmu_init_domain(u32 dev_base, u32 asid);
+void  smmu_deinit_domain(u32 dev_base, u32 asid);
+void  smmu_domain_bypass(u32 dev_base, bool bypass);
+void  smmu_map(void *ptb, u32 iova, u64 iopa, u32 pages, u32 attr);
+void  smmu_map_huge(void *ptb, u32 iova, u64 iopa, u32 regions, u32 attr);