@@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2023 CTCaer
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* Copyright (c) 2018-2024 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -42,6 +42,26 @@ static bool _nx_aula = false;
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static void _display_panel_and_hw_end(bool no_panel_deinit);
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void display_enable_interrupt(u32 intr)
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{
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DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) |= intr;
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}
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void display_disable_interrupt(u32 intr)
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{
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DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) &= ~intr;
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DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = intr;
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}
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void display_wait_interrupt(u32 intr)
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{
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DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = intr;
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// Interrupts are masked. Poll status register for checking if fired.
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while (!(DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) & intr))
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;
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}
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static void _display_dsi_wait(u32 timeout, u32 off, u32 mask)
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{
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u32 end = get_tmr_us() + timeout;
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@@ -64,22 +84,18 @@ static void _display_dsi_wait_vblank(bool enable)
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if (enable)
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{
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// Enable vblank interrupt.
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DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) = DC_CMD_INT_FRAME_END_INT;
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display_enable_interrupt(DC_CMD_INT_FRAME_END_INT);
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// Use the 4th line to transmit the host cmd packet.
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = DSI_CMD_PKT_VID_ENABLE | DSI_DSI_LINE_TYPE(4);
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// Wait for vblank before starting the transfer.
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DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT; // Clear interrupt.
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while (!(DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) & DC_CMD_INT_FRAME_END_INT))
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;
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display_wait_interrupt(DC_CMD_INT_FRAME_END_INT);
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}
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else
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{
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// Wait for vblank before resetting sync points.
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DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT; // Clear interrupt.
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while (!(DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) & DC_CMD_INT_FRAME_END_INT))
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;
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display_wait_interrupt(DC_CMD_INT_FRAME_END_INT);
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usleep(14);
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// Reset all states of syncpt block.
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@@ -94,8 +110,7 @@ static void _display_dsi_wait_vblank(bool enable)
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0;
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// Disable and clear vblank interrupt.
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DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) = 0;
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DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT;
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display_disable_interrupt(DC_CMD_INT_FRAME_END_INT);
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}
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}
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@@ -383,10 +398,10 @@ void display_init()
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_DISP1);
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = BIT(CLK_X_UART_FST_MIPI_CAL);
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL) = 10; // Set PLLP_OUT3 and div 6 (17MHz).
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL) = CLK_SRC_DIV(6); // Set PLLP_OUT3 and div 6 (17MHz).
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_SET) = BIT(CLK_W_DSIA_LP);
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP) = 10; // Set PLLP_OUT and div 6 (68MHz).
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP) = CLK_SRC_DIV(6); // Set PLLP_OUT and div 6 (68MHz).
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// Bring every IO rail out of deep power down.
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PMC(APBDEV_PMC_IO_DPD_REQ) = PMC_IO_DPD_REQ_DPD_OFF;
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